CN111480236A

CN111480236A - Directly bonded optoelectronic interconnects for high density integrated photonic devices

Info

Publication number: CN111480236A
Application number: CN201880080463.XA
Authority: CN
Inventors: 王亮; R·卡特卡尔
Original assignee: Evanss Adhesive Technologies
Current assignee: Evanss Adhesive Technologies
Priority date: 2017-12-15
Filing date: 2018-12-14
Publication date: 2020-07-31
Also published as: US11011503B2; US20190189603A1; WO2019118846A1; US20210265331A1

Abstract

The present invention provides a direct bonded optoelectronic interconnect for high density integrated photonic devices.A combined electrical interconnect and optical interconnect enables direct bonding of a fully processed optoelectronic die or wafer to a wafer using optoelectronic driver circuitry.A photonic device can be a III-V semiconductor device.A direct bond to a silicon or silicon-on-insulator (SOI) wafer enables integration of the photonic device with high density CMOS and other microelectronic packages.

Description

Directly bonded optoelectronic interconnects for high density integrated photonic devices

RELATED APPLICATIONS

This patent application claims the benefit of priority from U.S. non-provisional patent application No. 16/219,693 filed on day 13, 12, 2018 and U.S. provisional patent application No. 62/599,146 filed on day 15, 12, 2017, which are incorporated herein by reference in their entirety.

Background

Silicon has become an important component of optoelectronic devices as a good conductor of infrared light and has many technical and economic advantages. Silicon photonics combine the advantages of photonics with the widespread use of silicon in conventional CMOS fabrication. Photonic devices offer high performance communication, low operating power, and smaller size and weight. CMOS offers mass production, low cost, miniaturization, and high integration. Thus, silicon photonics devices provide high integration, miniaturization, higher bandwidth, lower cost, and lower operating power. Micro-photonic integration using silicon photonics devices reduces the cost of optical links.

Compound semiconductors used for optoelectronic devices and silicon optoelectronic devices combine elements of group III of the periodic table (e.g., In, Ga, Al) with elements of group V of the periodic table (e.g., As, P, Sb, N). This produces twelve different III-V compounds, but the most commercially available of these are GaAs, InP, GaN, and GaP.

Silicon photonics circuits most often operate in infrared light at 1550nm wavelength, at which silicon becomes a good conduit for transmission of infrared light beams. Due to the different refractive indices of silicon and silicon dioxide, on a waveguide structure made of silicon, the top and bottom cladding layers of silicon dioxide (silica) confine infrared light within the silicon by Total Internal Reflection (TIR), similar in some respects to how light is conducted in a fiber optic filament. Silicon photonic devices using such silicon waveguides may be constructed by semiconductor fabrication techniques previously dedicated to microelectronic devices. Since silicon has been used as a substrate in most conventional microelectronic integrated circuits, hybrid devices in which optical and electronic components are integrated onto a single microchip can be manufactured using conventional semiconductor manufacturing processes, sometimes even without rework.

The process of fabricating photonic devices using silicon and silicon dioxide may also utilize conventional silicon-on-insulator (SOI) technology, well known in microelectronics, to provide an SOI waveguide layer on the wafer to which optical dies such as L ED, lasers and photodetectors may be conventionally attached by less than ideal means.

Silicon photonics based platforms that can facilitate highly integrated electron-photon fusion face several obstacles. Thick transparent substrates, such as sapphire or indium phosphide (InP), are often not bonded to silicon wafers due to optical mode matching requirements. This is because III-V compound semiconductors, while providing more powerful functions than silicon, are generally derived from different sources with different matrix materials. Thus, instead of conventional bonding, flip chip and/or die-to-wafer (D2W) interconnect and packaging techniques are commonly used to bond such optical dies to silicon wafers. The integration of die and III-V compound semiconductors onto silicon chips requires die-to-wafer bonding, but the bulky solder interconnect characteristics of these technologies hinder the optical path. The options for using these solder interconnects and applying mirror optics for compensation are complex and expensive. Thus, to avoid solder interconnections, fabrication in conventional photonic devices typically bonds an unprocessed photonic die to a silicon wafer, but then metal contacts for the optoelectronic device must be fabricated on the die in a retrospective front-end step after the die has been bonded to the wafer.

Since the die with III-V compound semiconductors are typically not fully processed before bonding to the silicon wafer, it may not be possible to optimize the process by selecting a known good die, so the front end process must be performed after the die has been bonded to the wafer. After the die is bonded to the wafer, photolithography on the topographic surface of the die has limited accuracy and cannot scale to high density.

Disclosure of Invention

Direct bonded optoelectronic interconnects are also useful in other wafer-level manufacturing processes that bond organic L ED (O L ED) or quantum dot L ED on a first wafer to CMOS driver circuitry on a second wafer.

L each bonding surface of the ED wafer or chip and the CMOS wafer or chip to be directly bonded has an optical window to be coupled by direct bonding.

Exemplary optoelectronic interconnects can be used to construct photonic devices, including, but not limited to, Photonic Integrated Circuits (PICs) (also known as photonic integrated circuits) and planar lightwave circuits (P L C). furthermore, optoelectronic interconnects can be used to fabricate optical devices, for example, for fiber optic communications, optical computing, for medical applications, including minimally invasive scanner probes, for aerospace and automotive applications, such as optical sensors for sensing changes in the shape of flexures, and optical metrology.

This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

Drawings

Certain embodiments of the present disclosure will hereinafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements. It should be understood, however, that the drawings illustrate various implementations described herein and are not intended to limit the scope of the various techniques described herein.

Fig. 1 is a schematic diagram of an optoelectronic die with III-V semiconductor components on the optoelectronic die and metallization completed, and finished electrodes bonded directly to the wafer to fabricate photonic devices integrated with high density microelectronic devices.

FIG. 2 is a side view of an exemplary optoelectronic interconnect implemented by direct bonding in a single direct bonding plane.

Fig. 3 is a top view of an exemplary optoelectronic die and an exemplary corresponding direct bonding plane of an exemplary silicon or silicon-on-insulator (SOI) wafer that are directly bonded together to form an exemplary optoelectronic interconnect.

FIG. 4 is a schematic view of an exemplary optoelectronic interconnect in which the first electrical contact of the photonic device and the second electrical contact of the photonic device are each a single metal pad to be directly bonded.

FIG. 5 illustrates an embodiment of an exemplary optoelectronic interconnect, wherein the first electrical contact of the photonic device and the second electrical contact of the photonic device are each one or more metal pads on two or more sides outside of the optical region to be directly bonded.

FIG. 6 illustrates an exemplary photonic device, wherein the photonic device such as L ED, m L ED, or a laser source is arrayed on a wafer using exemplary optoelectronic interconnects.

FIG. 7 illustrates another exemplary photonic device in which a photonic device such as an L ED, m L ED, or laser source is arrayed on a wafer using exemplary optoelectronic interconnects.

Fig. 8 is a flow chart of an exemplary method of forming a flat bonding interface suitable for directly bonding a die (which includes a photonic device, such as a photonic device utilizing III-V semiconductor compounds) to a wafer, such as a silicon or SOI wafer, to form optoelectronic interconnects for high density integrated photonic devices.

FIG. 9 is a flow chart of another exemplary method of bonding a die (which includes a photonic device utilizing a III-V semiconductor compound) to a silicon or SOI wafer to form an optoelectronic interconnect for high density integrated photonic devices.

Detailed Description

The present disclosure describes direct bonded optoelectronic interconnects for high density integrated photonic devices.A combined electrical and optical interconnect enables direct bonding of fully processed optoelectronic dies or wafers including III-V semiconductor devices, O L ED or quantum dots L ED to silicon, or silicon-on-insulator (SOI) wafers, particularly CMOS wafers carrying IC driver circuitry, with or without built-in silicon or other optical waveguides.

In this specification, the term L ED for "light emitting diode" also encompasses micro L ED and various types of L ED, such as phosphor-based L ED, III-V semiconductor L ED, O L ED, quantum dot L ED, and the like.

The wafers used in exemplary processes may be silicon or silicon-on-insulator (SOI) wafers, or may be made of other materials such as quartz, polymers, etc., and may contain silicon waveguides or other waveguides utilizing, for example, infrared light. The exemplary electrical and optical interconnects described herein are not limited to silicon-on-insulator (SOI) wafers, but SOI wafers are used as working examples.

The first and second flat bonding surfaces of the die and wafer to be bonded are made sufficiently flat for a direct bonding process. The respective optical windows of the die and wafer are directly bonded to each other across the bonding interface by, for example, a dielectric-to-dielectric (or oxide-oxide) direct bonding process. Corresponding coplanar metallic electrical contacts are also directly bonded to each other across the same bonding interface using a metal-to-metal direct bonding process. When direct-mix bonding is utilized (e.g.,

) Non-metallic direct bonding and subsequent metallic direct bonding results in the formation of a directly bonded optoelectronic interconnect between a die carrying a photonic III-V semiconductor device on one side and a silicon or SOI wafer carrying optoelectronic circuits on the other side.

In one embodiment, the mating metal contacts on either side of the bonding interface between the die and wafer or wafer and wafer are in a different bonding region than the optical path provided by the optical region to be interconnected by direct bonding, while remaining coplanar with the optical region, so that both the optical and electrical interconnects formed in one bonding operation have only one flat bonding interface. In one embodiment, the electrical contacts that are directly bonded between the surfaces are coplanar with and external to the respective optical regions of the surfaces that are directly bonded together. In another embodiment, the electrical contacts that are directly bonded across the optoelectronic interconnect are coplanar with and at least partially circumscribe the respective optical regions that are being directly bonded together. The combined optical and electrical interconnects enable high density integration of photonic devices into microelectronic packages, as the employed adhesive-free dielectric-to-dielectric bonding and solder-free metal-to-metal bonding can form high density electrical interconnects on the same bonding interface as the bonded optical interconnects, and can scale to high densities.

Fig. 1 shows an optoelectronic die 100, such as a fully processed optoelectronic die 100, with III-V semiconductor optics on the optoelectronic die and metallization completed, and finished electrodes bonded to an exemplary silicon wafer or an exemplary silicon-on-insulator (SOI) wafer 102, for example, using die-to-wafer (D2W) techniques. The arrangement of electrical contacts between the die 100 and the wafer 102, and the arrangement of the optical area that will also interconnect between the die 100 and the wafer 102, enables the conductive contacts of the die 100 to be directly metal-to-metal bonded without solder, while the dielectric surface of the optical area is also directly bonded between the die 100 and the wafer 102 without adhesive. The solder-free process and absence of bulk solder enables the formation of high density electrical interconnects on the same planar bonding interface as the optical interconnects being formed. In addition, the finished optoelectronic die 100 may be used for die-to-wafer bonding operations. Although the finished optic 100 is shown in fig. 1 as bonded to a silicon or SOI wafer 102, the finished optic wafer may alternatively be hybrid bonded directly to a silicon, glass, quartz, or SOI wafer.

In a wafer-to-wafer (W2W) process, L ED 104 or micro L ED (m L ED)104 may be formed or reconstituted on wafer 106 or reconstituted wafer and then bonded directly to another wafer 102 using the exemplary optoelectronic interconnects described herein the wafer 102 being bonded may possess, for example, CMOS driver circuitry with optical waveguides.

Fig. 2 shows an embodiment of an exemplary combined electrical interconnect and optical ("optoelectronic") interconnect 200 for a high density integrated photonic device in one embodiment, an exemplary die 100 includes an optoelectronic device 202 and an optical coupling region 204 of the die 100 in optical communication with the optoelectronic device 202 the die 100 may be a fully processed III-V die of a laser, photodiode, L ED, etc. the exemplary die 100 has a coupling plane 206 (also shown in fig. 3) for optically and electrically coupling with a complementary coupling plane 208 of the wafer 102, such as a silicon-on-insulator (SOI) wafer, silicon, glass, or other wafer, a section of the coupling plane 206 of the die 100 contains the optical coupling region 204 of the die 100. an exemplary directly bonded L ED array and an interconnect applied in U.S. patent application No. 15/919,570 to Tao et al, filed 3.13.2018, which is incorporated by reference herein in its entirety.

The coupling plane 206 of the die 100 and the coupling plane 208 of the wafer 102 are provided with a high degree of physical flatness suitable for direct bonding of metals and non-metals in the bonding planes 206 and 208, respectively. This planarity may be achieved by fabrication or by polishing, such as by Chemical Mechanical Planarization (CMP).

The first electrical contact 212 of the optoelectronic device 202 is disposed outside the perimeter of the optical coupling region 204, within the coupling plane 206 of the die 100. The first electrical contact 212 is located outside of, and in some cases may completely or at least partially surround, the outer perimeter of the optical coupling region 204 in the coupling plane 206 of the die 100. The second electrical contacts 214 of the optoelectronic device 202 are also disposed outside the perimeter of the optical coupling region 204 and, in some cases, outside the perimeter of the first electrical contacts 212 in the coupling plane 206 of the die 100. The second electrical contact 214 may at least partially surround the first electrical contact 212 when the second electrical contact 214 is positioned beyond the outer perimeter of the first electrical contact 212. In one embodiment, the first ("inner") electrical contact 212 completely surrounds the optical coupling region 204, with an uninterrupted perimeter of metal traces in the coupling plane 206 of the die 100. In another embodiment, as shown later in fig. 4-5, the first electrical contact 212 and the second electrical contact 214 may be pads or contact point connectors for direct bonding that are located only in a different region of the bonding interface than the optical bonding region 204.

The first electrical contact 212 of the die 100 (or optics wafer) is also configured to match a complementary electrical contact 222 on the wafer 102 that is being bonded outside the area or perimeter of the complementary optical coupling region 216 of the wafer 102. This places both complementary

electrical contacts

212 and 222 outside of the perimeter or optical footprint of the silicon waveguide 218 in or below the optical coupling region 216 of the wafer 102.

In the example shown, from the perspective of the flat bottom wafer side 208 of the bonding interface 200, the instances of the example die 100 are able to optically and electrically couple with the wafer 102 when the

respective coupling planes

206 and 208 of the die 100 and the wafer 102 are bonded. The optical coupling region 216 of the wafer 102 occupies a flat section of the coupling plane 208 of the wafer 102. For each die-to-wafer bonding site, wafer 102 has a respective silicon waveguide 218 that is in optical communication with optical coupling region 216 of wafer 102 (i.e., above silicon waveguide 218).

Wafer 102 has optoelectronic circuits 220 and 220' or other circuitry to connect to the electronics of die 100 across bonding interface 200. Although the optoelectronic circuits 220 and 220' are depicted on the bonding surface 208, they may be located below the bonding surface 208 or embedded in or below the bonding surface. The first electrical contact 222 of the optoelectronic circuit 220 of the wafer 102 is complementary in planar geometry in the bonding plane 208 to the first electrical contact 212 in the coupling plane 206 of the die 100 (see also fig. 3). The first complementary electrical contacts 222 of the wafer 102 are collectively disposed in the coupling plane 208 of the wafer 102 and outside the perimeter of the optical coupling region 216 of the wafer 102.

In the illustrated embodiment, the second electrical contact 224 of the optoelectronic circuit 220 of the wafer 102 is disposed outside the perimeter of the first electrical contact 222 of the wafer 102, and is also disposed in the planar coupling plane 208 of the wafer 102. The second electrical contact 222 is complementary in flat profile to a corresponding second electrical contact 214 of the die 100 to which it is to be bonded via a metal-to-metal direct bond.

Electrical routing paths (leads, wires, traces) from the optoelectronic circuit 220 of the wafer 102 to the first and second complementary

electrical contacts

222, 224 of the wafer 102 may also be within or directly below the coupling plane 208 of the wafer 102, as described above.

The optical coupling region 216 of wafer 102 may include at least a grating surface 226 for optical mode-matching coupling between the optics of die 100 and the silicon waveguide 218 of wafer 102. In one embodiment, the grating surface 226 may be less than 10 microns (μ) wide for single mode infrared transmission in the silicon waveguide 218.

As described above, the die 100 has fully processed electrodes for the optoelectronic devices 202 on the die 100 and has fully processed first and second

electrical contacts

212 and 214 for electrical interconnection with corresponding

electrical contacts

222 and 224 on the flat bonding interface 208 of the wafer 102. When the coupling plane 206 of the die 100 is bonded with the coupling plane 208 of the wafer 102, optical coupling and metal-to-metal electrical coupling occur with the same bonding operation at the combined coupling planes 206 and 208 ("coupling planes" or "optoelectronic interconnects" 200) that are being bonded.

Direct hybrid bonding operations (such as exemplary

Direct hybrid bonding) may be used to achieve non-metallic dielectric-to-dielectric direct bonding (e.g., oxide-to-oxide direct bonding), the non-metals constituting the surfaces of the complementary

optical regions

204 and 216 of the die 100 and the wafer 102. The annealing step of the same exemplary direct hybrid bonding process also directly bonds the corresponding metal electrodes together and strengthens all direct bonds formed in the exemplary direct hybrid bonding processAnd (6) mixing.

The coupling plane 200 at the bonding interfaces 206 and 208 enables optical coupling between the optical coupling region 204 of the die 100 and the optical coupling region 216 of the wafer 102 that fits in the bonded coupling plane 200. The coupling plane 200 at the bonding interface also includes a metal-to-metal direct bond between the first electrical contact 212 of the die 100 and the complementary electrical contact 222 of the wafer 102, and also includes a metal-to-metal direct bond between the second electrical contact 214 of the die 100 and the complementary electrical contact 224 of the wafer 102.

For example, a Transparent Conductive Oxide (TCO)228 or other similar film may be added between the III-V compound semiconductor (or optical device) 202 and the silicon waveguide 218 to enhance conductivity in the III-V compound semiconductor 202 or to enhance uniformity of conductivity in the III-V compound semiconductor 202 if desired.

In one embodiment, reflective losses may be reduced by roughening the bottom surface of the III-V compound semiconductor or optical device 202, for example, by etching. In another technique for reducing reflection losses, a selected dielectric material between the bottom surface of III-V compound semiconductor 202 and silicon waveguide 218 may be used to reduce reflection losses between III-V compound semiconductor 202 and silicon waveguide 218. In one embodiment, the refractive index of the dielectric material to be used is approximately equal to the square root of the refractive index of silicon 218 multiplied by the refractive index of the III-V compound semiconductor material 202. In another embodiment, the dielectric material has a refractive index in a range between the refractive index of silicon 218 and the refractive index of the III-V compound semiconductor 202.

Thus, some common refractive indices of dielectrics and semiconductors that can also be used to reduce reflection losses in exemplary optoelectronic interconnects are:

for example, TiO₂Can be used as an intermediate dielectric material to reduce reflection loss. Depending on the III-V compound semiconductor 202 present, dielectric materials such as aluminum doped zinc oxide (AZO) may also be used) And gallium doped zinc oxide (ZNO). It is also possible that the optical interconnect is located between silicon oxide and GaN, as silicon oxide can act as an optical waveguide.

The optical components of the optoelectronic interconnect 200 can also be optimized by configuring the optical thickness between the bottom surface of the III-V compound semiconductor 202 and the top surface of the silicon waveguide 218. The thickness may be an odd multiple of one quarter of the wavelength of the operating light (such as infrared light at 1550 nm) used in each photonic device formed by bonding optoelectronic die 100 and wafer 102.

Depending on the thickness of the substrate 230 of the die 100 to be bonded to the wafer 102, layers of the substrate 230 may be removed by laser lift-off, grinding, etching, etc. to thin the die 100 being bonded. A reflective layer, metal, or Distributed Bragg Reflector (DBR)232 may then be added on top of the optoelectronic device 202 of the die 100, for example, to keep the light contained and advantageously reflected into the optoelectronic device 202 on the die 100.

Fig. 3 shows a top view (or bottom view) of

exemplary bonding planes

206 and 208 of the respective die 100 and wafer 102 that form the exemplary optoelectronic interconnect 200. In contrast, fig. 2 shows a side view. This configuration of

electrodes

212 and 222 and 214 and 224 that would be directly bonded together is merely one exemplary configuration. Other exemplary configurations are shown in fig. 4-5.

In fig. 3, in an exemplary embodiment, a first coupling plane 206 formed on one side of the die 100 has a first optical bonding region 204 formed in the coupling plane 206, a first electrical contact 212 (also disposed in the coupling plane 206 of the die 100) around the outer periphery of the first optical window 204, and a second electrical contact 214 around the outer periphery of the first "inner" electrical contact 212, all of which are disposed in the coupling plane 206 of the die 100.

The wafer side bonding plane 208 of the optical interconnect 200 and the electrical interconnect for the high density integrated photonic device includes a wafer side optical window 216 in the coupling plane 208, a first electrical contact 222 of the wafer 102 outside the perimeter of the optical window 216, a second electrical contact 224 of the wafer 102 outside the perimeter of the first electrical contact 222, and

electrical leads

302 and 304 connected to the first electrical contact 222 and the second electrical contact 224, respectively, all disposed in the coupling plane 208 of the wafer 102.

In one embodiment, the second complementary electrical contact 224 of the optoelectronic circuit 220 of the wafer 102 is in an open loop or other discontinuous planar shape in the coupling plane 208 of the wafer 102 and has a gap 300 in its open loop or discontinuous form for accommodating electrical routing 302 from the circuit 220 to the first complementary electrical contact 222 in the coupling plane 208 of the wafer 102. The gap 300 allows the second electrical contact 224 to remain electrically isolated from the lead 302 or other electrically conductive wire leading to the first electrical contact 222 of the optoelectronic circuit 220.

The first electrical contact 212 of the die 100 and the first complementary electrical contact 222 of the wafer 102 may each be, for example, a conductive line or trace or ring in the form of a square, rectangle, circle, or oval surrounding the respective first and second

optical windows

204, 216.

The electrical and optical interconnects 200 for high density integrated photonic devices have a dielectric-to-dielectric directly bonded optical interconnect between the (first) optical window 204 of the die 100 and the (second) optical window 216 of the wafer 102 when bonded. The electrical and optical interconnects 200 also have solder metal-to-metal direct bond-free electrical interconnects between the first and second

electrical contacts

212, 214 of the die 100 and the complementary first and second

electrical contacts

222, 224 of the wafer. The direct bonding of both the

optical regions

204 and 216 and the respective

electrical contacts

212 and 222 and 214 and 224 forms a complete bonding interface 200 that forms the volume of the high-density optoelectronic interconnect 200 via the bonded

coupling planes

206 and 208 between the die 100 and the wafer 102.

Although the

electrical contacts

212, 214, 222, and 224 are shown exposed to the surface in fig. 3, in one scenario only portions of the contacts in the form of small pads are exposed and actually bonded. Not all CMP processes are capable of planarizing a bonding surface with an exposed metal load in the form of a ring, as depicted in fig. 3. Conversely, in some embodiments, a more uniformly exposed metal load (distributed pads) may be more suitable for an optimized CMP process.

Although the

electrical contacts

212, 214, 222, and 224 are shown as conductive lines or traces formed in the shape of a ring, square, rectangle, circle, or oval, each of the electrical contacts may also be in the form of only one (or more) pad(s), and not necessarily circumscribing the

optical window

204 or 206. In addition, each such pad may be electrically connected to its die 100 by a conductive via. Examples of pad bonding embodiments are shown in fig. 4-5.

After the directly bonded optoelectronic interconnects are formed between the die 100 and the wafer 102, the wafer 102 and its bonded die 100 may be diced or individualized into individual optoelectronic devices, or into groups of optoelectronic devices. For some applications, the wafer 102 with the directly bonded die 100 may remain intact and uncut, with the array of optoelectronic devices on, for example, a relatively large section of the wafer 102, or on the entire wafer 102.

Fig. 4 illustrates an embodiment of an exemplary optoelectronic interconnect 200 in which the first electrical contact 212 of the photonic device 100 and the second electrical contact 214 of the photonic device 100 are each a single metal pad polished and prepared for direct metal-to-metal bonding with

complementary pads

222 and 224 on the surface 208 of the wafer 102 being directly bonded. In different direct bonding regions that do not interfere with the direct bonding of

optical regions

204 and 216, the directly bonded

contacts

212 and 214 are both offset from one side of

optical regions

204 and 216. For bonding reliability, the

individual bond pads

212 and 214 or contacts may be a single instance of the corresponding pad (left) or multiple redundant instances of the pad for each lead or wire (right). Multiple pads (right) may also be used when the photonic device has more than two leads to be connected across the optoelectronic interconnect 200.

Traces or wires 220 and 220' that couple the

bond pads

222 and 224 to circuitry of the wafer 102 being bonded, such as L ED driver circuitry, are typically embedded or disposed beneath the bonding surface 208 itself.

Fig. 5 illustrates an embodiment of an exemplary optoelectronic interconnect 200 in which the first electrical contact 212 of the photonic device 100 and the second electrical contact 214 of the photonic device 100 are each metal pads, polished and prepared for direct metal-to-metal bonding.

Complementary pads

222 and 224 are located on surface 208 of wafer 102 being bonded directly thereto. In this configuration, the

contacts

212 and 214 to be directly bonded are on two or more sides outside of the

optical regions

204 and 216 to be directly bonded, in one or more different direct bonding regions that do not interfere with the optical path or interfere with the direct bonding between the surfaces of the

optical regions

204 and 216. For bonding reliability, for example, if one of the redundant pads is weakly bonded, the

respective bond pads

212 and 214 or contacts may be a single instance of the corresponding pad (left), or may be multiple redundant instances of the pad for each wire or lead (right). Multiple pads (right) may also be used when the photonic device has more than two types of leads to be connected across the optoelectronic interconnect 200.

Traces or wires 220 and 220' that couple the

bond pads

FIG. 6 illustrates an exemplary apparatus 600 in which photonic devices (such as L ED, m L ED, or an array of laser sources) are formed or arrayed on a wafer 602 or reconstituted wafer to fabricate photonic devices, the second wafer 102 being bonded to may have electronic circuitry such as CMOS driver circuitry to connect to the photonic devices on the first wafer 602 by direct bonding between the two wafers 602 and 102 across a planar optoelectronic interface (206 and 208 bonded by direct bonding), the two

surfaces

206 and 208 of the optoelectronic interface are planarized using CMP or other techniques for achieving an ultra-planar direct bonding surface in order to form optoelectronic interconnects, the

surfaces

206 and 208 being directly bonded may also include respective

optical bonding regions

206 and 216, in addition to the electronic driver circuitry, the second wafer 102 may also contain photonic circuitry (optical paths) into which light is injected or irradiated through waveguides 218 that are directly bonded to the optical regions 204 of the photonic devices L ED 100 or other photonic devices.

Direct hybrid bonding (such as

Hybrid bond) forms a direct bond between the non-metallic (e.g., S1O2)

optical regions

204 and 216 and, in the same overall operation, between the metallic

electrical contacts

212 and 214 across the same

optoelectronic interfaces

206 and 208 to form a wafer-to-wafer optoelectronic interconnect at each photonic device.

Fig. 7 shows another exemplary apparatus 700 in which photonic devices such as L ED, m L ED, or laser sources are arrayed on a wafer 702 a second wafer 704 being bonded to may have electronic circuitry such as CMOS driver circuitry to connect to the photonic devices on the first wafer 702 by electrical contacts 706 and 708 being bonded directly between the two

wafers

702 and 704 across a flat direct bonding interface (710 bonded to 712).

The two

wafers

702 and 704 of the example apparatus 700 may utilize a direct hybrid bonding process (such as

Direct hybrid bonding) where both the non-metal 714 and the conductive metal 714 are directly bonded together in the same integral direct hybrid bonding process. The non-metal 714 to be directly bonded may be a dielectric and may or may not be an optical region for transmitting light.

In one embodiment, the direct bonding process forms a thin m L ED array 700, where a wafer 702 with L ED structures is directly bonded to a CMOS driver chip wafer 704.

To achieve direct hybrid bonding, in one embodiment, after a planar and activated surface 710 is formed on the m L ED device wafer 702, the CMOS wafer 704 is planarized, for example, using CMP or other means to obtain an ultra-planar surface, and plasma activation 718.

After the non-metallic dielectric surfaces are directionally bonded 714 on the contacts, the direct bonding of the metallic conductors 716 may be performed at an annealing temperature of approximately 100 ℃ to 200 ℃ to form strong direct bond interconnects of both metal and non-metal, thereby preparing the exemplary m L ED array 700.

Exemplary method

Fig. 8 illustrates an exemplary method 800 of forming a flat bonding interface suitable for directly bonding a die (which includes a photonic device, such as a III-V semiconductor photonic device) to a wafer, such as a silicon or SOI wafer, to form an optoelectronic interconnect for an integrated photonic device. In some embodiments, an optoelectronic interconnect can directly bond two electrical contacts across an interface, and can directly bond an optical via across the same interface. In the flowchart of fig. 8, the operations of the exemplary method 800 are illustrated as separate blocks.

At block 802, a first optical window is formed in a first planar bonding surface of a die that includes a photonic device, such as a III-V semiconductor compound based sensor or L ED.

At block 804, first electrical contacts of a photonic device of a die are formed in the first planar bonding surface, the first electrical contacts at least partially circumscribing a first optical window of the die.

At block 806, second electrical contacts of the photonic device of the die are formed in the first planar bonding surface, the second electrical contacts at least partially circumscribing the first electrical contacts.

At block 808, a second optical window in communication with the silicon waveguide is formed in a second planar bonding surface associated with the wafer.

At block 810, a first electrical contact of an optoelectronic circuit of the wafer is formed in the second planar bonding surface, the first electrical contact at least partially circumscribing a second optical window of the silicon or SOI wafer.

At block 812, a second electrical contact of the optoelectronic circuit of the wafer is formed in the second planar bonding surface, the second electrical contact at least partially circumscribing the first electrical contact of the second planar bonding surface.

For example, the first and second flat bonding surfaces of the die and wafer, respectively, are made sufficiently flat for a direct bonding process by CMP. The respective optical windows are directly bonded to each other across the bonding interface by, for example, a dielectric-to-dielectric direct bonding process (e.g., an oxide-to-oxide direct bonding process). Respective coplanar metallic electrical contacts are directly bonded to each other across the bonding interface using a metal-to-metal direct bonding process. When direct-mix bonding is utilized (e.g.,

) Non-metallic direct bonding and subsequent metallic direct bonding results in the formation of a directly bonded optoelectronic interconnect between a die carrying a photonic device (such as a III-V semiconductor photonic device) and a wafer carrying optoelectronic circuits.

After forming directly bonded optoelectronic interconnects between the dies and the wafer, the wafer with the bonded instances of the dies may be diced or individualized into individual optoelectronic devices, or into groups of optoelectronic devices. For some applications, such as analog camera sensors, the wafer with the directly bonded die may remain uncut, with the array of optoelectronic devices forming a grid of camera sensors over a relatively large section of the wafer.

The photonic device may also be positioned on its own wafer to be bonded directly to another wafer carrying CMOS circuitry or other optoelectronic circuitry, providing a wafer-to-wafer (W2W) process for preparing, for example, m L ED arrays.

Fig. 9 illustrates an exemplary method 900 of bonding a die comprising a photonic device, such as a III-V semiconductor photonic device, to a silicon wafer or a silicon-on-insulator (SOI) wafer to form optoelectronic interconnects for high density integrated photonic devices. In the flowchart of fig. 9, the operations of the exemplary method 900 are illustrated as separate blocks.

At block 902, a first planar bonding interface is formed based on a III-V semiconductor compound with fully processed metal contacts on a die including a photonic device.

At block 904, a second flat bonding interface is formed on the silicon or SOI wafer.

At block 906, the respective optical windows of the first planar bonding interface of the die and the second planar bonding interface of the silicon or SOI wafer are bonded together directly to form an optical interconnect between the die and the silicon or SOI wafer.

At block 908, the first planar bonding interface of the die and the corresponding first electrical contact of the second planar bonding interface of the silicon or SOI wafer are bonded together directly to form a first electrical interconnect between the die and the silicon or SOI wafer.

At block 910, respective second electrical contacts of the first planar bonding interface of the die and the second planar bonding interface of the silicon wafer or wafer are bonded together directly to form a second electrical interconnect between the die and the silicon or SOI wafer.

The coplanar optical window, first electrode, and second electrode enable a direct bonding operation, such as a direct hybrid bonding (e.g.,

) To bond the optical and electrical paths in the combined optoelectronic interconnect thus formed. In one bonding operation, there is only one flat bonding interface for the optical and electrical interconnects. The combined optical and electrical interconnects enable high density integration of photonic devices into microelectronic packages because the employed adhesive-free dielectric-to-dielectric bonding and solder-free metal-to-metal bonding can form high density electrical interconnects on the same bonding interface as the bonded optical interconnects. Since the optoelectronic die can be started by full processing, a known good die can be used, but this is not conventionally possible. Since the optoelectronic die is from all sidesThe processed part is started and therefore the lithography of its top surface can be scaled to high density.

In this specification and the following claims: the terms "connect (connection)", "connected (connected)", "connect (in connection with)" and "connecting (connecting)" are used to mean "directly connected" or "connected through one or more elements. The terms "coupled," coupled, "and" coupled with "mean" coupled together directly "or" coupled together by one or more elements.

While the present disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover such modifications and variations as fall within the true spirit and scope of this present disclosure.

The claims (modification according to treaty clause 19)

1. A directly bonded optoelectronic interconnect, comprising:

a first bonding plane of a first die or wafer, the first bonding plane comprising a first optical window and electrical contacts of a photonic device of the first die or wafer;

a second bonding plane of a second die or wafer, the second bonding plane comprising a second optical window and electrical contacts of the second die or wafer; and

the optical windows of the first die or wafer and the second die or wafer bonded directly together; and

the respective electrical contacts of the first die or wafer and the second die or wafer bonded together directly.

2. The direct bonded optoelectronic interconnect of claim 1, wherein the electrical contact of the first die or wafer at least partially circumscribes the first optical window of the first die or wafer, or the electrical contact of the second die or wafer at least partially circumscribes the second optical window of the second die or wafer.

3. The directly bonded optoelectronic interconnect of claim 1, wherein the first optical window and the second optical window are directly bonded together by dielectric-to-dielectric direct bonding without a separate adhesive or direct bonding by a direct hybrid bonding operation; and is

Wherein the electrical contacts of the first die and the electrical contacts of the second die are directly bonded together by a metal-to-metal direct bond or a direct bond by the direct hybrid bonding operation.

4. The directly bonded optoelectronic interconnect of claim 1, further comprising:

a first bonding plane associated with the first die, the first bonding plane comprising: the first optical window, a first electrical contact at least partially circumscribing the first optical window and coplanar with the first optical window, and a second electrical contact at least partially circumscribing the first electrical contact and coplanar with both the first electrical contact and the first optical window; and

a second bonding plane associated with the second die, the second bonding plane comprising: the second optical window, a first electrical contact of the second die at least partially circumscribing the second optical window and coplanar with the second optical window, and a second electrical contact of the second die at least partially circumscribing the first electrical contact of the second die and coplanar with both the first electrical contact of the second die and the second optical window.

5. An apparatus, comprising:

a first die comprising an optoelectronic device;

an optical coupling region of the first die in optical communication with the optoelectronic device;

a coupling plane of the first die for optically and electrically coupling with a complementary coupling plane of a second die, a portion of the coupling plane of the first die containing the optical coupling region of the first die;

a first electrical contact of the optoelectronic device disposed outside a perimeter of the optical coupling region in the coupling plane of the first die; and

a second electrical contact of the optoelectronic device disposed outside a perimeter of the first electrical contact in the coupling plane of the first die.

6. The apparatus of claim 5, wherein the first electrical contact completely surrounds the optical coupling region in the coupling plane of the first die; and is

Wherein the first electrical contacts of the optoelectronic device of the first die are disposed outside a perimeter of an optical coupling region of a silicon waveguide of the second die.

7. The apparatus of claim 5, further comprising:

a second die, wherein the first die is optically and electrically couplable with the second die when respective coupling planes of the first die and the second die are joined;

a silicon waveguide in the second die in optical communication with the optical coupling region of the second die;

the optical coupling region of the second die occupying a portion of the coupling plane of the second die;

an optoelectronic circuit of the second die;

a first electrical contact of the optoelectronic circuit disposed outside a perimeter of the optical coupling region of the second die in the coupling plane of the second die, the first electrical contact of the optoelectronic circuit matching a planar geometric profile of the first electrical contact of the first die; and

a second electrical contact of the optoelectronic circuit disposed outside a perimeter of the first electrical contact of the optoelectronic circuit in the coupling plane of the second die, the second electrical contact of the optoelectronic circuit matching a planar geometric profile of the second electrical contact of the first die.

8. The apparatus of claim 7, wherein electrical routing from the optoelectronic circuit of the second die to the first and second electrical contacts of the optoelectronic circuit is within the coupling plane of the second die.

9. The apparatus of claim 8, wherein the second electrical contact of the optoelectronic circuit comprises an open loop or discontinuous trace within the coupling plane of the second die, further comprising a gap in the open loop or discontinuous trace to accommodate the electrical routing to the first electrical contact of the optoelectronic circuit within the coupling plane of the second die.

10. The apparatus of claim 7, wherein the optical coupling region of the second die comprises at least a grating surface for optical mode-matching coupling between the first die and the second die.

11. The apparatus of claim 10, wherein the grating surface is less than 10 micrometers (μ) thick for single-mode infrared transmission.

12. The apparatus of claim 5, wherein the first die has a fully processed electrode of the optoelectronic device and fully processed first and second electrical contacts of the optoelectronic device prior to bonding to the second die.

13. The apparatus of claim 5, further comprising:

an optical coupling between the optical coupling region of the first die and the optical coupling region of the second die in a bond coupling plane;

a metal-to-metal bond or a direct hybrid bond between the first electrical contact of the optoelectronic device of the first die and the first electrical contact of the optoelectronic circuit of the second die in the bonding coupling plane; and

a metal-to-metal bond or a direct hybrid bond between the second electrical contact of the optoelectronic device of the first die and the second electrical contact of the optoelectronic circuit of the second die in the bonding coupling plane.

14. The device of claim 13, further comprising a Transparent Conductive Oxide (TCO) between the III-V compound semiconductor and the silicon waveguide to enhance conductivity into the III-V compound semiconductor and to enhance uniformity of the conductivity.

15. The device of claim 14, wherein the Transparent Conductive Oxide (TCO) is selected from the group consisting of: aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and Indium Tin Oxide (ITO).

16. The device of claim 5, further comprising a bottom surface of the III-V compound semiconductor, the bottom surface roughened by etching to reduce reflection losses.

17. The apparatus of claim 5, further comprising a dielectric material between the bottom surface of a III-V compound semiconductor and the silicon waveguide to reduce reflection losses between the III-V compound semiconductor and the silicon waveguide, wherein a refractive index of the dielectric material is between the refractive index of the silicon and the refractive index of the III-V compound semiconductor.

18. The device of claim 17, wherein an optical thickness between the bottom surface of the III-V compound semiconductor and a top surface of the silicon waveguide is an odd multiple of one quarter of a wavelength of operating light of the device.

19. The apparatus of claim 18, further comprising a reflective layer on top of the optoelectronic device of the first die on the surface opposite the bonding surface.

20. An electrical interconnect and optical interconnect for a high density integrated photonic device, comprising:

a first coupling plane formed on a side of the first die;

a first optical window formed in the coupling plane of the first die;

a first electrical contact outside a perimeter of the first optical window and disposed in the coupling plane of the first die; and

a second electrical contact outside a perimeter of the first electrical contact and disposed in the coupling plane of the first die.

21. The electrical and optical interconnect for high density integrated photonic devices of claim 20, further comprising:

a second coupling plane formed on a second die;

a second optical window in the coupling plane of the second die;

a first complementary electrical contact outside a perimeter of the second optical window and disposed in the coupling plane of the second die;

a second complementary electrical contact outside a perimeter of the first complementary electrical contact and disposed in the coupling plane of the second die; and

an electrical lead leading to the first and second complementary electrical contacts disposed in the coupling plane of the second die.

22. The electrical and optical interconnects for high density integrated photonic devices of claim 20, wherein the first electrical contact of the first die and the first complementary electrical contact of the second die each comprise a square, rectangular, circular or oval electrically conductive wire surrounding the respective first or second optical window.

23. The electrical and optical interconnects for high density integrated photonic devices of claim 20, further comprising a dielectric-to-dielectric optical interconnect between the first optical window of the first die and the second optical window of the second die, and a solderless metal-to-metal bonded electrical interconnect or a direct hybrid bonded interconnect between the first and second electrical contacts of the first die and the first and second complementary electrical contacts of the second die, thereby forming a high density of electrical interconnects on a bonded coupling plane of the first and second dies.

24. A method, comprising:

bonding an optoelectronic die directly to a wafer, comprising:

forming a direct-bonded optical interconnect between the optoelectronic die and the wafer on the same coplanar bonding interface as the electrical interconnect formed between the optoelectronic die and the wafer; and

forming at least one metal-to-metal direct bond electrical interconnect between the metal contact of the optoelectronic die and a complementary metal contact of the wafer on the same coplanar bonding interface as the optical interconnect is formed between the optoelectronic die and the wafer.

25. The method of claim 24, further comprising:

forming a first optical coupling region, a first electrical contact, and a second electrical contact on a coupling plane of the optoelectronic die, wherein the first optical coupling region, the first electrical contact, and the second electrical contact are coplanar, and wherein the first electrical contact and the second electrical contact are disposed outside of an optical path of the first optical coupling region of the optoelectronic die; and

forming a second optical coupling region, a first complementary electrical contact, and a second complementary electrical contact on a coupling plane of the wafer, wherein the second optical coupling region, the first complementary electrical contact, and the second complementary electrical contact are coplanar, and wherein the first complementary electrical contact and the second complementary electrical contact are disposed outside of an optical path of the second optical coupling region of the wafer.

26. The method of claim 24, further comprising dicing the wafer and the instances of the die into individual photonic devices.

27. An apparatus, comprising:

a photonic device on a respective die or first wafer;

each photonic device includes an electrical contact and an optical via;

a second wafer comprising electrical contacts for electrical circuitry of the photonic device and an optical waveguide;

a non-metallic direct bond between the optical vias of the photonic devices of the respective die or first wafer;

a metal directly bonded between the electrical contacts of the photonic device of the respective die or first wafer and the electrical contacts of the circuit of the second wafer.

28. The apparatus of claim 27, wherein the photonic device comprises a laser, photodetector, optical diode, L ED, or micro L ED.

Claims

1. A directly bonded optoelectronic interconnect, comprising:

3. The directly bonded optoelectronic interconnect of claim 1, wherein the first optical window and the second optical window are directly bonded together by dielectric-to-dielectric direct bonding without a separate adhesive or direct bonding by a direct hybrid bonding operation; and

5. An apparatus, comprising:

a first die comprising an optoelectronic device;

7. The apparatus of claim 5, further comprising:

an optoelectronic circuit of the second die;

13. The apparatus of claim 5, further comprising:

a first coupling plane formed on a side of the first die;

a first optical window formed in the coupling plane of the first die;

a second coupling plane formed on a second die;

a second optical window in the coupling plane of the second die;

24. A method, comprising:

bonding an optoelectronic die directly to a wafer, comprising:

25. The method of claim 24, further comprising:

26. The method of claim 26, further comprising dicing the wafer and the instances of the die into individual photonic devices.

27. An apparatus, comprising:

a photonic device on a respective die or first wafer;

each photonic device includes an electrical contact and an optical via;