CN111479033A - Multi-display synchronous display device and method and aging test device - Google Patents
Multi-display synchronous display device and method and aging test device Download PDFInfo
- Publication number
- CN111479033A CN111479033A CN202010176955.8A CN202010176955A CN111479033A CN 111479033 A CN111479033 A CN 111479033A CN 202010176955 A CN202010176955 A CN 202010176955A CN 111479033 A CN111479033 A CN 111479033A
- Authority
- CN
- China
- Prior art keywords
- signal
- display
- signals
- image
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 46
- 238000012360 testing method Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims abstract description 11
- 230000032683 aging Effects 0.000 title abstract description 7
- 238000006243 chemical reaction Methods 0.000 claims abstract description 32
- 230000033228 biological regulation Effects 0.000 claims abstract description 20
- 230000002708 enhancing effect Effects 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101150010989 VCATH gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004984 smart glass Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
The invention discloses a multi-display synchronous display device which comprises a signal conversion module, an FPGA control module, a plurality of signal enhancement units, a plurality of Micro-O L ED displays and a plurality of boost regulation units, wherein the signal conversion module is electrically connected with the FPGA control module and is used for receiving video signals and simplifying the video signals into image signals or low-speed signals required by the FPGA control module, the FPGA control module is respectively connected with the signal enhancement units and the boost regulation units, each Micro-O L ED display is respectively electrically connected with the signal enhancement units and the boost regulation units, the signal enhancement units are used for enhancing the image signals or the low-speed signals, the FPGA control module is used for controlling the up-down electrical time sequence relation of each boost regulation unit, dividing the enhanced image signals or the low-speed signals into a plurality of image display signals and outputting the image display signals to each Micro-O L ED display to realize synchronous display, and the multi-O L ED display synchronous display method and the aging test device can also relate to realize synchronous display of the multi-O L ED displays.
Description
Technical Field
The invention relates to the technical field of micro-displays, in particular to a multi-display synchronous display device and method and an aging test device.
Background
With the development of display technology and the increasing popularity of AR/VR devices, smart glasses, and head-mounted displays, micro-display devices are slowly turning to the mainstream of micro-O L ED from the beginning L CoS.
However, in the application occasions of VR/AR glasses, production line tests and the like, the single driving micro-O L ED micro display module is very chicken-rib, cannot meet the requirements, and has low production efficiency, at the moment, a circuit system is needed, three or more micro-O L ED micro display modules are required to be driven to display the same picture content at the same time, and if the picture contents displayed by the two micro-O L ED micro display modules cannot be synchronous, the requirements of VR/AR glasses and the like cannot be met.
Disclosure of Invention
In view of this, the present invention provides a multi-display synchronous display device, which can avoid the problem of image signal interference caused by attenuation of received image display signals of each Micro-O L ED display, and implement synchronous display of multiple Micro-O L ED displays.
A multi-display synchronous display device comprises a signal conversion module, an FPGA control module, a plurality of signal enhancement units, a plurality of Micro-O L ED displays and a plurality of boosting regulation units;
the signal conversion module is electrically connected with the FPGA control module and is used for receiving the video signal and simplifying the video signal into an image signal or a low-speed simple signal required by the FPGA control module;
the FPGA control module is electrically connected with the signal enhancement units and the boost regulation units respectively, each signal enhancement unit is arranged corresponding to each Micro-O L ED display, each boost regulation unit is arranged corresponding to each Micro-O L ED display, each Micro-O L ED display is electrically connected with each signal enhancement unit and each boost regulation unit respectively, the signal enhancement units are used for enhancing image signals or low-speed simple signals, the FPGA control module is used for controlling the up-down power time sequence relation of each boost regulation unit, dividing the enhanced image signals or low-speed simple signals into a plurality of image display signals, and outputting the image display signals to each Micro-O L ED display respectively to achieve synchronous display.
In the embodiment of the invention, the video signals comprise HDMI signals, DVI signals, VGA signals and V-by-One signals;
the HDMI signal is a complex signal combining sound and an image, and the signal conversion module is used for simplifying the HDMI signal into the image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into the low-speed simple RGB basic signal.
In an embodiment of the present invention, the multi-display synchronous display device further includes a signal source module, the signal source module is electrically connected to the signal conversion module, and the signal source module is configured to provide the video signal to the signal conversion module.
In an embodiment of the present invention, the multi-display synchronous display device further includes a power module, the power module is electrically connected to the signal conversion module, the FPGA control module, each signal enhancement unit, and each boost adjustment unit, respectively, and the power module is configured to provide a dc voltage.
The invention also provides a multi-display synchronous display method, which utilizes the multi-display synchronous display device, and the method comprises the following steps:
enhancing the image signal or the low-speed simple signal by using a signal enhancement unit;
and an FPGA control module is utilized to control the power-up and power-down time sequence relation of a plurality of boosting adjusting units, the enhanced image signals or low-speed simple signals are divided into a plurality of image display signals, and the image display signals are respectively output to the Micro-O L ED displays to realize synchronous display.
In the embodiment of the invention, the video signals comprise HDMI signals, DVI signals, VGA signals and V-by-One signals;
the HDMI signal is a complex signal combining sound and an image, and is simplified into the image signal by the signal conversion module;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the DVI signal, the VGA signal and the V-by-One signal are simplified into the low-speed simple RGB basic signal by the signal conversion module.
The invention also provides an aging test device which comprises the multi-display synchronous display device.
The FPGA control module of the multi-display synchronous display device is electrically connected with the Micro-O L ED displays through the signal enhancement units, so that the problem of image signal interference caused by attenuation of received image display signals of the Micro-O L ED displays is solved, synchronous display of the multi-Micro-O L ED displays is realized, and the performance stability is good.
Drawings
Fig. 1 is a schematic structural diagram of the multi-display synchronous display device of the invention.
Detailed Description
Fig. 1 is a schematic structural diagram of an inventive multi-display synchronous display device, and as shown in fig. 1, the multi-display synchronous display device includes a signal conversion module 11, an FPGA control module 12, a plurality of signal enhancement units 13, a plurality of Micro-O L ED displays 14, and a plurality of boost regulation units 15;
the signal conversion module 11 is electrically connected with the FPGA control module 12, and the signal conversion module 11 is used for receiving a video signal and simplifying the video signal into an image signal or a low-speed simple signal required by the FPGA control module 12;
the FPGA control module 12 is electrically connected to the signal enhancement units 13 and the boost adjusting units 15, the signal enhancement units 13 are disposed corresponding to the Micro-O L ED displays 14, the boost adjusting units 15 are disposed corresponding to the Micro-O L ED displays 14, the Micro-O L ED displays 14 are electrically connected to the signal enhancement units 13 and the boost adjusting units 15, the signal enhancement units 13 are used for enhancing image signals or low-speed simple signals, the FPGA control module 12 is used for controlling the power-up and power-down timing relationship of the boost adjusting units 15 and dividing the enhanced image signals or low-speed simple signals into multiple image display signals (including but not limited to RGB TT L signals) and outputting the image display signals to the Micro-O L ED displays 14 respectively to achieve synchronous display.
It should be noted that the boost adjusting unit 15 is used to generate each set of voltages (including but not limited to VDD voltage and Vcath voltage) required by the Micro-O L ED display 14 further, the video signals include HDMI signal, DVI signal, VGA signal, V-by-One signal;
the HDMI signal is a complex signal combining sound and image, and the signal conversion module 11 is configured to simplify the HDMI signal into an image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module 11 is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into low-speed simple RGB basic signals. In this embodiment, high-speed complex signals such as DVI signals, VGA signals, V-by-One signals and the like are suitable for long-distance transmission, and the complexity of the FPGA control module 12 can be reduced by simplifying the high-speed complex signals into low-speed simple RGB basic signals, that is, the high-speed complex signals need to be processed by the FPGA control module 12 with higher complexity, and the low-speed simple RGB basic signals need to be processed by the FPGA control module 12 with lower complexity.
It should be noted that the video signal also includes other complex signals of sound and image combination and other high-speed complex signals, and is not limited to the above.
Further, the multi-display synchronous display device further includes a signal source module 16, the signal source module 16 is electrically connected to the signal conversion module 11, and the signal source module 16 is configured to provide a video signal to the signal conversion module 11.
Furthermore, the multi-display synchronous display device further comprises a power module 17, the power module 17 is electrically connected with the signal conversion module 11, the FPGA control module 12, each signal enhancement unit 13, each boosting adjustment unit 15, and the signal source module 16, respectively, and the power module 17 is used for providing a direct current voltage. In this embodiment, the commercial power grid voltage 220V/50H is provided to be input to the power module 17, and the dc voltage is output to the signal conversion module 11, the FPGA control module 12, the signal enhancement units 13, and the boost adjusting units 15 through the voltage reduction and stabilization of the power circuit.
Further, the Micro-O L ED display 14 is an O L ED display device fabricated by using single crystal silicon as an active driving backplane, and its pixels are 1/10 of a conventional display device, and has high resolution, high integration, low power consumption, small volume, light weight, and the like.
Further, the number of the signal enhancement units 13, the Micro-O L ED displays 14 and the number of the boost regulation units 15 are all greater than or equal to 3, for example, the multi-display synchronous display device includes 3 signal enhancement units 13, 3 Micro-O L ED displays 14 and 3 boost regulation units 15;
defining 3 signal enhancement units 13 as a first signal enhancement unit, a second signal enhancement unit and a third signal enhancement unit respectively, wherein the first signal enhancement unit, the second signal enhancement unit and the third signal enhancement unit are arranged in parallel, and the FPGA control module 12 is electrically connected with the first signal enhancement unit, the second signal enhancement unit and the third signal enhancement unit respectively;
defining 3 Micro-O L ED displays 14 as a first Micro-O L ED display, a second Micro-O L ED display and a third Micro-O L ED display respectively, wherein the first Micro-O L ED display, the second Micro-O L ED display and the third Micro-O L ED display are arranged in parallel, the first Micro-O L ED display is electrically connected with a first signal enhancement unit and a first boosting regulation unit respectively, the second Micro-O L ED display is electrically connected with a second signal enhancement unit and a second boosting regulation unit respectively, and the third Micro-O L ED display is electrically connected with a third signal enhancement unit and a third boosting regulation unit respectively;
defining 3 boosting adjusting units 15 as a first boosting adjusting unit, a second boosting adjusting unit and a third boosting adjusting unit respectively, wherein the first boosting adjusting unit, the second boosting adjusting unit and the third boosting adjusting unit are arranged in parallel; the FPGA control module 12 is electrically connected with the first boost regulating unit, the second boost regulating unit and the third boost regulating unit respectively, and the FPGA control module 12 controls the power-up and power-down time sequence relation of the boost regulating unit 15 respectively.
The signal enhancement units 13 are electrically connected between the FPGA control module 12 and each Micro-O L ED display 14 of the multi-display synchronous display device, so that the problem of image signal interference caused by attenuation of received image display signals of each Micro-O L ED display 14 is solved, synchronous display of the multi-Micro-O L ED displays 14 is realized, the performance stability is good, and the multi-display synchronous display device is simple in structure and low in manufacturing cost.
The invention also relates to a multi-display synchronous display method, which utilizes the multi-display synchronous display device and comprises the following steps:
enhancing the image signal or the low-speed simple signal with the signal enhancing unit 13;
the FPGA control module 12 is used for controlling the power-up and power-down time sequence relation of the plurality of boost adjusting units 15, dividing the enhanced image signal or the low-speed simple signal into a plurality of image display signals, and respectively outputting the image display signals to the Micro-O L ED displays 14 to realize synchronous display.
In the embodiment, the signal conversion module 11 can simplify the complex video signal into an image signal or a low-speed simple signal (including but not limited to L VDS signal and mini-L VDS signal) required by the FPGA control module 12, so that the multi-display synchronous display device has more compatibility and applicability, and can reduce the complexity of the FPGA control module 12, which is beneficial to reducing the manufacturing cost of the FPGA control module 12 and reducing the volume of the FPGA control module 12.
Further, the video signals comprise HDMI signals, DVI signals, VGA signals and V-by-One signals;
the HDMI signal is a complex signal combining sound and images, and is simplified into an image signal by using a signal conversion module 11;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the DVI signal, the VGA signal and the V-by-One signal are simplified into low-speed simple RGB basic signals by the signal conversion module 11.
It is worth mentioning that the multi-display synchronous display method can be used for contrast display testing, after micro-O L ED micro-display modules are produced in batches, the micro-O L ED micro-display modules can be lightened for comparison at the same time, so that the micro-O L ED micro-display modules with larger differences can be found out quickly, and the production efficiency can be improved.
The invention also relates to an aging test device which comprises the multi-display synchronous display device.
Furthermore, the aging test device is used for driving and lighting each micro-O L ED micro display module one by one for a specific time under the conditions of normal temperature, high humidity and the like after the micro-O L ED micro display modules are produced and prepared, the test speed is high, and the production efficiency is greatly improved (if a single driving mode is adopted, the problems of low test speed, low production efficiency and the like are solved).
The present invention is not limited to the specific details of the above-described embodiments, and various simple modifications may be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (7)
1. A multi-display synchronous display device is characterized by comprising a signal conversion module, an FPGA control module, a plurality of signal enhancement units, a plurality of Micro-O L ED displays and a plurality of boosting regulation units;
the signal conversion module is electrically connected with the FPGA control module and is used for receiving video signals and simplifying the video signals into image signals or low-speed simple signals required by the FPGA control module;
the FPGA control module is electrically connected with each signal enhancement unit and each boosting regulation unit respectively, each signal enhancement unit is arranged corresponding to each Micro-O L ED display, each boosting regulation unit is arranged corresponding to each Micro-O L ED display, each Micro-O L ED display is electrically connected with each signal enhancement unit and each boosting regulation unit respectively, the signal enhancement unit is used for enhancing the image signals or the low-speed simple signals, the FPGA control module is used for controlling the up-down electrical time sequence relation of each boosting regulation unit, dividing the enhanced image signals or the low-speed simple signals into a plurality of image display signals, and outputting each image display signal to each Micro-O L ED display respectively to achieve synchronous display.
2. The multi-display synchronous display device of claim 1, wherein the video signals comprise HDMI signals, DVI signals, VGA signals, V-by-One signals;
the HDMI signal is a complex signal combining sound and an image, and the signal conversion module is used for simplifying the HDMI signal into the image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into the low-speed simple RGB basic signal.
3. The multi-display synchronous display device of claim 1, further comprising a signal source module electrically connected to the signal conversion module, the signal source module being configured to provide the video signal to the signal conversion module.
4. The multi-display synchronous display device according to any one of claims 1 to 3, further comprising a power module, wherein the power module is electrically connected to the signal conversion module, the FPGA control module, each signal enhancement unit, and each boost adjustment unit, respectively, and is configured to provide a DC voltage.
5. A multi-display synchronous display method using the multi-display synchronous display device of any one of claims 1 to 4, the method comprising:
enhancing the image signal or the low-speed simple signal by using a signal enhancement unit;
and an FPGA control module is utilized to control the power-up and power-down time sequence relation of a plurality of boosting adjusting units, the enhanced image signals or low-speed simple signals are divided into a plurality of image display signals, and the image display signals are respectively output to the Micro-O L ED displays to realize synchronous display.
6. The multi-display synchronous display method of claim 5, wherein the video signal comprises an HDMI signal, a DVI signal, a VGA signal, a V-by-One signal;
the HDMI signal is a complex signal combining sound and an image, and is simplified into the image signal by the signal conversion module;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the DVI signal, the VGA signal and the V-by-One signal are simplified into the low-speed simple RGB basic signal by the signal conversion module.
7. A burn-in test apparatus comprising the multi-display synchronous display apparatus of any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010176955.8A CN111479033A (en) | 2020-03-13 | 2020-03-13 | Multi-display synchronous display device and method and aging test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010176955.8A CN111479033A (en) | 2020-03-13 | 2020-03-13 | Multi-display synchronous display device and method and aging test device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111479033A true CN111479033A (en) | 2020-07-31 |
Family
ID=71748301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010176955.8A Pending CN111479033A (en) | 2020-03-13 | 2020-03-13 | Multi-display synchronous display device and method and aging test device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111479033A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1566980A (en) * | 2003-06-20 | 2005-01-19 | 统宝光电股份有限公司 | Ageing testing system |
| CN1987972A (en) * | 2005-12-23 | 2007-06-27 | 上海广电电子股份有限公司 | Video frequency driving system and its method for organic light emitting diode display screen |
| US20100134384A1 (en) * | 2008-11-28 | 2010-06-03 | Seong Gyun Kim | Multi-panel display device and method of driving the same |
| EP2391134A1 (en) * | 2010-05-26 | 2011-11-30 | Advanced Digital Broadcast S.A. | A video display system, a shutter glasses device and a method for operating shutter glasses |
| US20140009412A1 (en) * | 2012-07-09 | 2014-01-09 | Byeongkil Ahn | Touch display device and multi-touch display device |
| CN105093589A (en) * | 2015-08-25 | 2015-11-25 | 昆山龙腾光电有限公司 | Aging testing system for liquid crystal display modules |
| CN106982383A (en) * | 2017-04-26 | 2017-07-25 | 威盛电子股份有限公司 | Distributed video shows system, control device and control method |
| CN108172153A (en) * | 2017-12-27 | 2018-06-15 | 苏州华兴源创电子科技有限公司 | A kind of LCD module group aging test device and include its equipment |
| CN109036276A (en) * | 2018-09-25 | 2018-12-18 | 深圳市峰泳科技有限公司 | A kind of Micro-OLED miniscope driving circuit |
| CN110221432A (en) * | 2019-03-29 | 2019-09-10 | 华为技术有限公司 | The image display method and equipment of head-mounted display |
| US20190294239A1 (en) * | 2018-03-21 | 2019-09-26 | Samsung Electronics Co., Ltd. | System and method for utilizing gaze tracking and focal point tracking |
-
2020
- 2020-03-13 CN CN202010176955.8A patent/CN111479033A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1566980A (en) * | 2003-06-20 | 2005-01-19 | 统宝光电股份有限公司 | Ageing testing system |
| CN1987972A (en) * | 2005-12-23 | 2007-06-27 | 上海广电电子股份有限公司 | Video frequency driving system and its method for organic light emitting diode display screen |
| US20100134384A1 (en) * | 2008-11-28 | 2010-06-03 | Seong Gyun Kim | Multi-panel display device and method of driving the same |
| EP2391134A1 (en) * | 2010-05-26 | 2011-11-30 | Advanced Digital Broadcast S.A. | A video display system, a shutter glasses device and a method for operating shutter glasses |
| US20140009412A1 (en) * | 2012-07-09 | 2014-01-09 | Byeongkil Ahn | Touch display device and multi-touch display device |
| CN105093589A (en) * | 2015-08-25 | 2015-11-25 | 昆山龙腾光电有限公司 | Aging testing system for liquid crystal display modules |
| CN106982383A (en) * | 2017-04-26 | 2017-07-25 | 威盛电子股份有限公司 | Distributed video shows system, control device and control method |
| CN108172153A (en) * | 2017-12-27 | 2018-06-15 | 苏州华兴源创电子科技有限公司 | A kind of LCD module group aging test device and include its equipment |
| US20190294239A1 (en) * | 2018-03-21 | 2019-09-26 | Samsung Electronics Co., Ltd. | System and method for utilizing gaze tracking and focal point tracking |
| CN109036276A (en) * | 2018-09-25 | 2018-12-18 | 深圳市峰泳科技有限公司 | A kind of Micro-OLED miniscope driving circuit |
| CN110221432A (en) * | 2019-03-29 | 2019-09-10 | 华为技术有限公司 | The image display method and equipment of head-mounted display |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106157917B (en) | A kind of drive device for display and its driving method can reduce power consumption | |
| US10304398B2 (en) | Driver integrated circuit for driving display panel, display device and method for driving driver integrated circuit capable of providing different current intensities to different length transmission wires | |
| CN109036295A (en) | Image display processing method and device, display device and storage medium | |
| KR101279351B1 (en) | Timing controller and liquid crystal display using the same | |
| CN112102770B (en) | Drive chip, display screen and display device | |
| CN100423071C (en) | Plane-board display device and its driving method | |
| CN102254535A (en) | Pixel drive method and system | |
| US9966023B1 (en) | Liquid crystal display device and control method for the same | |
| US10872558B2 (en) | Image display processing method and device, display device and non-volatile storage medium | |
| CN102214450B (en) | Liquid crystal display and driving method thereof | |
| US11380271B2 (en) | Backlight driving method, display driving method, drive device and display device | |
| WO2021203778A1 (en) | Display device and display system | |
| CN110379386A (en) | Display panel and display | |
| CN111479033A (en) | Multi-display synchronous display device and method and aging test device | |
| CN101699555A (en) | Liquid crystal display and terminal | |
| CN101325042B (en) | Liquid crystal display device and method for driving the same | |
| CN111464848A (en) | Double-display synchronous display device, head-mounted display device, VR/AR and intelligent glasses | |
| CN208351186U (en) | A kind of display device of vending machine | |
| CN203181061U (en) | Cascaded extension multi-screen seamless-switching high-definition video processing device | |
| CN207718781U (en) | A kind of liquid crystal display panel circuit of list TCON plates | |
| CN109493815A (en) | Display device and backlight driving method | |
| CN201562441U (en) | Head-up display liquid crystal image source display | |
| CN115035872B (en) | Display device | |
| CN220856080U (en) | Multi-module color continuous compensation device | |
| US20240013736A1 (en) | Power supply system for display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200731 |