CN111464848A - Double-display synchronous display device, head-mounted display device, VR/AR and intelligent glasses - Google Patents
Double-display synchronous display device, head-mounted display device, VR/AR and intelligent glasses Download PDFInfo
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- CN111464848A CN111464848A CN202010176123.6A CN202010176123A CN111464848A CN 111464848 A CN111464848 A CN 111464848A CN 202010176123 A CN202010176123 A CN 202010176123A CN 111464848 A CN111464848 A CN 111464848A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/01—Head-up displays
- G02B27/017—Head mounted
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
Abstract
A double-display synchronous display device comprises a signal conversion module, an FPGA control module, a first Micro-O L ED display, a second Micro-O L ED display and a voltage adjusting unit, wherein the signal conversion module is electrically connected with the FPGA control module and used for receiving video signals and simplifying the video signals into image signals or low-speed signals required by the FPGA control module, the FPGA control module is respectively electrically connected with the first Micro-O L ED display, the second Micro-O L ED display and the voltage adjusting unit, and the FPGA control module is used for controlling the up-down electrical time sequence relation of the voltage adjusting unit and dividing the image signals or the low-speed signals into first image display signals and second image display signals, outputting the first image display signals to the first Micro-O L ED display and outputting the second image display signals to the second Micro-O L ED display to achieve synchronous display.
Description
Technical Field
The invention relates to the technical field of micro-displays, in particular to a double-display synchronous display device, a head-mounted display device, VR/AR and intelligent glasses.
Background
With the development of display technology and the increasing popularity of AR/VR devices, smart glasses, and head-mounted displays, micro-display devices are slowly turning to the mainstream of micro-O L ED from the beginning L CoS.
At present, in application occasions such as binocular VR/AR glasses, a single-drive micro-O L ED micro display module is very chicken-rib and can not meet requirements, at the moment, a circuit system is designed, a left eye uses one micro-O L ED micro display module as a carrier to display a picture, a right eye uses the other micro-O L ED micro display module as a carrier to display the picture, the binocular micro-O L ED micro display module is required to synchronously display the same picture content, and if the picture contents displayed by the two micro-O L ED micro display modules can not be synchronous, the requirements of the binocular VR/AR glasses and the like can not be met.
Disclosure of Invention
In view of the above, the present invention provides a dual-display synchronous display device, which can simultaneously drive two displays to perform synchronous display, and display image signals are not interfered with each other, and the performance is stable.
A double-display synchronous display device comprises a signal conversion module, an FPGA control module, a first Micro-O L ED display, a second Micro-O L ED display and a voltage regulation unit;
the signal conversion module is electrically connected with the FPGA control module and is used for receiving the video signal and simplifying the video signal into an image signal or a low-speed simple signal required by the FPGA control module;
the FPGA control module is respectively electrically connected with the first Micro-O L ED display, the second Micro-O L ED display and the voltage adjusting unit, the voltage adjusting unit is respectively electrically connected with the first Micro-O L ED display and the second Micro-O L ED display, and the FPGA control module is used for controlling the up-down power time sequence relation of the voltage adjusting unit, dividing an image signal or a low-speed simple signal into a first image display signal and a second image display signal, outputting the first image display signal to the first Micro-O L ED display and outputting the second image display signal to the second Micro-O L ED display to achieve synchronous display.
In the embodiment of the invention, the video signals comprise HDMI signals, DVI signals, VGA signals and V-by-One signals;
the HDMI signal is a complex signal combining sound and an image, and the signal conversion module is used for simplifying the HDMI signal into the image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into the low-speed simple RGB basic signal.
In an embodiment of the present invention, the dual-display synchronous display device further includes a signal source module, the signal source module is electrically connected to the signal conversion module, and the signal source module is configured to provide the video signal to the signal conversion module.
In an embodiment of the present invention, the FPGA control module is electrically connected to the first Micro-O L ED display through a plurality of first data lines and a plurality of first control lines, the FPGA control module is electrically connected to the second Micro-O L ED display through a plurality of second data lines and a plurality of second control lines, and the lengths of the first data lines and the second data lines are equal to each other.
In an embodiment of the invention, the voltage regulation unit is electrically connected to the first Micro-O L ED display through a first voltage signal line, the voltage regulation unit is electrically connected to the second Micro-O L ED display through a second voltage signal line, and the first voltage signal line and the second voltage signal line are connected in parallel.
In an embodiment of the present invention, the dual-display synchronous display device further includes a power module, the power module is electrically connected to the signal conversion module, the FPGA control module, and the voltage adjustment unit, respectively, and the power module is configured to provide a dc voltage.
In an embodiment of the present invention, a voltage-reducing and voltage-stabilizing power supply circuit is disposed in the power supply module.
The invention also provides binocular VR/AR glasses which comprise the dual-display synchronous display device.
The invention also provides a head-mounted display device which comprises the double-display synchronous display device.
The invention also provides intelligent glasses, which comprise the double-display synchronous display device.
The double-display synchronous display device can simultaneously drive the first Micro-O L ED display and the second Micro-O L ED display to synchronously display, display image signals between the first Micro-O L ED display and the second Micro-O L ED display are not interfered with each other, the performance stability is good, and the double-display synchronous display device is simple in structure and low in manufacturing cost.
Drawings
Fig. 1 is a schematic structural diagram of the dual-display synchronous display device of the invention.
Detailed Description
FIG. 1 is a schematic structural diagram of the dual-display synchronous display device of the present invention, and as shown in FIG. 1, the dual-display synchronous display device includes a signal conversion module 11, an FPGA control module 12, a first Micro-O L ED display 13, a second Micro-O L ED display 14, and a voltage adjustment unit 15;
the signal conversion module 11 is electrically connected with the FPGA control module 12, and the signal conversion module 11 is used for receiving a video signal and simplifying the video signal into an image signal or a low-speed simple signal required by the FPGA control module 12;
the FPGA control module 12 is electrically connected to the first Micro-O L ED display 13, the second Micro-O L ED display 14 and the voltage adjusting unit 15, respectively, the voltage adjusting unit 15 is electrically connected to the first Micro-O L ED display 13 and the second Micro-O L ED display 14, respectively, the FPGA control module 12 is used for controlling the up-down electrical timing relationship of the voltage adjusting unit 15 and dividing the image signal or the low-speed simple signal into a first image display signal and a second image display signal (including but not limited to RGB TT L signals), and outputting the first image display signal to the first Micro-O L ED display 13 and outputting the second image display signal to the second Micro-O L ED display 14 to achieve synchronous display, in the embodiment, the signal conversion module 11 can simplify the complex video signal into the image signal or the low-speed simple signal (including but not limited to L VDS signals and mini-L VDS signals) required by the FPGA control module 12, so that the compatibility of the FPGA control module and the low-speed simple signal conversion module can reduce the manufacturing cost of the FPGA control module and the FPGA control module, and the development of the FPGA control device can reduce the compatibility of the FPGA and the FPGA control module, and the display device.
It is worth mentioning that the voltage adjusting unit 15 is used to generate the sets of voltages (including but not limited to VDD voltage, Vcath voltage) required by the first Micro-O L ED display 13 and the second Micro-O L ED display 14.
Further, the video signals comprise HDMI signals, DVI signals, VGA signals and V-by-One signals;
the HDMI signal is a complex signal combining sound and image, and the signal conversion module 11 is configured to simplify the HDMI signal into an image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module 11 is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into low-speed simple RGB basic signals. In this embodiment, high-speed complex signals such as DVI signals, VGA signals, V-by-One signals and the like are suitable for long-distance transmission, and the complexity of the FPGA control module 12 can be reduced by simplifying the high-speed complex signals into low-speed simple RGB basic signals, that is, the high-speed complex signals need to be processed by the FPGA control module 12 with higher complexity, and the low-speed simple RGB basic signals need to be processed by the FPGA control module 12 with lower complexity.
It should be noted that the video signal also includes other complex signals of sound and image combination and other high-speed complex signals, and is not limited to the above.
Further, the dual-display synchronous display device further includes a signal source module 16, the signal source module 16 is electrically connected to the signal conversion module 11, and the signal source module 16 is configured to provide a video signal to the signal conversion module 11.
Further, the FPGA control module 12 is electrically connected to the first Micro-O L ED display 13 through a plurality of first data lines 121 and a plurality of first control lines 122, the FPGA control module 12 is electrically connected to the second Micro-O L ED display 14 through a plurality of second data lines 123 and a plurality of second control lines 124, and the first data lines 121 are equal to the second data lines 123.
Furthermore, the voltage adjusting unit 15 is electrically connected with the first Micro-O L ED display 13 through a first voltage signal line 171, the voltage adjusting unit 15 is electrically connected with the second Micro-O L ED display 14 through a second voltage signal line 172, and the first voltage signal line 171 is electrically connected with the second voltage signal line 172 in parallel.
Furthermore, the dual-display synchronous display device further comprises a power module 17, the power module 17 is electrically connected with the signal conversion module 11, the FPGA control module 12, the voltage adjusting unit 15 and the signal source module 16, and the power module 17 is used for providing direct-current voltage.
Further, a voltage-reducing and voltage-stabilizing power supply circuit (not shown) is disposed in the power supply module 17. In this embodiment, the commercial power network voltage 220V/50H is provided to the power module 17, and the dc voltage is outputted to the signal conversion module 11, the FPGA control module 12, and the voltage adjustment unit 15 through the step-down and voltage stabilization of the power circuit.
Further, the first Micro-O L ED display 13 and the second Micro-O L ED display 14 are O L ED display devices fabricated by using single crystal silicon as an active driving backplane, and pixels thereof are 1/10 of conventional display devices, so that the display devices have the advantages of high resolution, high integration, low power consumption, small volume, light weight and the like.
The double-display synchronous display device can simultaneously drive the first Micro-O L ED display 13 and the second Micro-O L ED display 14 to synchronously display, display image signals between the first Micro-O L ED display 13 and the second Micro-O L ED display 14 are not interfered with each other, the performance stability is good, and the requirements of binocular VR/AR glasses can be met.
In the embodiment, the first Micro-O L ED display 13 is used as a left eye display of the VR/AR glasses, and the second Micro-O L ED display 14 is used as a right eye display of the VR/AR glasses.
In this embodiment, the first Micro-O L ED display 13 is used as the left-eye display of the head-mounted display device, and the second Micro-O L ED display 14 is used as the right-eye display of the head-mounted display device.
In the embodiment, the first Micro-O L ED display 13 serves as a left eye display of the smart glasses, and the second Micro-O L ED display 14 serves as a right eye display of the smart glasses.
The present invention is not limited to the specific details of the above-described embodiments, and various simple modifications may be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (10)
1. A double-display synchronous display device is characterized by comprising a signal conversion module, an FPGA control module, a first Micro-O L ED display, a second Micro-O L ED display and a voltage regulation unit;
the signal conversion module is electrically connected with the FPGA control module and is used for receiving video signals and simplifying the video signals into image signals or low-speed simple signals required by the FPGA control module;
the FPGA control module is respectively electrically connected with the first Micro-O L ED display, the second Micro-O L ED display and the voltage adjusting unit, the voltage adjusting unit is respectively electrically connected with the first Micro-O L ED display and the second Micro-O L ED display, and the FPGA control module is used for controlling the up-down power timing relationship of the voltage adjusting unit, dividing the image signal or the low-speed simple signal into a first image display signal and a second image display signal, outputting the first image display signal to the first Micro-O L ED display and outputting the second image display signal to the second Micro-O L ED display to realize synchronous display.
2. The dual-display synchronous display device of claim 1, wherein the video signal comprises an HDMI signal, a DVI signal, a VGA signal, a V-by-One signal;
the HDMI signal is a complex signal combining sound and an image, and the signal conversion module is used for simplifying the HDMI signal into the image signal;
the DVI signal, the VGA signal and the V-by-One signal are high-speed complex signals, and the signal conversion module is used for simplifying the DVI signal, the VGA signal and the V-by-One signal into the low-speed simple RGB basic signal.
3. The dual-display synchronous display device of claim 1, further comprising a signal source module electrically connected to the signal conversion module, the signal source module being configured to provide the video signal to the signal conversion module.
4. The dual-display synchronous display device as claimed in claim 1, wherein the FPGA control module is electrically connected to the first Micro-O L ED display via a plurality of first data lines and a plurality of first control lines, the FPGA control module is electrically connected to the second Micro-O L ED display via a plurality of second data lines and a plurality of second control lines, and each of the first data lines and each of the second data lines have the same length.
5. The dual-display synchronous display device as recited in claim 1, wherein the voltage regulating unit is electrically connected to the first Micro-O L ED display through a first voltage signal line, and the voltage regulating unit is electrically connected to the second Micro-O L ED display through a second voltage signal line, and the first voltage signal line and the second voltage signal line are connected in parallel.
6. The dual-display synchronous display device according to any one of claims 1 to 5, further comprising a power module, wherein the power module is electrically connected to the signal conversion module, the FPGA control module, and the voltage adjustment unit, respectively, and is configured to provide a DC voltage.
7. The dual-display synchronous display device of claim 6, wherein a buck-regulator power supply circuit is disposed in the power supply module.
8. Binocular VR/AR glasses comprising the dual-display synchronous display device of any one of claims 1 to 7.
9. A head-mounted display device comprising the dual-display synchronous display device according to any one of claims 1 to 7.
10. Smart glasses comprising the dual-display synchronous display device of any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010176123.6A CN111464848A (en) | 2020-03-13 | 2020-03-13 | Double-display synchronous display device, head-mounted display device, VR/AR and intelligent glasses |
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| CN202010176123.6A CN111464848A (en) | 2020-03-13 | 2020-03-13 | Double-display synchronous display device, head-mounted display device, VR/AR and intelligent glasses |
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