CN111475325B

CN111475325B - Error correction method and error correction device for storage equipment

Info

Publication number: CN111475325B
Application number: CN202010259554.9A
Authority: CN
Inventors: 段小康
Original assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Current assignee: Jiangsu Xinsheng Intelligent Technology Co ltd
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2022-10-14
Anticipated expiration: 2040-04-03
Also published as: CN111475325A

Abstract

The invention discloses an error correction method and an error correction device for storage equipment, which do not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage equipment, and also do not need to distinguish the error correction mechanism behaviors of various storage equipment by macro in one set of codes, thereby reducing the coding work and the later maintenance cost. The method comprises the following steps: when the storage device has data reading errors, acquiring error correction mechanism format information of the storage device; setting standard format information of an error correction mechanism according to the format information of the error correction mechanism, wherein the standard format information of the error correction mechanism comprises header information and data information; analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism; executing an error correction mechanism behavior according to the command parameter, the register parameter and the data parameter, and reading error correction mechanism behavior data from the data information; and judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data.

Description

Error correction method and error correction device for storage equipment

Technical Field

The present invention relates to the field of data processing, and in particular, to an error correction method and an error correction apparatus for a storage device.

Background

NAND FLASH is a storage medium and is widely available in the field of life. With the advancement of technology, NAND FLASH has also evolved from Single-Level Cell (SLC) to multi-Level Cell (XLC). As the capacity is larger and larger, the stability is deteriorated, and the bit flipping is improved, which requires a stronger error correction mechanism. The NAND FLASH is affected by conditions such as temperature and storage time, which causes bit flipping to increase suddenly, which may cause the error correction mechanism to fail and cause data reading failure. NAND FLASH manufacturers provide a mechanism for adjusting the decision voltage, i.e., an error correction mechanism, which can first move the decision voltage and then reinitiate the read. The direction and magnitude of the voltage shift determined in the actual application is unknown. NAND FLASH tends to offer several, even tens of combinations, including what is possible. The user attempts to adjust the decision voltage, read the data, and if the data is normal, the process ends, otherwise, the next combination is continued.

For the format of the error correction mechanism, the method is different for different NAND FLASH manufacturers, and different styles of the same manufacturer may be different. In the face of different formats of a plurality of manufacturers, the first method is to write a set of corresponding codes every time one NAND FLASH is matched, and a plurality of sets of codes can be formed along with the increase of the matched NAND FLASH; the second method is to compile corresponding codes according to different error correction mechanism formats by using macro differences in a set of codes.

However, the first method needs to write a plurality of sets of codes and needs a large amount of manpower input, which causes time and manpower waste and high later maintenance cost; the second method, using macro-partitioning within a set of codes, is not conducive to reading, can cause frustration to maintainers, can cause confusion, and is also not conducive to later maintenance.

Disclosure of Invention

The invention aims to provide an error correction method and an error correction device for storage equipment, which do not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage equipment, and do not need to distinguish the error correction mechanism behaviors of various storage equipment by macro in one set of codes, thereby reducing the coding work and the later maintenance cost.

The invention provides a storage device error correction method in a first aspect, which comprises the following steps:

when the storage device has data reading errors, acquiring error correction mechanism format information of the storage device;

setting standard format information of an error correction mechanism according to the format information of the error correction mechanism, wherein the standard format information of the error correction mechanism comprises header information and data information, the header information comprises parameters required for executing the behavior of the error correction mechanism, and the data information comprises data for executing the behavior of the error correction mechanism;

analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism behavior;

executing an error correction mechanism behavior according to the command parameter, the register parameter and the data parameter, and reading error correction mechanism behavior data from the data information;

and judging whether the error correction mechanism behavior succeeds or not according to the error correction mechanism behavior data.

Further, setting the standard format information of the error correction mechanism according to the format information of the error correction mechanism, including:

constructing an error correction mechanism structure body, wherein the error correction mechanism structure body comprises a first structure body and a second structure body;

obtaining parameters and data of the storage device for executing the error correction mechanism behavior according to the error correction mechanism format information;

storing the parameters to a first structure body, and storing the data to a second structure body;

obtaining head information according to parameters in the first structural body, and obtaining data information according to data in the second structural body;

and obtaining standard format information of an error correction mechanism according to the header information and the data information.

Further, executing an error correction mechanism behavior according to the command parameter, the register parameter, and the data parameter, and reading error correction mechanism behavior data from the data information, including:

determining the times of current parameter setting;

judging whether the error correction mechanism behavior needs a prefix command according to the command parameter;

if the prefix command is needed, analyzing, acquiring and sending the prefix command;

if the prefix command is not needed, the prefix command does not need to be obtained through analysis;

determining register modes according to register parameters, wherein the register modes comprise an SLC mode and an XLC mode, the SLC mode corresponds to a register related to SLC, and the XLC mode corresponds to a register related to XLC;

determining a register address according to the register parameter, determining a target register according to the register mode and the register address, and sending the target register to data information;

determining the data volume corresponding to the target register according to the data parameters, and determining the position of the data in the target register according to the data volume;

calculating the data position of the error correction mechanism behavior of the target register according to the number of times of current parameter setting and the position of data in the target register according to whether the error correction mechanism behavior is stopped, SLC information and XLC information of the data information;

and reading the error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register.

Further, after reading the error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register, the method further includes:

judging whether a next register is available according to the register parameters;

if the next register exists, the next parameter setting is carried out;

if no next register exists, determining whether the error correction mechanism behavior needs a suffix command according to the command parameter;

if the suffix command is needed, analyzing, acquiring and sending the suffix command, and judging whether to terminate the action of the error correction mechanism;

if the suffix command is not needed, judging whether to terminate the error correction mechanism behavior;

if the error correction mechanism behavior needs to be terminated, the error correction mechanism behavior is terminated.

Further, judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data includes:

if the error correction mechanism behavior does not need to be terminated, the error correction mechanism behavior data is read again, and whether the error correction mechanism behavior succeeds or not is judged according to the error correction mechanism behavior data;

if the error correction mechanism behavior is successful, terminating the error correction mechanism behavior;

if the error correction mechanism is unsuccessful, judging the register mode to be an SLC mode or an XLC mode;

if the SLC mode is adopted, determining the maximum combination number of the SLC mode according to the register parameters;

if the XLC mode is the XLC mode, determining the maximum combination number of the XLC mode according to the register parameter;

judging whether the maximum combination number of the SLC mode and the XLC mode is reached;

if the maximum combination number is not reached, setting the next parameter;

if the maximum combination number is reached, judging whether to terminate the error correction mechanism behavior;

if the error correction mechanism behavior needs to be terminated, terminating the error correction mechanism behavior;

and if the error correction mechanism behavior does not need to be terminated, performing the next parameter setting.

A second aspect of the present invention provides an error correction apparatus for a memory device, including:

the device comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring the error correction mechanism format information of the storage device when the storage device has data reading errors;

the setting module is used for setting the error correction mechanism standard format information according to the error correction mechanism format information, the error correction mechanism standard format information comprises header information and data information, the header information comprises parameters required by executing the error correction mechanism behavior, and the data information comprises data for executing the error correction mechanism behavior;

the analysis module is used for analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism behaviors;

the execution module is used for executing the error correction mechanism behavior according to the command parameter, the register parameter and the data parameter and reading error correction mechanism behavior data from the data information;

and the error correction judging module is used for judging whether the error correction mechanism behavior succeeds or not according to the error correction mechanism behavior data.

Further, the setting module includes:

the device comprises a construction unit, a first transmission unit, a second transmission unit and a control unit, wherein the construction unit is used for constructing an error correction mechanism structure body which comprises a first structure body and a second structure body;

the construction unit is also used for obtaining parameters and data of the storage equipment for executing the error correction mechanism behavior according to the error correction mechanism format information;

the building unit is also used for storing the parameters to the first structural body and storing the data to the second structural body;

the setting unit is used for obtaining head information according to the parameters in the first structural body and obtaining data information according to the data in the second structural body;

and the setting unit is also used for obtaining the standard format information of the error correction mechanism according to the header information and the data information.

Further, the execution module includes:

the first determining unit is used for determining the number of times of current parameter setting;

the command judging unit is used for judging whether the error correction mechanism behavior needs a prefix command according to the command parameter;

the command unit is used for analyzing, acquiring and sending the prefix command if the prefix command is needed;

the command unit is also used for acquiring the prefix command without analyzing if the prefix command is not needed;

the first determining unit is further used for determining register modes according to the register parameters, wherein the register modes comprise an SLC mode and an XLC mode, the SLC mode corresponds to a register related to SLC, and the XLC mode corresponds to a register related to XLC;

the first determining unit is also used for determining a register address according to the register parameter, determining a target register according to the register mode and the register address, and sending the target register to the data information;

the first determining unit is further used for determining the data volume corresponding to the target register according to the data parameters and determining the position of the data in the target register according to the data volume;

the first determining unit is further used for calculating the data position of the error correction mechanism behavior of the target register according to the number of times of current parameter setting and the position of data in the target register according to whether the error correction mechanism behavior is terminated, SLC information and XLC information of the data information;

and the reading unit is used for reading the error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register.

Further, the execution module further comprises:

the register judging unit is also used for judging whether a next register is available according to the register parameters;

the first execution unit is used for setting the next parameter if a next register exists;

the command judging unit is also used for determining whether the error correction mechanism behavior needs a suffix command according to the command parameter if the next register does not exist;

the command unit is also used for analyzing, acquiring and sending a suffix command if the suffix command is needed, and judging whether to terminate the action of an error correction mechanism;

the first termination judging unit is also used for judging whether to terminate the behavior of the error correction mechanism or not if the suffix command is not needed;

and the first termination unit is used for terminating the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated.

Further, the error correction judging module includes:

the error correction judging unit is used for reading the error correction mechanism behavior data again if the error correction mechanism behavior does not need to be terminated, and judging whether the error correction mechanism behavior succeeds or not according to the error correction mechanism behavior data;

the second termination judging unit is used for terminating the behavior of the error correction mechanism if the behavior of the error correction mechanism succeeds;

the register mode judging unit is used for judging whether the register mode is an SLC mode or an XLC mode if the error correction mechanism behavior is unsuccessful;

a second determining unit, configured to determine, if the mode is the SLC mode, a maximum combination number of the SLC mode according to the register parameter;

a second determining unit, configured to determine, if the XLC mode is true, a maximum combination number of the XLC mode according to the register parameter;

a maximum combination number judging unit for judging whether the maximum combination number of the SLC mode and the XLC mode is reached;

the second execution unit is used for setting the next parameter if the maximum combination number is not reached;

the second termination judging unit is also used for judging whether to terminate the error correction mechanism behavior if the maximum combination number is reached;

the second termination unit is used for terminating the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated;

and the second execution unit is used for setting the next parameter if the error correction mechanism behavior does not need to be terminated.

Therefore, according to the error correction method of the storage device, when data reading errors occur in the storage device, error correction mechanism format information of the storage device is obtained, error correction mechanism standard format information is set according to the error correction mechanism format information, the error correction mechanism standard format information comprises header information and data information, the header information comprises parameters required for executing error correction mechanism behaviors, the data information comprises data for executing the error correction mechanism behaviors, the header information of the error correction mechanism standard format information is analyzed to obtain command parameters, register parameters and data parameters required for executing the error correction mechanism behaviors, the error correction mechanism behaviors are executed according to the command parameters, the register parameters and the data parameters, the error correction mechanism behavior data are read from the data information, and whether the error correction mechanism behaviors are successful or not is judged according to the error correction mechanism behavior data. Compared with the prior first method which needs to write a plurality of sets of codes and the second method which uses macro-division in one set of codes, the invention only needs to set the error correction mechanism format information of the storage device into the error correction mechanism standard format information which is set into the header information and the data information and comprises the parameters and the data required by executing the error correction mechanism behavior, thereby being compatible with the storage devices with different error correction mechanism behaviors, therefore, the invention does not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage devices and does not need to use the macro-division of the error correction mechanism behaviors of a plurality of storage devices in one set of codes, thereby reducing the coding work and lowering the later maintenance cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a flow chart illustrating an error correction method for a memory device according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating cell value determination of an SLC according to the present invention;

FIG. 3 is a diagram illustrating the distribution drift of SLC of the present invention;

FIG. 4 is a schematic diagram of the NAND FLASH vendor tuning the decision voltage in accordance with the present invention;

FIG. 5 is a diagram illustrating a format of header information of standard format information of an error correction mechanism according to the present invention;

FIG. 6 is a diagram illustrating a format of standard format information of an error correction mechanism according to the present invention;

FIG. 7 is a flow chart illustrating a method for correcting errors of a memory device according to another embodiment of the present invention;

FIG. 8 is a flow chart illustrating a method for correcting errors of a memory device according to another embodiment of the present invention;

FIG. 9 is a schematic structural diagram of an embodiment of an error correction apparatus for a memory device according to the present invention;

FIG. 10 is a schematic structural diagram of another embodiment of an error correction apparatus for a memory device according to the present invention;

FIG. 11 is a schematic structural diagram of an error correction apparatus for a memory device according to another embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a memory device error correction apparatus according to still another embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a memory device error correction apparatus according to another embodiment of the present invention.

Detailed Description

The core of the invention is to provide an error correction method and an error correction device for a storage device, which do not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage devices and differentiate the error correction mechanism behaviors of various storage devices in a macro manner in one set of codes, thereby reducing the coding work and the later maintenance cost.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, an embodiment of the invention provides an error correction method for a memory device, including:

101. when the storage device has data reading errors, acquiring error correction mechanism format information of the storage device;

in this embodiment, an error correction mechanism of the memory device is also referred to as read retry, taking SLC as an example, as shown in fig. 2, if a voltage stored in the cell is greater than a determination voltage, the cell is regarded as 0, and if the voltage is less than the determination voltage, the cell is regarded as 1, the middle vertical line is the determination voltage, the right side is 0, and the left side is 1. Whether the data of the current cell is "0" or "1" is determined according to the determination voltage.

As the capacity becomes larger and larger, the stability becomes worse, and bit flipping increases, which requires a stronger error correction mechanism. The memory device is affected by conditions such as temperature and storage time, which can cause bit inversion to increase suddenly, which can cause the error correction mechanism to fail and cause data reading failure. For example, temperature variation may cause electron drift, which affects voltage distribution shift, and ultimately affects the accuracy of determining the voltage. As shown in fig. 3, the dashed line is the normal voltage profile and the solid line is the new position that has drifted. At this time, the judgment voltage is overlapped with the distribution diagram on the right, so that the judgment of the unit crossing the left is wrong, bit inversion is generated, and as the drift to the left is more, the bit inversion is more, and finally the data reading is failed.

NAND FLASH manufacturers provide a mechanism for adjusting the decision voltage, i.e., read retry, which can move the decision voltage and then reinitiate the read. As shown in fig. 4, the determination voltage is adjusted to the left to return to the middle of the distribution diagram.

In practical applications, it is not known whether the profile is shifted to the left, to the right, or to the middle and the magnitude of the shift. The direction and magnitude of the determined voltage shift is also unknown. NAND FLASH tends to offer several, even tens of combinations, including what is possible. The user attempts to adjust the decision voltage, read the data, and if the data is normal, the process ends, otherwise, the next combination is continued. In short, adjusting the decision voltage and reading again may be many times. The method is different for different NAND FLASH manufacturers, and different styles of the same manufacturer may be different. In the face of different formats of a plurality of manufacturers, the first method is that each adaptive NAND FLASH writes a set of corresponding read retry codes, and a plurality of sets of codes are formed along with the increase of the adaptive NAND FLASH; in another method, macro-differences are used in a set of codes, and corresponding codes are compiled according to different read retry formats.

In order to solve the problems of complex coding work and high later maintenance cost caused by setting a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage devices or macro-distinguishing the error correction mechanism behaviors of a plurality of storage devices in one set of codes, in the embodiment of the invention, when data reading errors occur in the storage devices, the error correction mechanism behaviors are started, and the format information of the error correction mechanism of the current storage device is firstly obtained. The format information of the error correction mechanism is obtained by factory setting of a NAND FLASH manufacturer.

102. Setting standard format information of an error correction mechanism according to the format information of the error correction mechanism, wherein the standard format information of the error correction mechanism comprises header information and data information, the header information comprises parameters required for executing the behavior of the error correction mechanism, and the data information comprises data for executing the behavior of the error correction mechanism;

in this embodiment, according to the error correction mechanism format information, parameters and data required for executing the error correction mechanism behavior are obtained, and error correction mechanism standard format information is set and generated, where the error correction mechanism standard format information includes header information and data information, the header information includes the parameters required for executing the error correction mechanism behavior, and the data information includes the data for executing the error correction mechanism behavior;

specifically, the parameters included in the header information are as shown in fig. 5, and include 12 parameters, which are specifically as follows:

the first parameter represents the number of registers corresponding to the XLC mode adjustment decision voltage of the adaptive NAND FLASH manufacturer, and the XLC generally refers to MLC and TLC and QLC. For example, TLC has 7 decision voltages, some TLC by heilish is 7 registers, while TLC by magnesium light only requires 2 registers;

for the second parameter, a register corresponds to several data quantities, for example, a register corresponds to one data quantity for a Hercules, and a register corresponds to four data quantities for a magnesium light;

the third parameter, XLC mode, is the maximum number of times the decision voltage needs to be adjusted as provided by the NAND FLASH manufacturer. If a read data error occurs, the decision voltage is adjusted, perhaps unsuccessfully for the first time, possibly many times. The manufacturer provides many combinations, several combinations, even tens of combinations, one trial after another until the data is correct. If all the attempts are finished and the data is still wrong, the read retry is abandoned;

the fourth parameter, SLC mode, requires adjustment of the maximum number of times of determining the voltage, and this XLC NAND FLASH may also have an SLC mode, and may have two read retry manners at the same time, and determine which of the current read retry is selected according to whether the XLC or SLC mode is used in the current error place. If the NAND FLASH is only in an SLC mode, the XLC information is set to be 0, and the NAND FLASH is not used;

in the fifth parameter, registers corresponding to an XLC mode are a plurality of continuous numerical values, only the starting address is recorded, the number of the first parameter is recorded, the starting value is recorded, and the number of the first parameter is recorded, so that how many XLC registers need to be operated;

the sixth parameter, SLC mode only has a decision voltage, so there must be only one register, the starting value is the only register;

a seventh parameter, starting read retry has a prefix command needed, and has no need, which is a mark to indicate whether the prefix command is needed or not;

the eighth parameter, if a prefix command is required, is then viewed. Some prefixes command the first register to be sent once ahead, and some registers need to be sent once ahead. Command 36h is required only once at the beginning and EFh is required each time the register is written, this parameter represents these two modes, mode 1: only once; mode 2: with the register multiple times;

the ninth parameter, whether the content of the prefix command is 36h, EFh, or another value, is not limited;

a tenth parameter, some NAND flashes send a round of assembly, requiring an end command;

an eleventh parameter, the content of the suffix command, if the suffix command is needed, if the value is not needed to be invalid;

a twelfth parameter, whether termination action is required; for example, after Toshiba needs to complete read retry, a termination action is initiated to restore the determination voltage as before.

Specifically, the format of the standard format information of the error correction mechanism is shown in fig. 6, and includes header information and data information, and the data format of the data information includes 3 portions including XLC data, SLC data, and termination action data.

103. Analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism behavior;

in this embodiment, the header information of the information in the standard format of the error correction mechanism is analyzed, and since the header information includes parameters required for executing the error correction mechanism, command parameters, register parameters, and data parameters required for executing the error correction mechanism can be obtained, specifically, parameters shown in fig. 5.

104. Executing an error correction mechanism behavior according to the command parameter, the register parameter and the data parameter, and reading error correction mechanism behavior data from the data information;

in this embodiment, after obtaining the command parameter, the register parameter, and the data parameter, the execution step of the error correction mechanism behavior, the mode, number, address, and amount of data corresponding to one register of the error correction mechanism behavior, and the like can be determined, so that the error correction mechanism behavior data can be read from the data information.

105. And judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data.

In the embodiment, after the error correction mechanism behavior data is read, whether the error correction mechanism behavior data is correct or not is judged, and if the error correction mechanism behavior data is incorrect, the error correction mechanism behavior is not successful; if the error correction mechanism is correct, the error correction mechanism is indicated to act successfully.

In the embodiment of the invention, when the data reading error occurs in the storage device, the error correction mechanism format information of the storage device is obtained, the error correction mechanism standard format information is set according to the error correction mechanism format information, the error correction mechanism standard format information comprises header information and data information, the header information comprises parameters required by executing the error correction mechanism behavior, the data information comprises data for executing the error correction mechanism behavior, the header information of the error correction mechanism standard format information is analyzed to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism behavior, the error correction mechanism behavior is executed according to the command parameters, the register parameters and the data parameters, the error correction mechanism behavior data is read from the data information, and whether the error correction mechanism behavior succeeds or not is judged according to the error correction mechanism behavior data. Compared with the prior first method which needs to write a plurality of sets of codes and the second method which uses macro-division in one set of codes, the invention only needs to set the error correction mechanism format information of the storage device into the error correction mechanism standard format information which is set into the header information and the data information and comprises the parameters and the data required by executing the error correction mechanism behavior, thereby being compatible with the storage devices with different error correction mechanism behaviors, therefore, the invention does not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage devices and does not need to use the macro-division of the error correction mechanism behaviors of a plurality of storage devices in one set of codes, thereby reducing the coding work and lowering the later maintenance cost.

Optionally, with reference to the embodiment shown in fig. 1, in some embodiments of the present invention, the setting of the error correction mechanism standard format information according to the error correction mechanism format information includes:

constructing an error correction mechanism structure body which comprises a first structure body and a second structure body;

storing the parameters to a first structure body and storing the data to a second structure body;

In the embodiment of the present invention, as shown in fig. 5 and fig. 6, when the error correction mechanism standard format information is set according to the error correction mechanism format information, an error correction mechanism structure needs to be constructed first, where the error correction mechanism structure includes a first structure and a second structure, where the first structure is used for storing parameters, that is, a structure of header information, and the parameters in the error correction mechanism format information are stored in the formats shown in fig. 5, respectively, so as to obtain the header information; the second structure is used for storing data, and is used for storing XLC data corresponding to a register in an XLC mode, SLC data corresponding to a register in an SLC mode and data of termination behaviors in sequence. The three parts of contents are determined according to actual conditions, and if the action is not required to be terminated, the action data is not terminated. If only SLC mode, no XLC data. One set of data, representing the data required for a read retry, e.g. TLC for Haishi, is 7 data. It should be noted that, if there is no data in a certain area in the stored XLC data, SLC data, and termination data, the following data is shifted forward and kept close to avoid space waste. These latter data sizes are determined according to reality, except that the header information is of a fixed size.

Referring to fig. 7, an embodiment of the invention provides a method for correcting errors of a memory device, including:

701. when the storage device has data reading errors, acquiring error correction mechanism format information of the storage device;

refer to step 101 of the embodiment shown in fig. 1 for details.

702. Setting standard format information of an error correction mechanism according to the format information of the error correction mechanism, wherein the standard format information of the error correction mechanism comprises header information and data information, the header information comprises parameters required for executing the behavior of the error correction mechanism, and the data information comprises data for executing the behavior of the error correction mechanism;

please refer to step 102 of the embodiment shown in fig. 1 for details.

703. Analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism;

please refer to step 103 of the embodiment shown in fig. 1 for details.

704. Determining the times of current parameter setting;

in this embodiment, after the action of the error correction mechanism is started, the number of times of the current parameter setting is determined, because there may be multiple times of adjusting the determination voltage, and then the determined direction and number of times of voltage movement also need to be adjusted accordingly, so the number of times of the current parameter setting needs to be recorded is the second round.

705. Judging whether the error correction mechanism behavior needs a prefix command according to the command parameter;

in this embodiment, taking the format of the header information shown in fig. 5 as an example, first, whether a prefix command is needed is determined according to the seventh parameter, and if so, step 706 is executed; if not, step 707 is performed.

706. Analyzing, acquiring and sending a prefix command;

in this embodiment, if a prefix command is required, the prefix command is parsed and acquired, and a register mode is determined according to the eighth parameter, the eighth parameter (the prefix command mode), and the mode 1: prefix commands are sent only before the first register, mode 2: this means that a prefix command is needed before each register, and specifically, the prefix command content is determined by the ninth parameter, command 36h is needed only once at the beginning, and command EFh is needed each time a register is written.

Specifically, step 7061 is prefix mode 2, and step 7062 determines and sends prefix command content according to a ninth parameter; step 7063 is prefix mode 1, in case of prefix mode 1, step 7064 needs to further determine whether it is the first time, if so, step 7062 is executed to determine and transmit the prefix command content through the ninth parameter, and if not, step 708 is executed.

707. The prefix command does not need to be obtained through analysis;

in this embodiment, if the prefix command is not needed, the prefix command does not need to be parsed.

708. Determining register modes according to register parameters, wherein the register modes comprise an SLC mode and an XLC mode, the SLC mode corresponds to a register related to SLC, and the XLC mode corresponds to a register related to XLC;

in this embodiment, the register mode is determined according to the third parameter and the fourth parameter, and it is determined that the behavior is for XLC or SLC, and if the behavior is for XLC, the register related to XLC is used, and if the behavior is for SLC, the register related to SLC is used.

709. Determining a register address according to the register parameter, determining a target register according to the register mode and the register address, and sending the target register to data information;

in this embodiment, specifically, if the XLC mode is selected, in step 7091, the register address of the register associated with the XLC is determined according to the fifth parameter; if it is SLC mode, the address of the register of the SLC-related register is determined according to the sixth parameter in step 7092, and the SLC register has only one register after the SLC register starts. Step 7093: judging the register which is the sending number, accumulating on the basis of the register address, starting if the register is sent for the first time, adding one to the register address if the register is sent for the second time, and so on, determining a target register and sending the target register to the data information.

710. Determining the data volume corresponding to the target register according to the data parameters, and determining the position of the data in the target register according to the data volume;

in this embodiment, several data volumes corresponding to the target register are determined according to the second parameter, and the position of the data in the target register is determined according to the data volumes.

711. Calculating the data position of the error correction mechanism behavior of the target register according to the number of times of current parameter setting and the position of data in the target register according to whether the error correction mechanism behavior is stopped, SLC information and XLC information of the data information;

in this embodiment, the specific process is as follows: step 7111, first, determining whether to terminate the error correction mechanism; if yes, executing step 7112, according to the SLC information and the XLC information, combining the number of times of current parameter setting and the position of data in the target register, calculating to obtain the error correction mechanism behavior data position of the target register, it should be noted that this data position is in the termination action data area of the data information; if not, executing step 7113 to calculate an error correction mechanism behavior data position of the target register according to the SLC information and the XLC information, by combining the number of times of current parameter setting and the position of the data in the target register, where it is to be noted that the data position is in the SLC data area or the XLC data area of the data information.

712. Reading error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register;

in this embodiment, the error correction mechanism behavior data is read from the termination action data area, the SLC data area, or the XLC data area according to the error correction mechanism behavior data position of the target register.

713. And judging whether the error correction mechanism behavior succeeds or not according to the error correction mechanism behavior data.

Please refer to step 105 of the embodiment shown in fig. 1 for details.

In conjunction with the embodiment shown in fig. 7, as shown in fig. 8, an embodiment of the present invention provides a method for correcting errors of a memory device, including:

801. when the storage device has data reading errors, acquiring error correction mechanism format information of the storage device;

please refer to step 701 of the embodiment shown in fig. 7 for details.

802. Setting standard format information of an error correction mechanism according to the format information of the error correction mechanism, wherein the standard format information of the error correction mechanism comprises header information and data information, the header information comprises parameters required for executing the behavior of the error correction mechanism, and the data information comprises data for executing the behavior of the error correction mechanism;

please refer to step 702 of the embodiment shown in fig. 7 for details.

803. Analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required by executing the error correction mechanism behavior;

refer to step 703 of the embodiment shown in FIG. 7 for further details.

804. Determining the times of current parameter setting;

please refer to step 704 of the embodiment shown in fig. 7 for details.

805. Judging whether the error correction mechanism behavior needs a prefix command or not according to the command parameters;

see step 707 of the embodiment shown in figure 7 for details.

806. Analyzing, acquiring and sending a prefix command;

refer to step 706 of the embodiment shown in FIG. 7 for details.

807. Prefix commands do not need to be obtained through analysis;

see step 707 of the embodiment shown in figure 7 for details.

808. Determining register modes according to the register parameters, wherein the register modes comprise an SLC mode and an XLC mode, the SLC mode corresponds to an SLC-related register, and the XLC mode corresponds to an XLC-related register;

refer to step 708 of the embodiment shown in FIG. 7 for details.

809. Determining a register address according to the register parameter, determining a target register according to the register mode and the register address, and sending the target register to data information;

refer to step 709 of the embodiment shown in FIG. 7 for details.

810. Determining the data volume corresponding to the target register according to the data parameters, and determining the position of the data in the target register according to the data volume;

please refer to step 710 of the embodiment shown in fig. 7 for details.

811. Calculating the data position of the error correction mechanism behavior of the target register according to the number of times of current parameter setting and the position of data in the target register according to whether the error correction mechanism behavior is stopped, the SLC information and the XLC information of the data information;

see step 711 of the embodiment shown in FIG. 7 for details.

812. Reading error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register;

please refer to step 712 of the embodiment shown in fig. 7 for details.

813. Judging whether a next register exists according to the register parameters;

in this embodiment, it is determined whether there is a next register according to the first parameter, and since the first parameter represents the number of registers corresponding to the XLC mode adjustment determination voltage of the NAND FLASH manufacturer adapted this time, it is also determined whether there is a next register, and if there is a next register, the next parameter setting is performed, that is, step 804 is performed; if not, step 814 is performed.

814. Determining whether the error correction mechanism behavior needs a suffix command according to the command parameter;

in this embodiment, if there is no next register, which means that the register and data transmission in this round is completed, it is determined whether the error correction mechanism behavior needs a suffix command according to the tenth parameter, and if so, step 815 is executed; if not, step 816 is performed.

815. Analyzing, acquiring and sending a suffix command, and judging whether to terminate the error correction mechanism behavior;

in this embodiment, if a suffix command is needed, a suffix command is obtained and sent according to the eleventh parameter analysis, and it is determined whether to terminate the error correction mechanism, and step 816 is executed.

816. Judging whether to terminate the error correction mechanism behavior;

in this embodiment, if a suffix command is not needed, whether to terminate the error correction mechanism behavior is determined according to the twelfth parameter, and if yes, step 817 is performed; if not, step 818 is performed.

817. Terminating the error correction mechanism behavior;

in this embodiment, if the error correction mechanism behavior needs to be terminated, the termination register and the data are sent to terminate the error correction mechanism behavior.

818. Re-reading the error correction mechanism behavior data, and judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data;

in this embodiment, if the error correction mechanism behavior does not need to be terminated, the error correction mechanism behavior data is read again, whether the error correction mechanism behavior succeeds or not is judged according to the error correction mechanism behavior data, and if the error correction mechanism behavior succeeds, step 817 is executed; if not, step 819 is performed.

819. Judging whether the register mode is an SLC mode or an XLC mode;

in this embodiment, if the behavior of the error correction mechanism is unsuccessful, the register mode is determined to be the SLC mode or the XLC mode, and if the register mode is the SLC mode, step 820 is executed; if XLC mode, go to step 821;

820. determining the maximum combination number of the SLC mode according to the register parameter;

in this embodiment, if it is the SLC mode, the maximum combination of SLC modes is determined according to the fourth parameter.

821. Determining the maximum combination number of the XLC mode according to the register parameter;

in this embodiment, if the mode is XLC mode, the maximum combination of SLC modes is determined according to the third parameter.

822. Judging whether the maximum combination number of the SLC mode and the XLC mode is reached;

in this embodiment, it is determined whether the maximum combination number of the SLC mode and the XLC mode is reached, if yes, step 823 is performed; if not, the next parameter setting is performed, and step 804 is executed.

823. Judging whether to terminate the error correction mechanism behavior;

in this embodiment, if the maximum number of combinations is reached, it is determined whether to terminate the error correction mechanism behavior, and if necessary, step 817 is performed to terminate the error correction mechanism behavior; if not, the next parameter setting is performed, and step 804 is executed.

In the above embodiments, the error correction method of the memory device is specifically described, and the error correction apparatus of the memory device to which the error correction method of the memory device is applied is described below by the embodiments.

Referring to fig. 9, an embodiment of the invention provides an error correction apparatus for a memory device, including:

an obtaining module 901, configured to obtain format information of an error correction mechanism of a storage device when a data reading error occurs in the storage device;

a setting module 902, configured to set error correction mechanism standard format information according to the error correction mechanism format information, where the error correction mechanism standard format information includes header information and data information, the header information includes parameters required for executing an error correction mechanism behavior, and the data information includes data for executing the error correction mechanism behavior;

the analysis module 903 is configured to analyze header information of the error correction mechanism standard format information to obtain a command parameter, a register parameter, and a data parameter required for executing an error correction mechanism behavior;

an executing module 904, configured to execute an error correction mechanism behavior according to the command parameter, the register parameter, and the data parameter, and read error correction mechanism behavior data from the data information;

and the error correction judging module 905 is configured to judge whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data.

In the embodiment of the present invention, when a data read error occurs in a storage device, an obtaining module 901 obtains error correction mechanism format information of the storage device, a setting module 902 sets error correction mechanism standard format information according to the error correction mechanism format information, the error correction mechanism standard format information includes header information and data information, the header information includes parameters required for executing an error correction mechanism behavior, the data information includes data for executing the error correction mechanism behavior, an analyzing module 903 analyzes the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required for executing the error correction mechanism behavior, an executing module 904 executes the error correction mechanism behavior according to the command parameters, the register parameters and the data parameters, reads the error correction mechanism behavior data from the data information, and an error correction judging module 905 judges whether the error correction mechanism behavior succeeds according to the error correction mechanism behavior data. Compared with the prior first method which needs to write a plurality of sets of codes and the second method which uses macro-division in one set of codes, the invention only needs to set the error correction mechanism format information of the storage device into the error correction mechanism standard format information which is set into the header information and the data information and comprises the parameters and the data required by executing the error correction mechanism behavior, thereby being compatible with the storage devices with different error correction mechanism behaviors, therefore, the invention does not need to set a plurality of sets of codes aiming at the error correction mechanism behaviors of different storage devices and does not need to use the macro-division of the error correction mechanism behaviors of a plurality of storage devices in one set of codes, thereby reducing the coding work and lowering the later maintenance cost.

In conjunction with the embodiment shown in fig. 9, optionally, as shown in fig. 10, in some embodiments of the present invention, the setting module 902 includes:

a constructing unit 1001 configured to construct an error correction mechanism structure body, the error correction mechanism structure body including a first structure body and a second structure body;

the constructing unit 1001 is further configured to obtain parameters and data of the storage device executing the error correction mechanism behavior according to the error correction mechanism format information;

the building unit 1001 is further configured to store the parameters in the first structural body, and store the data in the second structural body;

a setting unit 1002, configured to obtain header information according to parameters in the first structural body, and obtain data information according to data in the second structural body;

the setting unit 1002 is further configured to obtain standard format information of an error correction mechanism according to the header information and the data information.

In the embodiment of the present invention, as shown in fig. 5 and fig. 6, when setting the standard format information of the error correction mechanism according to the format information of the error correction mechanism, the constructing unit 1001 needs to construct an error correction mechanism structure first, where the error correction mechanism structure includes a first structure and a second structure, where the first structure is used to store parameters, that is, a structure of the header information, and the setting unit 1002 stores the parameters in the format information of the error correction mechanism into the format shown in fig. 5, respectively, so as to obtain the header information; the second structure is for storing data, and the setting unit 1002 sequentially stores XLC data corresponding to a register in the XLC mode, SLC data corresponding to a register in the SLC mode, and data of termination behavior. The three parts of contents are determined according to actual conditions, and if the action does not need to be terminated, the action data is not terminated. If only SLC mode, no XLC data. One set of data, representing the data required for a read retry, e.g. TLC for Haishi, is 7 data. It should be noted that, if there is no data in a certain area, the stored XLC data, SLC data, and termination data are moved forward and kept close to each other, so as to avoid space waste. These latter data sizes are determined according to reality, except that the header information is fixed in size.

In conjunction with the embodiment shown in fig. 10, optionally, as shown in fig. 11, in some embodiments of the present invention, the executing module 904 includes:

a first determination unit 1101 for determining the number of times of current parameter setting;

a command judgment unit 1102, configured to judge whether an error correction mechanism behavior requires a prefix command according to a command parameter;

a command unit 1103, configured to parse, acquire, and send a prefix command if the prefix command is needed;

the command unit 1103 is further configured to, if the prefix command is not needed, obtain the prefix command without parsing;

the first determining unit 1101 is further configured to determine register modes according to the register parameters, where the register modes include an SLC mode and an XLC mode, where the SLC mode corresponds to an SLC-related register, and the XLC mode corresponds to an XLC-related register;

the first determining unit 1101 is further configured to determine a register address according to the register parameter, determine a target register according to the register mode and the register address, and send the target register to the data information;

the first determining unit 1101 is further configured to determine a data amount corresponding to the target register according to the data parameter, and determine a position of data in the target register according to the data amount;

the first determining unit 1101 is further configured to calculate, according to the number of times that the current parameter is set and the position of the data in the target register, the error correction mechanism behavior data position of the target register according to whether the error correction mechanism behavior is terminated, SLC information and XLC information of the data information;

and a reading unit 1104 for reading the error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register.

In this embodiment of the present invention, the first determining unit 1101 is specifically configured to execute

steps

704, 708, 709, 710, and 711 in the embodiment shown in fig. 7, the command determining unit 1102 is configured to execute step 705 in the embodiment shown in fig. 7, the command unit 1103 is configured to execute steps 706 and 707 in the embodiment shown in fig. 7, and the reading unit 1104 is configured to execute step 712 in the embodiment shown in fig. 7.

In conjunction with the embodiment shown in fig. 11, optionally, as shown in fig. 12, in some embodiments of the present invention, the executing module 904 further includes:

the register judging unit 1201 is further configured to judge whether a next register exists according to the register parameter;

a first execution unit 1202, configured to perform next parameter setting if there is a next register;

the command determining unit 1102 is further configured to determine whether a suffix command is required for an error correction mechanism behavior according to the command parameter if there is no next register;

the command unit 1103 is further configured to, if a suffix command is needed, parse, acquire and send the suffix command, and determine whether to terminate the error correction mechanism behavior;

the first termination judging unit 1203 is further configured to judge whether to terminate the error correction mechanism behavior if the suffix command is not needed;

a first terminating unit 1204, configured to terminate the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated.

In the embodiment of the present invention, the register determining unit 1201 is specifically configured to perform step 813 in the embodiment shown in fig. 8, the first executing unit 1202 is specifically configured to perform step 804 in the embodiment shown in fig. 8, the first termination determining unit 1203 is specifically configured to perform step 816 in the embodiment shown in fig. 8, and the first terminating unit 1204 is specifically configured to perform step 817 in the embodiment shown in fig. 8.

With reference to the embodiment shown in fig. 12, optionally, as shown in fig. 13, in some embodiments of the present invention, the error correction determining module 905 includes:

an error correction judging unit 1301, configured to re-read the error correction mechanism behavior data if the error correction mechanism behavior does not need to be terminated, and judge whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data;

a second terminating unit 1302, configured to terminate the error correction mechanism if the error correction mechanism succeeds in acting;

a register mode determining unit 1303, configured to determine that the register mode is the SLC mode or the XLC mode if the error correction mechanism behavior is unsuccessful;

a second determining unit 1304, configured to determine, if the SLC mode is established, a maximum combination number of the SLC mode according to the register parameter;

a second determining unit 1304, configured to determine, if the XLC mode is true, a maximum combination number of the XLC mode according to the register parameter;

a maximum combination number determining unit 1305, configured to determine whether the maximum combination numbers of the SLC mode and the XLC mode are reached;

a second execution unit 1306, configured to perform next parameter setting if the maximum number of combinations is not reached;

a second termination judging unit 1307, configured to judge whether to terminate the error correction mechanism behavior if the maximum number of combinations is reached;

a second termination unit 1302, configured to terminate the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated;

and a second execution unit 1306, configured to perform next parameter setting if the error correction mechanism behavior does not need to be terminated.

In this embodiment of the present invention, the error correction determining unit 1301 is specifically configured to perform step 818 in the embodiment shown in fig. 8, the second terminating unit 1302 is specifically configured to perform step 817 in the embodiment shown in fig. 8, the register pattern determining unit 1303 is specifically configured to perform step 819 in the embodiment shown in fig. 8, the second determining unit 1304 is specifically configured to perform step 820 in the embodiment shown in fig. 8, the second determining unit 1304 is specifically configured to perform step 821 in the embodiment shown in fig. 8, the maximum combination number determining unit 1305 is specifically configured to perform step 822 in the embodiment shown in fig. 8, the second executing unit 1306 is specifically configured to perform step 804 in the embodiment shown in fig. 8, and the second terminating determining unit 1307 is specifically configured to perform step 823 in the embodiment shown in fig. 8.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for error correction in a memory device, comprising:

when data reading errors occur in the storage device, acquiring error correction mechanism format information of the storage device;

setting error correction mechanism standard format information according to the error correction mechanism format information, wherein the error correction mechanism standard format information comprises header information and data information, the header information comprises parameters required for executing an error correction mechanism behavior, and the data information comprises data for executing the error correction mechanism behavior;

analyzing the header information of the error correction mechanism standard format information to obtain command parameters, register parameters and data parameters required for executing the error correction mechanism behaviors;

executing the error correction mechanism behavior according to the command parameter, the register parameter and the data parameter, and reading error correction mechanism behavior data from the data information;

and judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data.

2. The method according to claim 1, wherein said setting error correction scheme standard format information according to said error correction scheme format information comprises:

storing the parameters to the first structure and storing the data to the second structure;

obtaining head information according to the parameters in the first structure body, and obtaining data information according to the data in the second structure body;

3. The method of claim 2, wherein said performing the error correction mechanism behavior based on the command parameter, the register parameter, and the data parameter, reading error correction mechanism behavior data from the data information, comprises:

determining the times of current parameter setting;

determining register modes according to the register parameters, wherein the register modes comprise a single-layer unit SLC mode and a multi-layer unit XLC mode, the SLC mode corresponds to a register related to SLC, and the XLC mode corresponds to a register related to XLC;

determining a register address according to the register parameter, determining a target register according to the register mode and the register address, and sending the target register to the data information;

calculating the data position of the error correction mechanism behavior of the target register according to the number of times of current parameter setting and the position of data in the target register according to whether the error correction mechanism behavior is terminated, the SLC information and the XLC information of the data information;

and reading error correction mechanism behavior data from the data information according to the error correction mechanism behavior data position of the target register.

4. The method according to claim 3, further comprising, after reading the error correction mechanism behavior data from the data information according to the error correction mechanism behavior data location of the target register:

if the next register exists, performing next parameter setting;

if the next register is not available, determining whether the error correction mechanism behavior needs a suffix command according to the command parameter;

if the suffix command is needed, analyzing, acquiring and sending the suffix command, and judging whether to terminate the error correction mechanism behavior;

and if the error correction mechanism behavior needs to be terminated, terminating the error correction mechanism behavior.

5. The method of claim 4, wherein determining whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data comprises:

if the error correction mechanism behavior does not need to be terminated, the error correction mechanism behavior data is read again, and whether the error correction mechanism behavior is successful or not is judged according to the error correction mechanism behavior data;

if the error correction mechanism is not successful, judging that the register mode is the SLC mode or the XLC mode;

if the SLC mode is adopted, determining the maximum combination number of the SLC mode according to the register parameter;

if the maximum combination number is not reached, setting the next parameter;

if the maximum combination number is reached, judging whether the error correction mechanism behavior is terminated;

and if the error correction mechanism behavior does not need to be terminated, setting the next parameter.

6. An error correction apparatus for a storage device, comprising:

a setting module, configured to set error correction mechanism standard format information according to the error correction mechanism format information, where the error correction mechanism standard format information includes header information and data information, the header information includes parameters required for executing an error correction mechanism behavior, and the data information includes data for executing the error correction mechanism behavior;

and the error correction judging module is used for judging whether the error correction mechanism behavior is successful according to the error correction mechanism behavior data.

7. The error correction apparatus according to claim 6, wherein the setting module comprises:

a construction unit configured to construct an error correction mechanism structure body including a first structure body and a second structure body;

the construction unit is further configured to obtain parameters and data of the storage device executing the error correction mechanism behavior according to the error correction mechanism format information;

the building unit is further configured to store the parameter to the first structural body, and store the data to the second structural body;

a setting unit, configured to obtain header information according to the parameter in the first structural body, and obtain data information according to the data in the second structural body;

the setting unit is further configured to obtain standard format information of an error correction mechanism according to the header information and the data information.

8. The error correction apparatus according to claim 7, wherein the execution module comprises:

the command unit is used for analyzing and acquiring and sending the prefix command if the prefix command is needed;

the command unit is further configured to obtain the prefix command without parsing if the prefix command is not needed;

the first determining unit is further configured to determine register modes according to the register parameters, where the register modes include a single-level cell SLC mode and a multi-level cell XLC mode, where the SLC mode corresponds to an SLC-related register, and the XLC mode corresponds to an XLC-related register;

the first determining unit is further configured to determine a register address according to the register parameter, determine a target register according to the register mode and the register address, and send the target register to the data information;

the first determining unit is further configured to determine a data amount corresponding to the target register according to the data parameter, and determine a position of data in the target register according to the data amount;

the first determining unit is further configured to calculate, according to the number of times that the current parameter is set and the position of the data in the target register, the error correction mechanism behavior data position of the target register according to whether the error correction mechanism behavior is terminated, SLC information of the data information, and XLC information;

9. The error correction apparatus according to claim 8, wherein the execution module further comprises:

the first execution unit is used for setting the next parameter if the next register exists;

the command judging unit is further configured to determine whether the error correction mechanism behavior requires a suffix command according to the command parameter if the next register is absent;

the command unit is also used for analyzing, acquiring and sending the suffix command if the suffix command is needed, and judging whether to terminate the error correction mechanism behavior;

a first termination judging unit, further configured to judge whether to terminate the error correction mechanism behavior if the suffix command is not needed;

a first termination unit, configured to terminate the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated.

10. The apparatus according to claim 9, wherein the error correction determining module comprises:

a second termination unit, configured to terminate the error correction mechanism behavior if the error correction mechanism behavior is successful;

a register mode determining unit, configured to determine that the register mode is the SLC mode or the XLC mode if the error correction mechanism behavior is unsuccessful;

a second determining unit, configured to determine, if the register is in the SLC mode, a maximum combination number of the SLC mode according to the register parameter;

a second determining unit, configured to determine, if the XLC mode is the XLC mode, a maximum combination number of the XLC mode according to the register parameter;

a maximum combination number determining unit for determining whether the maximum combination numbers of the SLC mode and the XLC mode are reached;

a second termination judging unit, further configured to judge whether to terminate the error correction mechanism behavior if the maximum number of combinations is reached;

a second termination unit, configured to terminate the error correction mechanism behavior if the error correction mechanism behavior needs to be terminated;