CN111474990A - Hard disk backboard - Google Patents
Hard disk backboard Download PDFInfo
- Publication number
- CN111474990A CN111474990A CN202010154814.6A CN202010154814A CN111474990A CN 111474990 A CN111474990 A CN 111474990A CN 202010154814 A CN202010154814 A CN 202010154814A CN 111474990 A CN111474990 A CN 111474990A
- Authority
- CN
- China
- Prior art keywords
- hard disk
- cpu
- connector
- disk connector
- ssd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims abstract description 5
- 238000013403 standard screening design Methods 0.000 description 29
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100327917 Caenorhabditis elegans chup-1 gene Proteins 0.000 description 1
- 241000282414 Homo sapiens Species 0.000 description 1
- 241000244317 Tillandsia usneoides Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/187—Mounting of fixed and removable disk drives
Abstract
The invention provides a hard disk backboard, comprising: the hard disk comprises a first hard disk connector and a second hard disk connector, wherein the first hard disk connector is connected with a first CPU, the second hard disk connector is connected with a second CPU, and the first hard disk connector is in communication connection with the second hard disk connector. The invention effectively solves the problem that in the E1.S SSD storage system, when a CPU needs to read and write data across PCIe Switch and the E1.S SSD, another UPI bus between the CPU and the CPU is occupied, thereby affecting the performance of the whole system.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a hard disk backboard.
Background
With the continuous integration of technologies such as internet of things, social networks, cloud computing and the like into our lives, data accumulated by human beings continuously grow and accumulate in various fields such as internet, communication, finance, commerce, medical treatment and the like, and the whole data center industry is impacted by the unprecedented growing trend of mass data.
Against the background of such market demands, how to increase the storage capacity of the server in a limited space becomes important. The e1.s SSD is a new type of hard disk that can provide larger storage capacity in a smaller size and higher data read and write rates than other types of hard disks. If the E1.S SSD needs to be used in the server, a backboard supporting the E1.S SSD needs to be designed, and the E1.S SSD is connected with a CPU on a server mainboard through the backboard. According to the size definition of the 1U server and the size definition of the E1.S SSD, the 1U server can support 32E1.S SSDs at most, and the patent provides a design method for supporting 32E1.S SSD backplanes.
The types of hard disks used for storing data by the current server include SAS SATA hard disks, NVME hard disks, etc., the e1.s SSD is a new hard disk type, and compared with other types of hard disks, a larger storage capacity can be provided in a smaller size, and the data read-write speed is also higher, the e1.s SSD establishes a connection with a CPU on a server motherboard through a backplane, and at present, there is no backplane capable of supporting the e1.s SSD.
Compared with the E1.S SSD, the conventional SAS SATA hard disk and NVME hard disk ruler are also larger, 10 2.5 hard disks can be placed in a 1U server applied to a 19' cabinet at most, so that the storage density is lower, and the heat dissipation effect of the server is poor due to the larger size of the hard disks. Meanwhile, compared with the E1.S SSD, the SAS SATA hard disk has a slower read-write speed. In order to use the e1.s SSD in the server, a backplane supporting the e1.s SSD needs to be designed currently, and the e1.s SSD establishes a connection with the CPU on the server motherboard through the backplane.
Disclosure of Invention
In view of the above-mentioned deficiencies of the prior art, the present invention provides a hard disk backplane to solve the above-mentioned technical problems.
The invention provides a hard disk backboard, comprising:
the hard disk comprises a first hard disk connector and a second hard disk connector, wherein the first hard disk connector is connected with a first CPU, the second hard disk connector is connected with a second CPU, and the first hard disk connector is in communication connection with the second hard disk connector.
Further, the first hard disk connector and the second hard disk connector establish a connection link through PCIe 4.0.
Furthermore, the first hard disk connector, the second hard disk connector, the first CPU and the second CPU all adopt homologous clocks.
Further, the first hard disk connector is connected with fifteen hard disks; and the second hard disk connector is connected with fifteen hard disks.
Furthermore, the first hard disk connector and the second hard disk connector and the hard disk adopt the same source clock.
Further, the hard disk is an E1.S SSD.
Further, the first CPU and the second CPU are connected by a UPI bus.
Further, the first hard disk connector and the second hard disk connector are provided with 100 PCIe links.
The beneficial effect of the invention is that,
the invention provides a hard disk backboard, which supports a CPU to read and write data of an E1.S SSD across a PCIe Switch in an E1.S SSD storage system comprising 2 CPUs and 2PCIe switches, and does not need to occupy a UPI bus between another CPU and the CPU. The backplane uses a clock topology that uses a homogeneous clock for the CPU and PCIe Switch, and a homogeneous clock for PCIe Switch and e1. sssd. The invention effectively solves the problem that in the E1.S SSD storage system, when a CPU needs to read and write data across PCIe Switch and the E1.S SSD, another UPI bus between the CPU and the CPU is occupied, thereby affecting the performance of the whole system.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a hard disk backplane according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a hard disk backplane according to an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
As shown in fig. 1, the present embodiment provides a hard disk backplane, and the specific structure is introduced as follows:
the hard disk drive comprises a first hard disk connector Swtich0 and a second hard disk connector Swtich1, wherein the first hard disk connector is connected with a first CPU (CPU0), the second hard disk connector is connected with a second CPU (CPU1), and the first hard disk connector is in communication connection with the second hard disk connector.
A connection link is established between PCIe Swtichs through a PCIe4.0, and when the CUP1 needs to read and write the E1.S SSD attached under the Swtich0, data flow reaches the PCIeSwtich0 through the PCIe4.0 link between the PCIe Swtichs, so that the read-write operation is completed. The whole read-write process does not occupy the computing resource of the CPU0 and the UPI bus resource between the CPUs. Similarly, when the CPU0 needs to read and write the e1.s SSD attached under the switch1, it will not occupy the computing resources of the CPU1 and the UPI bus resources between the CPUs. The backplane uses a clock scheme that uses a homogeneous clock for the CPU and PCIe Switch, and a homogeneous clock for PCIe Switch and e1.s SSD.
Example 2
Referring to fig. 2, the present embodiment provides a hard disk backplane, which is specifically described as follows:
the 32E1.S SSD backplane comprises 2PCIe switches, and the PCIe switches are Microsmi PM 40100. The Stack6 of the PCIe Switch0 is connected with the Stack6 of the PCIe Switch1, and when the CPU needs to read and write the e1.s SSD across the PCIe Switch, the data flow uses the PCIe4.0 link between the stacks 6, thereby avoiding occupying the computing resources of another CPU and the UPI bus resources between the CPUs.
The specific scheme is that the server mainboard provides 100M clock to PCIe _ REFC L K _ H1 and PCIe _ REFC L K _ H2 of the PCIe Switch, and the C L K Generator provides 100M clock to PCIe _ REFC L K _ D of the PCIe Switch, and the clock outputs PCIe _ REFC 8K _ S2, PCIe _ REFC L K _ S3, PCIe _ REFC L K _ S4 and PCIe _ REFC L K _ S5 of the PCIe Switch respectively provide clock to 32E1.S SSD L K Generator by C L K BUFFER which is divided by 4 to obtain Microsmi Z3025L DF1Q 5801Q P which is 1, C L K4028 and MICROSOF 598 which is 599 and HIP 599 which is 599.
The PCIe Switch0 Stack0 and Stack1 share 32PCIe lanes uplink connection mainboard CPU0, the PCIeSwitch0 Stack2, Stack3, Stack4 and SATACK5 share E1.S SSD0-15, the PCIe Switch1 Stack0 and Stack1 share 32PCIe lanes uplink connection mainboard CPU1, the PCIe Switch1 Stack2, Stack3, Stack4 and SATACK5 share E1.S SSD16-31, the backplane connects the mainboard through Slimline x8 connector, the Slimline x8 connector adopts P-U10-B074-250T of AMPHENO L, the number is 8, the backplane connects the E1.SSSD through hard disk connector, the hard disk connector adopts ME2005602311011 of HENO L, the number is 32, the structural design can support the SSD 32 in the size of the E1U server, and the SSD 32 can support the SSD 32 in the ESS server
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A hard disk backplane, comprising:
the hard disk comprises a first hard disk connector and a second hard disk connector, wherein the first hard disk connector is connected with a first CPU, the second hard disk connector is connected with a second CPU, and the first hard disk connector is in communication connection with the second hard disk connector.
2. The hard disk backplane of claim 1, wherein the first hard disk connector and the second hard disk connector establish a connection link over PCIe 4.0.
3. The hard disk backplane of claim 1, wherein the first hard disk connector, the second hard disk connector, the first CPU, and the second CPU all use a same source clock.
4. The hard disk backplane of claim 1, wherein the first hard disk connector connects fifteen hard disks; and the second hard disk connector is connected with fifteen hard disks.
5. The hard disk backplane of claim 4, wherein the first hard disk connector and the second hard disk connector are both provided with a same source clock as the hard disk.
6. The hard disk backplane of claim 4, wherein the hard disk is an E1.S SSD.
7. The hard disk backplane according to claim 1, wherein the first CPU and the second CPU are connected by a UPI bus.
8. The hard disk backplane of claim 1, wherein the first hard disk connector and the second hard disk connector each have 100 PCIe links.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010154814.6A CN111474990A (en) | 2020-03-08 | 2020-03-08 | Hard disk backboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010154814.6A CN111474990A (en) | 2020-03-08 | 2020-03-08 | Hard disk backboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111474990A true CN111474990A (en) | 2020-07-31 |
Family
ID=71747205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010154814.6A Pending CN111474990A (en) | 2020-03-08 | 2020-03-08 | Hard disk backboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111474990A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113190084A (en) * | 2021-03-25 | 2021-07-30 | 山东英信计算机技术有限公司 | Hard disk backboard connecting method and device supporting hard disks with various bit widths |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016149312A (en) * | 2015-02-13 | 2016-08-18 | ソニー株式会社 | Secondary battery, battery pack, motor vehicle, power storage system, power tool, and electronic apparatus |
| CN106569969A (en) * | 2016-10-19 | 2017-04-19 | 曙光信息产业(北京)有限公司 | Server |
| CN206684730U (en) * | 2017-04-20 | 2017-11-28 | 郑州云海信息技术有限公司 | The system that a kind of PCIE of storage server extends direct-connected hard disk |
| CN108763126A (en) * | 2018-05-29 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting EDSFF-1C standards |
| US20190272008A1 (en) * | 2018-03-01 | 2019-09-05 | HoneycombData Inc. | SSD Module For Mounting In A HDD Bay Of A Rack Server |
-
2020
- 2020-03-08 CN CN202010154814.6A patent/CN111474990A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016149312A (en) * | 2015-02-13 | 2016-08-18 | ソニー株式会社 | Secondary battery, battery pack, motor vehicle, power storage system, power tool, and electronic apparatus |
| CN106569969A (en) * | 2016-10-19 | 2017-04-19 | 曙光信息产业(北京)有限公司 | Server |
| CN206684730U (en) * | 2017-04-20 | 2017-11-28 | 郑州云海信息技术有限公司 | The system that a kind of PCIE of storage server extends direct-connected hard disk |
| US20190272008A1 (en) * | 2018-03-01 | 2019-09-05 | HoneycombData Inc. | SSD Module For Mounting In A HDD Bay Of A Rack Server |
| CN108763126A (en) * | 2018-05-29 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting EDSFF-1C standards |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113190084A (en) * | 2021-03-25 | 2021-07-30 | 山东英信计算机技术有限公司 | Hard disk backboard connecting method and device supporting hard disks with various bit widths |
| CN113190084B (en) * | 2021-03-25 | 2023-08-08 | 山东英信计算机技术有限公司 | Method and device for connecting hard disk backboard supporting multiple-bit-width hard disks |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101907978B (en) | Mixed storage system and storage method based on solid state disk and magnetic hard disk | |
| Weddle et al. | PARAID: A gear-shifting power-aware RAID | |
| US8949555B1 (en) | Methods for sustained read and write performance with non-volatile memory | |
| JP3157935U (en) | server | |
| WO2014169015A1 (en) | Multiprocessor system with independent direct access to bulk solid state memory resources | |
| Kassa et al. | Improving performance of flash based {Key-Value} stores using storage class memory as a volatile memory extension | |
| CN101923380A (en) | Power supply design method of high-density system | |
| CN104298574A (en) | Data high-speed storage processing system | |
| CN111474990A (en) | Hard disk backboard | |
| CN103365601A (en) | Cloud storage system based on Loongson 3A processor | |
| Huang et al. | Exploiting redundancies and deferred writes to conserve energy in erasure-coded storage clusters | |
| CN210639614U (en) | NVME hard disk backboard system supporting various bandwidths | |
| Yang et al. | Performance evaluation on cxl-enabled hybrid memory pool | |
| CN206021132U (en) | A kind of desk computer based on 400 processor of Shen prestige SW | |
| CN218768130U (en) | Hard disk backboard supporting CXL (CXL) signals and PCIe (peripheral component interface express) signals and storage device | |
| CN102999106A (en) | Design method for realizing expansion of PCIE (Peripheral Component Interface Express) card or storage equipment on blade server | |
| Volos et al. | An effective dram cache architecture for scale-out servers | |
| US11422702B2 (en) | Managing utilization of storage class memory (SCM) resources | |
| CN213545260U (en) | Loongson-based 3B4000 four-way processor server | |
| CN213276491U (en) | High-density server based on quick modification of detachable middle back plate | |
| Shirota et al. | Powering-off DRAM with aggressive page-out to storage-class memory in low power virtual memory system | |
| CN104011693A (en) | Method and apparatus for setting I/O bandwidth-based processor frequency floor | |
| CN212647385U (en) | AI server of 2U support nine two wide GPU cards | |
| CN201699750U (en) | Colony memory | |
| CN209895266U (en) | General SR node calculation storage architecture for server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200731 |