CN111464412B - LIN receiving and transmitting control circuit and dormancy and awakening control method thereof - Google Patents

LIN receiving and transmitting control circuit and dormancy and awakening control method thereof Download PDF

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Publication number
CN111464412B
CN111464412B CN202010246644.4A CN202010246644A CN111464412B CN 111464412 B CN111464412 B CN 111464412B CN 202010246644 A CN202010246644 A CN 202010246644A CN 111464412 B CN111464412 B CN 111464412B
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circuit
resistor
diode
power supply
lin
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CN111464412A (en
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彭金城
文雯
常云萍
杨显国
蔡丹丹
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Dongfeng Motor Corp
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Dongfeng Motor Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • H04L12/40013Details regarding a bus controller
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/403Bus networks with centralised control, e.g. polling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L2012/40208Bus networks characterized by the use of a particular bus standard
    • H04L2012/40234Local Interconnect Network LIN
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L2012/40267Bus for use in transportation systems
    • H04L2012/40273Bus for use in transportation systems the transportation system being a vehicle

Abstract

The invention relates to the technical field of automobile electronic controllers, in particular to an LIN receiving and transmitting control circuit and a dormancy and awakening control method thereof. The system comprises a Micro Control Unit (MCU), an LIN transceiver circuit, an LIN signal detection circuit, a wake-up processing circuit, an external wake-up detection and power control circuit, a first power enable circuit, a first power voltage stabilizing circuit and a second power enable control circuit, wherein a WK signal output end of the wake-up processing circuit is connected with the LIN transceiver circuit, an RXD _ MCU signal output end of the LIN transceiver circuit is connected with the MCU, an LIN signal output end of the LIN transceiver circuit is connected with the LIN signal detection circuit, a first enable signal output end of the LIN signal detection circuit is connected with the second power enable control circuit, and a second enable signal output end of the external wake-up detection and power control circuit is connected with the second power enable control circuit. The phenomenon that the LIN receiving and transmitting circuit is interfered by the static electricity of-25 kV to halt at the temperature of-25 ℃ below zero is avoided. Meanwhile, the ultra-low quiescent current requirement of the automobile electronic controller is realized.

Description

LIN receiving and transmitting control circuit and dormancy and awakening control method thereof
Technical Field
The invention relates to the technical field of automobile electronic controllers, in particular to an LIN receiving and transmitting control circuit and a dormancy and awakening control method thereof.
Background
LIN is a low-cost serial communication network, and is widely applied to automobiles to realize control of a distributed automobile electronic system. The cost of the LIN bus is much lower than that of the CAN bus, so the LIN bus is widely applied to systems without high requirements on network bandwidth, performance or fault-tolerant function, for example, an automobile skylight control system, an automobile door and window control system and an engine anti-theft locking system all adopt LIN communication.
There are many known brands of LIN transceiver chips (ICs) on the market today, which are nearly identical in function, performance and packaging, and can be interchanged with one another, and the recommended application circuitry of each chip is similar. The automobile BCM controller designed according to the chip recommendation application circuit can meet the national standard in performance, but the automobile provided with the BCM has a fault that the automobile cannot be started with an excessively small probability in the northeast winter, and the fault is found to be caused by the crash of an IMMO LIN transceiver chip of the BCM through analysis. Further experimental verification shows that the LIN transceiver circuit is easy to be halted by electrostatic interference of-25 kV at-25 ℃ or below, and the static electricity enters the IC through an INH pin and causes the internal circuit of the IC to latch. To solve this problem, the LIN transceiver circuit needs to be reconfigured.
Disclosure of Invention
The invention aims to provide an LIN transceiving control circuit which has no low-temperature crash fault and can realize multi-mode switching and a dormancy and awakening control method thereof aiming at the defects of the prior art.
The technical scheme of the invention is that the LIN receiving and transmitting control circuit comprises the following steps: the system comprises a MCU, a LIN transceiver circuit, a LIN signal detection circuit, a wake-up processing circuit, an external wake-up detection and power control circuit, a first power enable circuit, a first power voltage stabilizing circuit and a second power enable control circuit, wherein the wake-up processing circuit and the external wake-up detection and power control circuit are respectively provided with a Wk _ Exernal signal input end, a WK signal output end of the wake-up processing circuit is connected with a WK signal input end of the LIN transceiver circuit, an RXD _ MCU signal output end of the LIN transceiver circuit is connected with an RXD _ MCU signal input end of the MCU, an EN _ MCU signal output end and a TXD _ MCU signal output end of the MCU are respectively connected with an EN _ MCU signal input end and a TXD _ MCU signal input end of the LIN transceiver circuit, an LIN signal output end of the LIN transceiver circuit is connected with an LIN signal input end of the LIN signal detection circuit, and a first enable signal output end of the second power enable control circuit is connected with a first enable signal input end of the second power enable control circuit, the power EN-1 signal output part and the power DIS signal output part of the MCU are respectively connected with the power EN-1 signal input part and the power DIS signal input part of the external wake-up detection and power control circuit, the second enabling signal output part of the external wake-up detection and power control circuit is connected with the second enabling signal input part of the second power enabling control circuit, the controllable power signal output part of the second power enabling control circuit is connected with the controllable power signal input part of the first power enabling circuit, the first power enabling circuit further has a power EN _2 signal input part, the INH signal output part of the first power enabling circuit is connected with the INH signal input part of the first power voltage stabilizing circuit.
Preferably, the wake-up processing circuit includes a resistor R1, a resistor R2, a resistor R4, a diode D1, a diode D2, a capacitor C3, a capacitor C4, and a transistor Q1, the Wk _ Exernal signal input terminal is serially connected to the base of the transistor Q1 through the resistor R1 and the diode D1, the resistor R2, the diode D2, and the capacitor C3 are connected in parallel between the base of the transistor Q1 and ground, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to the Wk signal input terminal of the wake-up processing circuit through the resistor R4, one end of the capacitor C4 is connected to the Wk signal input terminal of the wake-up processing circuit, the other end of the capacitor is grounded, the anode of the diode D1 is connected to the base of the transistor Q1, and the cathode of the diode D2 is connected to the base of the transistor Q1.
Preferably, the LIN transceiver circuit includes a control module U1, a resistor R3, resistors R8 to R12, a capacitor C1, and a capacitor C2, the capacitor C1 is connected between a first power supply and ground, the capacitor C2 is connected between a second power supply and ground, the first power supply is connected with a TXD pin of a control module U1 through a resistor R8, the first power supply is connected with an RXD pin of the control module U1 through a resistor R9, an RXD _ MCU signal output terminal, an EN _ MCU signal input terminal, and a TXD _ MCU signal input terminal of the LIN transceiver circuit are connected with RXD, EN, and TXD pins of the control module U1 through a resistor R10, a resistor R11, and a resistor R12, and a BUS pin of the control module U1 is a LIN signal output terminal.
Preferably, the local protection circuit further comprises an LIN protection circuit, wherein the LIN protection circuit is provided with an LIN _ BUS signal output end, an LIN signal input end of the LIN protection circuit is connected with an LIN signal output end of the LIN transceiver circuit, and a controllable power supply signal input end of the LIN protection circuit is connected with a controllable power supply signal output end of the second power supply enabling control circuit;
the LIN protection circuit comprises an inductor L1, capacitors C5-C8, resistors R5-R7, a diode D3 and a diode D4, wherein one end of the inductor L1 is connected with the capacitors C5 and C6 which are arranged in parallel, the other end of the inductor L1 is connected with the capacitor C7, the capacitor C8 and the diode D4 which are arranged in parallel, anodes of the capacitors C5-C8 and the diode D4 are grounded, one end of the inductor L1 connected with the capacitor C6 is an LIN signal input end, one end of the inductor L7 connected with the capacitor C7 is an LIN _ BUS signal output end, a resistor string and the diode D3 are connected between the inductor L1 and the LIN _ BUS signal output end in series, the anode of the diode D3 is connected with a second power supply, and the resistor string is resistors R5-R7 which are arranged in parallel.
Preferably, the INH pin of the LIN transceiver circuit is suspended and is far away from the LIN pin and the LIN _ BUS pin.
Preferably, the LIN signal detection circuit includes a capacitor C18, a capacitor C19, a diode D10, a diode D14, a diode D16, a resistor R20, a resistor R23, a resistor R29, a resistor R32, and a transistor Q3, wherein an LIN signal input end of the LIN signal detection circuit is connected to a base of the transistor Q3 through the capacitor C19, the resistor R29, the diode D14, and the resistor R20, which are sequentially connected, an emitter of the transistor Q3 is grounded, a collector of the transistor Q3 is a first enable signal output end, the resistor R23 and the diode D10 are connected in parallel to a base of the transistor Q3, anodes of the resistor R23 and the diode D10 are grounded, one end of the capacitor C18 is connected between a cathode of the diode D14 and the resistor R20, the other end is grounded, a resistor R32 and a diode D16 which are connected in series are connected between the resistor R29 and the capacitor C19, and an anode of the diode D16 is grounded.
Preferably, the external wake-up detection and power control circuit includes a resistor R21, a resistor R22, resistors R24 to R28, resistors R30 to R31, resistors R33 to R33, a capacitor C33, capacitors C33 to C33, diodes D33 to D33, diodes D33, and transistors Q33 to Q33, wherein a Wk _ Exernal signal input terminal of the external wake-up detection and power control circuit is connected to a base of the transistor Q33 through the resistor R33, the diode D33 and the diode Q33 which are sequentially connected in series, an anode of the diode D33 is connected to an anode of the diode D33, a poen-1 signal input terminal of the external wake-up detection and power control circuit is connected to a base of the transistor Q33 through the resistor R33, the diode D33 and a power control signal input terminal of the external wake-up detection and power control circuit which are sequentially connected in series, and the diode D33 is connected to the diode D33 through the resistor R33 and the power control circuit which are sequentially connected in series A diode D15 and a resistor R31 are connected with the base of a triode Q5, the collector of the triode Q5 is connected with the base of a triode Q4 through a resistor R27 and a diode D12 which are sequentially connected in series, the anode of the diode D4 is connected with a resistor R4, the cathode of the diode D4 is connected with the base of the triode Q4, the base of the triode Q4 is connected with a capacitor C4, a resistor R4 and a diode D4 which are arranged in parallel, the anodes of the capacitor C4, the resistor R4 and the diode D4 are grounded, the collector of the triode Q4 is connected with a first power supply through the resistor R4, a capacitor C4 is connected between the collector and the emitter of the triode Q4, a resistor R4 is connected between the base and the emitter of the triode Q4, the cathode of the diode D4 is grounded through the capacitor C4, and the anode of the diode D4 is grounded through the resistor R4, the emitter of the transistor Q5 is grounded, the emitter of the transistor Q4 is grounded, and the collector of the transistor Q4 is a second enable signal output terminal.
Preferably, the second power enable control circuit includes resistors R17 to R19, a capacitor C10, a diode D7, and a MOS transistor Q2, a first enable signal input end of the second power enable control circuit is connected to the gate of the MOS transistor Q2 through a resistor R18, a second enable signal input end of the second power enable control circuit is connected to the gate of the MOS transistor Q2 through a resistor R19, the diode D7 and the resistor R17 are both connected between the source and the gate of the MOS transistor Q2, the diode D7 is connected in parallel to the resistor R17, the cathode of the diode D7 is connected to the source of the MOS transistor Q2, the source of the MOS transistor Q2 is connected to the second power supply, the source of the MOS transistor Q2 is grounded through a capacitor C10, and the drain of the MOS transistor Q2 is a controllable power signal output end;
when the first enable signal or the second enable signal is at a low level, the controllable power supply signal output end outputs a second power supply;
and when the first enable signal and the second enable signal are both open circuits, the controllable power supply signal output end outputs a 0V power supply.
Preferably, the first power enable circuit includes resistors R13 to R16, a capacitor C9, a capacitor C11, a diode D5, and a diode D6, a controllable power signal input end of the first power enable circuit is connected to one end of a resistor R15, the other end of the resistor R15 is connected to an anode of the diode D5, one end of a capacitor C11, and one end of the resistor R16, the other ends of the capacitor C11 and the resistor R16 are both grounded, a PowerEN _2 signal input end of the first power enable circuit is connected to one end of the resistor R14, the other end of the resistor R14 is connected to an anode of the diode D6, one end of the capacitor C19, and one end of the resistor R13, the other ends of the capacitor C19 and the resistor R13 are both grounded, and a cathode of the diode D5 and a cathode of the diode D6 are both connected to an INH signal output end of the first power enable circuit.
Preferably, the power supply protection circuit further comprises a power supply filter circuit and a power supply protection circuit, wherein a power supply signal output end of the power supply protection circuit is connected with a power supply signal input end of the first power supply voltage stabilizing circuit, a power supply signal output end of the first power supply voltage stabilizing circuit is connected with a power supply signal input end of the power supply filter circuit, and the power supply filter circuit outputs the first power supply.
The technical scheme of the invention is that the sleep and wake-up control method of the LIN receiving and transmitting control circuit comprises the following steps:
the LIN transceiving control circuit comprises a working mode, a shallow sleep mode and a deep sleep mode, wherein a first power supply and a second power supply power under the working mode, the MCU and other circuits work normally, the first power supply and the second power supply power under the shallow sleep mode, the MCU and other circuits are both in sleep, the first power supply and the second power supply are powered off under the deep sleep mode, and the MCU and other circuits are both in sleep;
in the deep sleep mode, if a wake-up signal is received, the MCU executes a corresponding application program according to the wake-up event, and judges whether a sleep condition is met after the execution is finished;
if the sleep condition is met, whether the deep sleep condition is met is further judged, if yes, the deep sleep mode is entered, and if not, the shallow sleep mode is entered.
The invention has the beneficial effects that: an INH pin is not used, so that the phenomenon that the LIN receiving and transmitting circuit is halted by electrostatic interference of-25 kV at the temperature below-25 ℃ is avoided. Meanwhile, in order to avoid consuming the quiescent current of the automobile when the LIN has a short-circuit fault, the INH function is reconstructed, and the function is expanded to realize unique sleep wake-up control, the quiescent current of the controller applying the circuit can reach below 50uA when the controller is normal or the LIN has a short-circuit fault, and the ultra-low quiescent current requirement of the automobile electronic controller is realized. Meanwhile, the circuit can be flexibly expanded and cut according to design requirements, for example, the loads of two power supplies can be expanded, or a 'PowerEN _ 2' control circuit can be cut.
Drawings
Fig. 1 is a schematic diagram of module connection of a LIN transceiver circuit of the present invention;
FIG. 2 is a schematic diagram of a power protection circuit according to the present invention;
FIG. 3 is a schematic diagram of an MCU pin according to the present invention;
fig. 4 is a schematic diagram of an LIN transceiver circuit, a wake-up processing circuit, and an LIN protection circuit according to the present invention;
FIG. 5 is a schematic diagram of a +5V voltage stabilizing circuit, a power filter circuit, a +5V enable circuit, a LIN signal detection circuit, a +12V enable control circuit, an external wake-up detection and power control circuit according to the present invention;
fig. 6 is a timing logic diagram of LIN signal detection in accordance with the present invention;
FIG. 7 is a logic diagram of sleep and wake-up control according to the present invention;
in the figure: the circuit comprises a 1-power supply protection circuit, a 2- +5V voltage stabilizing circuit, a 3-power supply filter circuit, a 4- +5V enable circuit, a 5-MCU, a 6-LIN transceiver circuit, a 7-wake-up processing circuit, an 8-LIN protection circuit, a 9-LIN signal detection circuit, a 10-external wake-up detection and power supply control circuit and an 11- +12V enable control circuit.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
As shown in fig. 1, the LIN transceiver control circuit includes 11 modules, which are a power protection circuit 1, a +5V voltage stabilizing circuit 2, a power filter circuit 3, a +5V enable circuit 4, an MCU5, a LIN transceiver circuit 6, a wake-up processing circuit 7, a LIN protection circuit 8, a LIN signal detection circuit 9, an external wake-up detection and power control circuit 10, and a +12V enable control circuit 11.
In this embodiment, the first power enable circuit, i.e., the +5V enable circuit 4, the first power regulator circuit, i.e., the +5V regulator circuit 2, and the second power enable control circuit, i.e., the +12V enable control circuit 11.
In this embodiment, the first power supply is a +5V power supply, and the second power supply is a +12V power supply. The first enable signal is a +12V _ EN _1 signal, the second enable signal is a +12V _ EN _2 signal, and the controllable power supply signal is a +12V _ SW signal. It can output 0V power or +12V power.
Wherein, the wake-up processing circuit 7 and the external wake-up detection and power control circuit 10 both have Wk _ Exernal signal input ends, the WK signal output end of the wake-up processing circuit 7 is connected with the WK signal input end of the LIN transceiver circuit 6, the RXD _ MCU signal output end of the LIN transceiver circuit 6 is connected with the RXD _ MCU signal input end of the MCU5, the EN _ MCU signal output end and the TXD _ MCU signal output end of the MCU5 are respectively connected with the EN _ MCU signal input end and the TXD _ MCU signal input end of the LIN transceiver circuit 6, the LIN signal output end of the LIN transceiver circuit 6 is connected with the LIN signal input end of the LIN signal detection circuit 9, the +12V _ EN _1 signal output end of the LIN signal detection circuit 9 is connected with the +12V _ EN _1 signal input end of the +12V enable control circuit 11, the PowerEN-1 signal output end and the PowerEN _1 signal output end of the MCU5 are respectively connected with the PowerEN-1 signal input end, the PowerEN-1 signal input end and the PowerDIS signal output end of the external wake-1 signal input end of the external wake-up detection and power control circuit 10, The PowerDIS signal input end is connected, the +12V _ EN _2 signal output end of the external wake-up detection and power supply control circuit 10 is connected with the +12V _ EN _2 signal input end of the +12V enable control circuit 11, the +12V _ SW signal output end of the +12V enable control circuit 11 is connected with the +12V _ SW signal input end of the +5V enable circuit 4, the +5V enable circuit 4 is also provided with a PowerEN _2 signal input end, and the INH signal output end of the +5V enable circuit 4 is connected with the INH signal input end of the +5 voltage stabilizing circuit V2. The LIN protection circuit 8 is provided with an LIN _ BUS signal output end, an LIN signal input end of the LIN protection circuit 8 is connected with an LIN signal output end of the LIN transceiver circuit 6, and a +12V _ SW signal input end of the LIN protection circuit 8 is connected with a +12V _ SW signal output end of the +12V enable control circuit 11; the power supply signal output end of the power supply protection circuit 1 is connected with the power supply signal input end of the +5V voltage stabilizing circuit 2, the power supply signal output end of the +5V voltage stabilizing circuit 2 is connected with the power supply signal input end of the power supply filter circuit 3, and the power supply filter circuit 3 outputs a +5V power supply.
As shown in fig. 2, the power protection circuit 1 performs protection and filtering processing on input power supplies ("Battery _ 12V" and "GND"), outputs a "+ 12V" power supply, and includes reverse connection protection, pulse protection, ESD protection, and high and low frequency filter circuits, which mainly include a diode, a TVS, and a capacitor. The reverse connection protection is not lower than 24V, the pulse protection meets the ISO7637 standard, the ESD protection reaches the +/-25 KV grade of the GB/T19951 standard, and the filtering frequency range is 100 Hz-16 MHz. The power protection circuit 1 comprises a capacitor C22, a capacitor C23, a diode D17 and a diode D18, one end of the capacitor C22 is connected with a power supply end of a storage battery, the other end of the capacitor C22 is grounded, the power supply end of the storage battery is connected with the anode of a diode D17, the cathode of a diode D17 is connected with a power signal output end of the power protection circuit, the cathode of a diode D17 is connected with the cathode of a diode D18 and one end of a capacitor C23, and the anode of a diode D18 and the other end of the capacitor C23 are grounded. In the embodiment, a capacitor (C22) of 100nF/100V is adopted for electrostatic prevention and surge prevention, a fast return diode (D17) of 2A/200V is adopted for an anti-reverse circuit, a TVS (D18) of 27V/5kW is adopted for electrostatic pulse protection, and a capacitor (C23) of 100uF/35V is adopted for energy storage filtering.
As shown in FIG. 5, the +5V voltage regulator circuit 2 is mainly composed of a low dropout linear regulator, and has an input voltage range ("+ 12V") of 5.5-18V, a transient peak input voltage of 45V, an output voltage ("Q") of 4.9-5.1V, an output current of not less than 400mA, and a ripple of less than 100 mV. The circuit has the functions of overheat protection, short-circuit protection and enable control, the static current is not more than 100uA when the circuit is enabled, and the static current is not more than 1uA when the circuit is not enabled, and the circuit meets the AEC-Q100 standard. The +5V may also power other circuits. The voltage stabilizing chip U2 in the embodiment adopts LDO (NCV4264-2C) with an enabling function, when INH (U2-2) is more than or equal to 2.8 and less than or equal to 45V, U2 is enabled, U2-5 outputs +5V, when INH (U2-2) is more than or equal to-42V and less than or equal to 1.8V, U2 is disabled, and U2-5 outputs 0V. C13(100nF/50V) was used as power input high frequency filtering. The +5V may also power other circuits.
The power supply filter circuit 3 mainly comprises a pi-type filter and energy storage circuit, wherein the input of the power supply filter circuit is Q, the output of the power supply filter circuit is +5V, the filter frequency range is 1 kHz-700 MHz, and the capacity of an energy storage capacitor is 44 uF. The module circuit occupies small PCB area and has low cost.
The +5V enable circuit 4 is mainly composed of a diode, a resistor, and a capacitor, and wired-or synthesizes 2 level or pulse signals ("+ 12V _ SW" and "PowerEN _ 2") inputted from the outside, and the synthesized output signal ("INH") is used as an enable signal of the +5V regulator circuit 2. Enabling the signal INH to be effective when the amplitude of the external input signal is 6-18V; when the amplitude of the input signal is 0-4V, the enable signal INH is invalid. The two paths of input signals do not influence each other. The +5V enabling circuit 4 comprises resistors R13-R16, a capacitor C9, a capacitor C11, a diode D5 and a diode D6, a +12V _ SW signal input end of the +5V enabling circuit 4 is connected with one end of a resistor R15, the other end of the resistor R15 is connected with an anode of the diode D5, one end of a capacitor C11 and one end of a resistor R16, the other ends of the capacitor C11 and the resistor R16 are grounded, a PowerEN _2 signal input end of the +5V enabling circuit 4 is connected with one end of a resistor R14, the other end of the resistor R14 is connected with an anode of the diode D6, one end of the capacitor C19 and one end of the resistor R13, the other ends of the capacitor C19 and the resistor R13 are grounded, and a cathode of the diode D5 and a cathode of the diode D6 are connected with an INH signal output end of the +5V enabling circuit 4. In this embodiment, C9(1nF) and C11(1nF) are high-frequency filter capacitors, R13(30kohm) and R14(30kohm) form a voltage divider circuit, and R15(30kohm) and R16(30kohm) form a voltage divider circuit. D5(BAV99) and D5(BAV99) are diodes that can prevent "+ 12V _ SW" and "PowerEN _ 2" from interacting.
As shown in fig. 3, the MCU is mainly composed of a single chip microcomputer used in an automobile, and has an LIN control function (or an analog LIN control function), a general input/output function, and the like. The power supply of the MCU is +5V, the LIN enabling signal is EN _ MCU, the LIN sending signal is TXD _ MCU, the LIN receiving signal is RXD _ MCU, the power supply enabling signal is PowerEN-1, and the power supply disabling signal is PowerDIS. When a falling edge or low level occurs for "RXD _ MCU", the MCU may wake up from a shallow sleep state ("+ 5V" power supply out +5V and MCU asleep). In this embodiment, the MCU has at least one LIN transceiver wake-up and at least 4I/O control functions, and may also include functions such as CAN, SPI, and PWM.
As shown in fig. 4, the LIN transceiver circuit 6 is mainly composed of a LIN transceiver, pins "RXD" and "TXD" of the LIN transceiver are respectively pulled up to "+ 5V", pins "RXD", "TXD" and "EN" of the LIN transceiver are respectively connected to corresponding pins of the MCU through resistors, VS is connected to a "+ 12V" power supply, WK "is a wake-up input of the LIN transceiver, and" INH "is floating and away from the" LIN "BUS, and BUS" is connected to the "LIN" BUS. When the 'WK' has a falling edge or a low level, the 'RXD _ MCU' has a falling edge or a low level, and the MCU can be awakened. The high-voltage power supply controller comprises a control module U1, a resistor R3, resistors R8-R12, a capacitor C1 and a capacitor C2, wherein the capacitor C1 is connected between a +5V power supply and the ground, the capacitor C2 is connected between a +12V power supply and the ground, the +5V power supply is connected with a TXD pin of the control module U1 through a resistor R8, the +5V power supply is connected with an RXD pin of the control module U1 through a resistor R9, an RXD _ MCU signal output end, an EN _ MCU signal input end and a TXD _ MCU signal input end of a transceiving circuit 6 are respectively connected with RXD, EN and TXD pins of a control module U1 through a resistor R10, a resistor R11 and a resistor R12, and the BUSLIN pin of the control module U1 is a signal output end. In this embodiment, U1 is a single-channel LIN transceiver integrated circuit with a supply voltage of +12V, and C2(100nF/50V) is a high-frequency filter capacitor of the U1 power supply. R10(1kohm) is a matching resistor between 'RXD' of the LIN transceiver and 'RXD _ MCU' of the single chip microcomputer, which can improve signal quality and reduce high-frequency interference, R11 is a matching resistor between 'EN' of the LIN transceiver and 'EN _ MCU' of the single chip microcomputer, which acts as R10, and R12 is a matching resistor between 'TXD' of the LIN transceiver and 'TXD _ MCU' of the single chip microcomputer, which acts as R10. R9 is a +5V pull-up resistor of RXD, which is one of the necessary conditions for waking up the singlechip by RXD, R8 is a +5V pull-up resistor of TXD, which is used for distinguishing BUS wake-up from WK wake-up, C1(100nF/50V) is a high-frequency filter capacitor of +5V, R3 is a +12V pull-up resistor of WK, which is one of the necessary conditions for waking up the singlechip by WK, and BUS (U1-6) is connected to LIN and INH of the module 8 and the module 9, and the INH is suspended and far away from LIN and LIN _ BUS.
The awakening processing circuit 7 is an inverted driving buffer circuit consisting of a triode, a voltage regulator tube, a diode, a capacitor and a resistor. The 'WK _ External' is an External awakening input signal, the high level is effective, the 'WK' is an output signal, the low level is effective, and the working temperature range of the circuit is-40-125 ℃. When the voltage range of the input signal (WK _ EXternal) is 6.8-50V, the voltage range of the output signal (WK) is 0.1-0.2V; when the voltage range of the input signal is 0-5.8V, the voltage of the output signal is 12V. When "WK _ EXternal" has a rising edge or a high level, "WK" has a falling edge or a low level, the MCU is woken up. The module comprises a reverse connection protection circuit, a pulse protection circuit, an ESD protection circuit and a high-frequency filter circuit, wherein the reverse connection protection circuit is not lower than 24V, the pulse protection circuit meets the ISO7637 standard, the ESD protection circuit reaches the +/-25 KV grade of GB/T19951, and the filter frequency range is 16 MHz-120 MHz. The conversion threshold is stable, and the circuit cost is low. The device comprises a resistor R1, a resistor R2, a resistor R4, a diode D1, a diode D2, a capacitor C3, a capacitor C4 and a triode Q1, wherein a Wk _ Exernal signal input end is serially connected with a diode D1 through the resistor R1 and the diode D1 and is arranged at the base of the triode Q1, the resistor R2, the diode D2 and the capacitor C3 are connected between the base of the triode Q1 and the ground in parallel, the emitter of the triode Q1 is grounded, the collector of the triode Q1 is connected with the WK signal input end of the wake-up processing circuit 7 through the resistor R4, one end of the capacitor C4 is connected with the WK signal input end of the wake-up processing circuit 7, the other end of the capacitor C6336 is grounded, the anode of the diode D1 is connected with the base of the triode Q1, and the cathode of the diode D2 is connected with the base of the triode Q1. In this embodiment, R1(10kohm) is a current-limiting resistor input to "WK _ External" and can protect a component connected in series with it, and D1(MMSZ5V6) is a series regulator input to "WK _ External", and its regulated voltage value is 5.6V, which plays a role in increasing the high level threshold of "WK _ External". R2(20kohm) is a base pull-down resistor of Q1(MMBT5550) and plays a role in ensuring the reliable cut-off of Q1, D2(BAV99) is a base emitter reverse protection diode of Q1, C3(10nF/50V) is a base high-frequency filter capacitor of Q1, Q1 is a high-voltage small-current triode meeting AEC-Q101 standard, the amplification factor is small, VBE (on) voltage is high at high temperature, C4(10nF/50V) is a high-frequency filter capacitor of WK output, and R4(100ohm) is a collector current-limiting resistor.
The LIN protection circuit 8 mainly comprises pi-type filtering, port protection and an LIN wire pull-up circuit, wherein an input signal of the LIN protection circuit is LIN, and an output signal of the LIN protection circuit is LIN _ BUS. The filtering frequency range is 30 MHz-500 MHz, the electrostatic protection level is +/-25 kV, the LIN wire is pulled up to a controllable power supply "+ 12V _ SW", when the working state LIN _ BUS is short-circuited, the MCU can detect and timely process the short circuit, when the dormant state LIN _ BUS is short-circuited, the "+ 12V _ SW" is 0V, the LIN _ BUS does not consume current to prevent the storage battery from being lack of power, the "LIN _ BUS" cannot supply power to the "+ 12V _ SW", and when the "LIN _ BUS" is short-circuited, the LIN pull-up circuit cannot be damaged. The high-voltage direct current power supply comprises an inductor L1, capacitors C5-C8, resistors R5-R7, a diode D3 and a diode D4, one end of the inductor L1 is connected with capacitors C5 and C6 which are arranged in parallel, the other end of the inductor L1 is connected with a capacitor C7, a capacitor C8 and a diode D4 which are arranged in parallel, anodes of the capacitors C5-C8 and the diode D4 are all grounded, one end of the inductor L1, which is connected with the capacitor C6, is a LIN signal input end, one end of the inductor C7 is a LIN _ BUS signal output end, a resistor string and a diode D3 are connected between the inductor L1 and the LIN _ BUS signal output end in series, the anode of the diode D3 is connected with a +12V power supply, and the resistor string is resistors R5-R7 which are arranged in parallel. In the embodiment, C5(1nF/50V), C6(220pF/50V), L1 (magnetic bead), C7(1nF/50V) and C8(220pF/50V) form a pi-type filter circuit, and the characteristic impedance of L1 in the range of 40MHz to 300MHz is more than 800 ohm. D4(PESDLIN) is a TVS suppressing electrostatic and pulse signals with a breakdown voltage of 27V. The 'LIN _ BUS' is pulled up to the '+ 12V _ SW' through R5(3kohm), R6(3kohm), R7(3kohm) and D3(BAS21-03W), R5, R6 and R7 are connected in parallel to improve reliability, and D3 can prevent the 'LIN _ BUS' from supplying power to the '+ 12V _ SW'. "+ 12V _ SW" is a controllable +12V supply, with "+ 12V _ SW" at 0V during deep sleep of the circuit and "+ 12V _ SW" at +12V during light sleep or normal operation of the circuit. Wherein, the INH pin of the LIN transceiver circuit 6 is suspended and is far away from the LIN pin and the LIN _ BUS pin.
As shown in fig. 5, the LIN signal detection circuit 9 is an edge detection circuit composed of a triode, a diode, a capacitor and a resistor, and realizes edge detection by using different charging and discharging loops of the capacitor and the dc blocking characteristic of the capacitor, wherein an input signal is "LIN", an output signal is "+ 12V _ EN _ 1", and the operating temperature range of the circuit is-40 to 125 ℃. When "LIN" is high or low, "+ 12V _ EN _ 1" output is open; when a single falling edge occurs to "LIN", the "+ 12V _ EN _ 1" output is open, and when a single rising edge occurs to "LIN", the "+ 12V _ EN _ 1" output is a low level pulse; when the continuous waveform (baud rate is 4800-19200) of "LIN" appears, "+ 12V _ EN _ 1" outputs low level, and the specific sequential logic is shown in fig. 6. When "+ 12V _ EN _ 1" or "+ 12V _ EN _ 2" is low, both "+ 12V _ EN _ 1" and "+ 12V _ EN _ 2" are 12V low; when "+ 12V _ EN _ 1" and "+ 12V _ EN _ 2" are both open circuits, "+ 12V _ EN _ 1" and "+ 12V _ EN _ 2" are both 12V high. The current drawn by the circuit from "LIN" is no more than 1.6mA, and the current injected into "LIN" is no more than 8 mA. The LIN signal input end of the LIN signal detection circuit 9 is connected with the base of a triode Q3 through a capacitor C3, a resistor R3, a diode D3 and a resistor R3 which are sequentially connected, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is a +12V _ EN _1 signal output end, the resistor R3 and the diode D3 are arranged at the base of the triode Q3 in parallel, the anodes of the resistor R3 and the diode D3 are grounded, one end of the capacitor C3 is connected between the cathode of the diode D3 and the resistor R3, the other end of the capacitor C3 is grounded, the resistor R3 and the capacitor C3 are connected with the diode D3 and the diode D3 which are arranged in series, and the anode of the diode D3 is grounded. In this embodiment, C19(100nF/50V), R29(10kohm), D14(BAV99) constitute a charging loop of C18(10nF), the base emitters of R20(47kohm), R23(24kohm), and Q3(MMBT5550) constitute a discharging loop of C18, and R32(2kohm) and D16(BAS21-03W) constitute a discharging loop of C19. Because the capacity of C18 is much smaller than C19, the C18 charge time constant is much smaller than the discharge time constant, and the C19 charge time constant is much larger than the discharge time constant. Therefore, when a single falling edge occurs to the "LIN", the voltage on the C18 is 0V, the Q3 is turned off, the "+ 12V _ EN _ 1" is open when the Q3 is turned off, the voltage charged by the C18 is enough to turn on the Q3 when a single rising edge or continuous square waves (baud rate is 4800-19200) occur to the "LIN", the Q3 can be kept on for 1.5ms after the rising edge disappears, and the "+ 12V _ EN _ 1" is low when the Q3 is turned on, and the specific waveform is as shown in fig. 6. Due to the dc blocking effect of C19, when "LIN" is at a long-term high level or a long-term low level, the voltage of C18 is 0V, and Q3 is turned off. R20 and R23 form a base emitter voltage division circuit of Q3, the anti-interference performance of the circuit is improved, R23 also plays a role in ensuring the reliable cut-off of Q3, D10 is a base reverse protection diode of Q3, Q3 is a high-voltage small-current triode meeting the AEC-Q101 standard, the amplification factor is small, and the VBE (on) voltage is high at high temperature. The charging current limiting resistor of C18 is R29, the current absorbed from LIN is not more than 1.6mA, the discharging current limiting resistor of C19 is R32, and the current poured into LIN is not more than 8 mA.
The external wake-up detection and power control circuit 10 is a special logic circuit consisting of a triode, a diode, a capacitor and a resistor, the working temperature range of the circuit is-40-125 ℃, input signals of the circuit are Wk _ external "," PowerEN-1 "and" PowerDIS ", and an output signal of the circuit is +12V _ EN _ 2". When the circuit is in a deep sleep state ("+ 5V" power output 0V), "+ 12V _ EN _ 2" output is open circuit when "Wk _ Exernal" is 0-6.2V (low level), "+ 12V _ EN _ 2" output is 0.1-0.2V (low level), "+ 5V" power output +5V when "Wk _ Exernal" is 7.6-50V (high level), "+ 12V _ EN _ 2" output is low level, and "+ 12V _ EN _ 2" output is maintained at low level even if "Wk _ Exernal" is changed to low level again; when the circuit is in a working state ("+ 5V" power output 5V) and "Wk _ Exernal" is at a low level, the MCU sets "PowerEN-1" and "PowerDIS" as a high level (3.8-5V), after a delay of about 150ms, the MCU sets "PowerEN-1" and "PowerDIS" as a low level (0-1.3V), after a delay of about 450ms, "+ 12V _ EN-2" changes from a low level to an open circuit state, "+ 12V _ SW" power output 0V, "+ 5V" power output 0V, the circuit enters a deep sleep state, and when "Wk _ Exernal" is at a high level, the circuit cannot enter the deep sleep state, the circuit outputs +12V _ SW +12V and + 5V; when the circuit is in a shallow sleep state ("+ 5V" power output +5V and MCU is asleep, "PowerEN-1" and "PowerDIS" are both 0V, and the MCU may be awakened when "Wk _ Exernal" is high. It includes resistance R, resistance R-R, capacitance C-C, diode D-D, diode D, triode Q-Q, Wk _ Exernal signal input end of the external wake-up detection and power supply control circuit 10 is connected with base electrode of triode Q through resistance R, diode D which are connected in series in turn, anode of diode D is connected with anode of diode D, PowerEN-1 signal input end of the external wake-up detection and power supply control circuit 10 is connected with base electrode of triode Q through resistance R, diode D which are connected in series in turn, anode of diode D is connected with resistance R, PowerDIS signal input end of the external wake-up detection and power supply control circuit 10 is connected with base electrode of triode Q through resistance R, diode D, resistance R which are connected in series in turn, the collector of the triode Q5 is connected with the base of the triode Q4 through a resistor R27 and a diode D12 which are sequentially connected in series, the anode of the diode D15 is connected with a resistor R30, the cathode of the diode D12 is connected with the base of the triode Q4, the base of the triode Q4 is connected with a capacitor C17 which is arranged in parallel, the high-voltage power supply comprises a resistor R22 and a diode D13, a capacitor C17, a resistor R22 and the anode of a diode D13 are grounded, the collector of a triode Q5 is connected with a +5V power supply through a resistor R28, a capacitor C20 is connected between the collector and the emitter of a triode Q5, a resistor R34 is connected between the base and the emitter of a triode Q5, a resistor R25 and the resistor R24 are grounded through a resistor R26, the cathode of the diode D15 is grounded through a capacitor C21, the anode of a diode D15 is grounded through a resistor R33, the emitter of a triode Q5 is grounded, the emitter of a triode Q4 is grounded, and the collector of a triode Q4 is a +12V _ EN _2 signal output end. In this embodiment, R21(10kohm), D8(MMSZ5V6), D9(BAV99), R22(20kohm) and Q4(MMBT5550) constitute an input detection circuit of "WK _ External", R21 is a current limiting resistor of "WK _ External" input and can protect a component connected in series therewith, D8 is a series regulator of "WK _ External" input, the voltage value of which is 5.6V and plays a role of increasing the high level threshold of "WK _ External", D9 can prevent current from flowing into "WK _ External", R22 is a base pull-down resistor of Q4 and plays a role of ensuring reliable cutoff of Q4, R21 and R22 constitute a voltage divider circuit and also play a role of increasing the high level threshold of "WK _ External". R25(4.7kohm), R26(4.7kohm), R24(10kohm), D11(BAV99), R22(20kohm) and Q4 form an input detection circuit of 'PowerEN _ 1', R25 and R26 form a voltage division circuit and play a role in improving the high level threshold of 'PowerEN _ 1', R24 is a current limiting resistor of 'PowerEN _ 1' input and can protect components connected in series with the current limiting resistor, D11 can prevent current from flowing into 'PowerEN _ 1', R22 is a base pull-down resistor of Q4 and plays a role in ensuring that Q1 is reliably cut off, and R24 and R22 form a voltage division circuit and also play a role in improving the high level of 'PowerEN _ 1'. R30(3.0kohm), R33(4.7kohm), D15(BAV99), C21(47uF/10V), R31(20kohm), R34(20kohm), Q5(MMBT5550), C20(10nF/50V), R28(10kohm), R27(10kohm), D12(BAV99), R22 and Q4 constitute an input detection processing circuit of "PowerDIS", R30 and R33 constitute voltage dividing circuits, which function to raise the high threshold of "PowerDIS", the charging circuit of C21 is R30, R33 and D15, the discharging circuit of C21 is the base emitters of R31, R34 and Q5, and the "+ 12V _ SW" and +5V "are turned off by the characteristics of short charging time and long discharging time of C21. C20 is a filter capacitor, R28 is a resistor which is pulled to +5V on the collector of Q5, R28, R27 and R22 form a voltage division circuit, the anti-interference capability of the circuit is improved, and D12 can prevent current from flowing into +5V or Q5. D13(BAV99) is a base emitter reverse protection diode of Q4, C17(10nF/50V) is a base high-frequency filter capacitor of Q4, Q4 and Q5 are high-voltage small-current triodes meeting the AEC-Q101 standard, the amplification factor is small, and the VBE (on) voltage is high at high temperature.
The +12V enable control circuit 11 is a high-side switching circuit composed of an MOSFET, a voltage stabilizing diode, a capacitor and a resistor, the operating temperature of the circuit ranges from-40 ℃ to 125 ℃, the input signals of the circuit are +12V _ EN _1 and +12V _ EN _2, and the output signal of the circuit is +12V _ SW. When "+ 12V _ EN _ 1" and "+ 12V _ EN _ 2" are both open circuits, "+ 12V _ SW" outputs 0V, and when "+ 12V _ EN _ 1" or "+ 12V _ EN _ 2" is 0.1 to 0.3V, "+ 12V _ SW" outputs +12V, the maximum output current thereof is 4A. "+ 12V _ SW" may also power other circuits. The power supply circuit comprises resistors R17-R19, a capacitor C10, a diode D7 and a MOS tube Q2, wherein a +12V _ EN _1 signal input end of a +12V enable control circuit 11 is connected with a grid electrode of an MOS tube Q2 through a resistor R18, a +12V _ EN _2 signal input end of the +12V enable control circuit 11 is connected with a grid electrode of the MOS tube Q2 through a resistor R19, the diode D7 and the resistor R17 are connected between a source electrode and a grid electrode of the MOS tube Q2, the diode D7 is connected with the resistor R17 in parallel, a cathode of the diode D7 is connected with a source electrode of the MOS tube Q2, a source electrode of the MOS tube Q2 is connected with a +12V power supply, a source electrode of the MOS tube Q2 is grounded through a capacitor C10, and a drain electrode of the MOS tube Q2 is a + 12V. In this embodiment, R18(6.8kohm) is a collector load resistor of Q3, R19(6.8kohm) is a collector load resistor of Q4, R18 and R17(5.1kohm) form a voltage divider circuit, R19 and R17 form a voltage divider circuit, so that the anti-interference capability of the circuit is improved, and R18 and R19 also play a role in isolating Q3 from Q4. Q2(SQ3419EV) is a P-channel MOSFET meeting AEC-Q101 standard, D7(FHZ06A15V) is a voltage regulator tube with breakdown voltage of 15V and is used for protecting GS of Q2, C10(100nF) is a high-frequency filter capacitor of +12V, and the +12V _ SW can also supply power to other circuits.
The LIN receiving and transmitting control circuit has three modes, which are respectively as follows: an operating mode, a light sleep mode, and a deep sleep mode.
In the working mode, a +5V power supply and a +12V power supply power, and the MCU and other circuits work normally;
in the shallow sleep mode, a +5V power supply and a +12V power supply power, and the MCU and other circuits are in sleep;
the +5V power supply and the +12V power supply are powered off in the deep sleep mode, and the MCU and other circuits are in sleep;
as shown in fig. 7, in the deep sleep state, after a valid wake-up event occurs, the "+ 12V" and "+ 5V" power supplies are enabled, the MCU processes the wake-up event, executes the application program, determines whether a sleep condition is satisfied, returns to execute the application program if not, continues to determine whether a deep sleep condition is satisfied if satisfied, enters a light sleep state if not, and disables the "+ 12V" and "+ 5V" power supplies and enters the deep sleep state if satisfied. In a light sleep state, after an effective wake-up event occurs, the MCU processes the wake-up event, and the subsequent flow is the same as the deep sleep wake-up.
Under the control of MCU software in a normal working state, the system can enter a shallow sleep state and also can enter a deep sleep state. In a light sleep state, "+ 12V _ SW" outputs +12V, "+ 5V" outputs +5V, the MCU and Other circuits enter the sleep state, the static current of the circuits is less than or equal to 1mA, the MCU can be awakened by a LIN _ BUS, Wk _ Exernal or Other MCU awakening sources ("Other ports"), and the circuit enters the normal working state after being awakened. In the deep sleep state, "+ 12V _ SW" and "+ 5V" both output 0V, the MCU and other circuits are powered off, the static current of the circuits is less than or equal to 50uA, the "+ 12V _ SW" and "+ 5V" can be awakened by "LIN _ BUS", "Wk _ Exernal" or other external awakening sources ("PowerEN _ 2"), after awakening, "+ 12V _ SW" and "+ 5V" output +12V and +5V respectively, the MCU is restarted, and the circuits enter the normal working state. "+ 12V _ SW" and "+ 5V" may also power other circuits.
The "LIN _ BUS" is connected to "+ 12V _ SW" through a resistor and an anti-reverse diode. In normal operation and light sleep mode, "+ 12V _ SW" provides pull-up current to "LIN _ BUS," which short can be detected by or wake up the MCU. In the deep sleep mode, "+ 12V _ SW" no longer provides pull-up current to "LIN _ BUS" and does not draw current from "LIN _ BUS", even if "LIN _ BUS" is shorted, the quiescent current of the circuit is guaranteed to be no more than 50 uA. "LIN _ BUS" cannot supply "+ 12V _ SW".
Details not described in this specification are within the skill of the art that are well known to those skilled in the art.

Claims (11)

1. A LIN transceiver control circuit, characterized by: the multifunctional low-voltage line-current wake-up circuit comprises an MCU (5), an LIN transceiver circuit (6), an LIN signal detection circuit (9), a wake-up processing circuit (7), an external wake-up detection and power control circuit (10), a first power enable circuit, a first power voltage stabilizing circuit and a second power enable control circuit, wherein both the wake-up processing circuit (7) and the external wake-up detection and power control circuit (10) are provided with Wk _ Exernal signal input ends, the WK signal output end of the wake-up processing circuit (7) is connected with the WK signal input end of the LIN transceiver circuit (6), the RXD _ MCU signal output end of the LIN transceiver circuit (6) is connected with the RXD _ MCU signal input end of the MCU (5), the EN _ MCU signal output end and the TXD _ MCU signal output end of the MCU (5) are respectively connected with the EN _ MCU signal input end and the TXD _ MCU signal input end of the LIN transceiver circuit (6), and the LIN signal output end of the LIN transceiver circuit (6) is connected with the signal input end of the LIN signal detection circuit (9) A first enable signal output end of the LIN signal detection circuit (9) is connected with a first enable signal input end of the second power supply enable control circuit, the PowerEN-1 signal output end and the PowerDIS signal output end of the MCU (5) are respectively connected with the PowerEN-1 signal input end and the PowerDIS signal input end of the external awakening detection and power control circuit (10), a second enable signal output end of the external wake-up detection and power control circuit (10) is connected with a second enable signal input end of a second power enable control circuit, the controllable power supply signal output end of the second power supply enabling control circuit is connected with the controllable power supply signal input end of the first power supply enabling circuit, the first power supply enabling circuit is further provided with a PowerEN _2 signal input end, and an INH signal output end of the first power supply enabling circuit is connected with an INH signal input end of the first power supply voltage stabilizing circuit.
2. The LIN transceiver control circuit of claim 1, wherein: the wake-up processing circuit (7) comprises a resistor R1, a resistor R2, a resistor R4, a diode D1, a diode D2, a capacitor C3, a capacitor C4 and a triode Q1, wherein the Wk _ Exernal signal input end is serially connected with a base of the triode Q1 through the resistor R1 and a diode D1, the resistor R2, the diode D2 and the capacitor C3 are connected between the base of the triode Q1 and the ground in parallel, an emitter of the triode Q1 is grounded, a collector of the triode Q1 is connected with the WK signal input end of the wake-up processing circuit (7) through the resistor R4, one end of the capacitor C4 is connected with the WK signal input end of the wake-up processing circuit (7), the other end of the capacitor C4 is grounded, an anode of the diode D1 is connected with the base of the triode Q1, and a cathode of the diode D2 is connected with the base of the triode Q1.
3. The LIN transceiver control circuit of claim 1, wherein: the LIN transceiver circuit (6) comprises a control module U1, a resistor R3, resistors R8-R12, a capacitor C1 and a capacitor C2, wherein the capacitor C1 is connected between a first power supply and the ground, the capacitor C2 is connected between a second power supply and the ground, the first power supply is connected with a TXD pin of a control module U1 through a resistor R8, the first power supply is connected with an RXD pin of the control module U1 through a resistor R9, an RXD _ MCU signal output end, an EN _ MCU signal input end and a TXD _ MCU signal input end of the LIN transceiver circuit (6) are respectively connected with RXD, EN and TXD pins of the control module U1 through a resistor R10, a resistor R11 and a resistor R12, and a BUS pin of the control module U1 is an LIN signal output end.
4. The LIN transceiver control circuit of claim 1, wherein: the LIN protection circuit (8) is provided with an LIN _ BUS signal output end, an LIN signal input end of the LIN protection circuit (8) is connected with an LIN signal output end of the LIN transceiver circuit (6), and a controllable power supply signal input end of the LIN protection circuit (8) is connected with a controllable power supply signal output end of the second power supply enabling control circuit;
the LIN protection circuit (8) comprises an inductor L1, capacitors C5-C8, resistors R5-R7, a diode D3 and a diode D4, one end of the inductor L1 is connected with the capacitors C5 and C6 which are arranged in parallel, the other end of the inductor L1 is connected with the capacitors C7, the capacitors C8 and the diode D4 which are arranged in parallel, anodes of the capacitors C5-C8 and the diode D4 are grounded, one end of the inductor L1, which is connected with the capacitor C6, is an LIN signal input end, one end of the inductor L7 is an LIN _ BUS signal output end, a resistor string and the diode D3 are connected between the inductor L1 and the LIN _ BUS signal output end in series, the anode of the diode D3 is connected with a second power supply, and the resistor string is connected with the resistors R5-R7 which are arranged in parallel.
5. The LIN transceiver control circuit of claim 4, wherein: an INH pin of the LIN transceiver circuit (6) is suspended and is far away from the LIN pin and the LIN _ BUS pin.
6. The LIN transceiver control circuit of claim 1, wherein: the LIN signal detection circuit (9) comprises a capacitor C18, a capacitor C19, a diode D10, a diode D14, a diode D16, a resistor R20, a resistor R23, a resistor R29, a resistor R32 and a triode Q3, wherein an LIN signal input end of the LIN signal detection circuit (9) is connected with a base of the triode Q3 through the capacitor C3, the resistor R3, the diode D3 and the resistor R3 which are sequentially connected, an emitter of the triode Q3 is grounded, a collector of the triode Q3 is a first enabling signal output end, the resistor R3 and the diode D3 are arranged at the base of the triode Q3 in parallel, anodes of the resistor R3 and the diode D3 are grounded, one end of the capacitor C3 is connected between a cathode of the diode D3 and the resistor R3, the other end of the capacitor C3 is grounded, the resistor R3 and the anode of the diode D3 are connected in series, and the anode of the diode D3 is connected in series.
7. The LIN transceiver control circuit of claim 1, wherein: the external wake-up detection and power control circuit (10) comprises a resistor R21, a resistor R22, resistors R24-R28, resistors R30-R31, resistors R33-R33, a capacitor C33, capacitors C33-C33, diodes D33-D33, a diode D33 and triodes Q33-Q33, wherein a Wk _ Exernal signal input end of the external wake-up detection and power control circuit (10) is connected with a base of the triode Q33 through the resistor R33, the diode D33 and the diode D33 which are sequentially connected in series, an anode of the diode D33 is connected with an anode of the diode D33, a PowerEN-1 signal input end of the external wake-up detection and power control circuit (10) is connected with a base of the triode Q33 through the resistor R33, the diode R33 and the PowerEN-1 signal input end of the external wake-up detection and power control circuit (10) which are sequentially connected in series, and the external wake-up detection and power control circuit (10) are connected with the DISR 33) through the resistor R33, the diode D33 and the diode D33 which are sequentially connected in series, A diode D15 and a resistor R31 are connected with the base of a triode Q5, the collector of the triode Q5 is connected with the base of a triode Q4 through a resistor R27 and a diode D12 which are sequentially connected in series, the anode of the diode D4 is connected with a resistor R4, the cathode of the diode D4 is connected with the base of the triode Q4, the base of the triode Q4 is connected with a capacitor C4, a resistor R4 and a diode D4 which are arranged in parallel, the anodes of the capacitor C4, the resistor R4 and the diode D4 are grounded, the collector of the triode Q4 is connected with a first power supply through the resistor R4, a capacitor C4 is connected between the collector and the emitter of the triode Q4, a resistor R4 is connected between the base and the emitter of the triode Q4, the cathode of the diode D4 is grounded through the capacitor C4, and the anode of the diode D4 is grounded through the resistor R4, the emitter of the transistor Q5 is grounded, the emitter of the transistor Q4 is grounded, and the collector of the transistor Q4 is a second enable signal output terminal.
8. The LIN transceiver control circuit of claim 1, wherein: the second power supply enabling control circuit comprises resistors R17-R19, a capacitor C10, a diode D7 and a MOS transistor Q2, wherein a first enabling signal input end of the second power supply enabling control circuit is connected with a grid electrode of a MOS transistor Q2 through a resistor R18, a second enabling signal input end of the second power supply enabling control circuit is connected with a grid electrode of a MOS transistor Q2 through a resistor R19, the diode D7 and the resistor R17 are both connected between a source electrode and a grid electrode of a MOS transistor Q2, the diode D7 is connected with the resistor R17 in parallel, a cathode of the diode D7 is connected with a source electrode of the MOS transistor Q2, a source electrode of the MOS transistor Q2 is connected with a second power supply, a source electrode of the MOS transistor Q2 is grounded through a capacitor C10, and a drain electrode of the MOS transistor Q2 is a controllable power supply signal output end;
when the first enable signal or the second enable signal is at a low level, the controllable power supply signal output end outputs a second power supply;
and when the first enable signal and the second enable signal are both open circuits, the controllable power supply signal output end outputs a 0V power supply.
9. The LIN transceiver control circuit of claim 1, wherein: the first power supply enabling circuit comprises resistors R13-R16, a capacitor C9, a capacitor C11, a diode D5 and a diode D6, a controllable power supply signal input end of the first power supply enabling circuit is connected with one end of a resistor R15, the other end of the resistor R15 is connected with an anode of the diode D5, one end of a capacitor C11 and one end of a resistor R16, the other ends of the capacitor C11 and the resistor R16 are grounded, a PowerEN _2 signal input end of the first power supply enabling circuit is connected with one end of a resistor R14, the other end of the resistor R14 is connected with an anode of the diode D6, one end of the capacitor C19 and one end of the resistor R13, the other ends of the capacitor C19 and the resistor R13 are grounded, and a cathode of the diode D5 and a cathode of the diode D6 are connected with an INH signal output end of the first power supply enabling circuit.
10. The LIN transceiver control circuit of claim 1, wherein: the power supply protection circuit comprises a power supply filter circuit (3) and a power supply protection circuit (1), wherein a power supply signal output end of the power supply protection circuit (1) is connected with a power supply signal input end of a first power supply voltage stabilizing circuit, a power supply signal output end of the first power supply voltage stabilizing circuit is connected with a power supply signal input end of the power supply filter circuit (3), and the power supply filter circuit (3) outputs a first power supply.
11. A sleep and wake-up control method of a LIN transceiver control circuit as claimed in claim 1, wherein: the LIN transceiving control circuit comprises a working mode, a shallow sleep mode and a deep sleep mode, wherein a first power supply and a second power supply power under the working mode, the MCU and other circuits work normally, the first power supply and the second power supply power under the shallow sleep mode, the MCU and other circuits are both in sleep, the first power supply and the second power supply are powered off under the deep sleep mode, and the MCU and other circuits are both in sleep;
in the deep sleep mode, if a wake-up signal is received, the MCU executes a corresponding application program according to the wake-up signal and judges whether a sleep condition is met after the execution is finished;
if the sleep condition is met, further judging whether the deep sleep condition is met, if so, entering a deep sleep mode, and if not, entering a shallow sleep mode.
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