CN111463265A - 一种基于二维材料的电荷俘获存储器及其制备方法 - Google Patents
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Abstract
本发明公开了一种基于二维材料的电荷俘获存储器及其制备方法,其中存储器包括:自下而上依次设置的硅衬底、隧穿层、电荷俘获层、阻挡层、沟道层、控制电极;其中,隧穿层和阻挡层均为氧化铝材料,电荷俘获层为掺杂的氧化铪薄膜,沟道层为二硫化钼材料。本发明采用掺杂的氧化铪材料作为电荷俘获层,可以有效提高电荷俘获效率,有助于在低电压下获得足够大的存储窗口;采用二维材料作为沟道层,能够提高器件性能。
Description
技术领域
本发明涉及微纳加工技术及存储技术领域,具体涉及一种基于二维材料的电荷俘获存储器及其制备方法。
背景技术
随着信息社会的不断发展,尤其是智能手机、大数据等技术的进步,人们对于大容量存储设备的需求与日俱增,随着半导体工艺的不断发展,芯片单位面积上存储器件的数量不断增加,传统存储器结构越来越难以满足尺寸等比例微缩的进行。闪存一种常用的非易失性移动存储设备,具有存取快速、无噪音、发热少等特点,应用在数码相机、掌上电脑、智能手机等小型数码产品中作为存储介质。
传统的闪存器件采用浮栅存储结构的器件,它的缺陷是需要一种特殊的结构来提升电压来满足它对较高的编程电压的要求,为了器件读写速率和保留特性的权衡,浮栅存储所使用的二氧化硅隧穿层的理想厚度为9nm-11nm,无法满足尺寸等比例微缩的推进。为了支持技术节点的前进,电荷俘获型存储器被提出,它采用电介质材料作为电荷俘获层取代多晶硅浮栅,避免了电荷的一次性泄露,同时,可以引入高k(高介电常数)材料作为隧穿层和阻挡层,在满足性能要求的基础上,将器件尺寸进一步减薄。但是器件减薄超过一定程度后会带来发热、漏电等问题,严重降低存储器件的性能。因而,开发在低电压下具有优秀存储性能的器件至关重要。
发明内容
针对上述已有技术存在的不足,本发明提供一种基于二维材料的电荷俘获存储器及其制备方法,以获得低工作电压下良好的存储性能。
本发明是通过以下技术方案实现的。
一种基于二维材料的电荷俘获存储器,其特征在于,所述存储器包括:自下而上依次设置的硅衬底(1)、隧穿层(2)、电荷俘获层(3)、阻挡层(4)、沟道层(5)、控制电极(6);所述隧穿层(2)和阻挡层(4)均为氧化铝材料,所述电荷俘获层(3)为掺杂的氧化铪薄膜,所述沟道层(5)为二硫化钼材料。
进一步地,所述电荷俘获层(3)为掺杂的氧化铪薄膜,掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物。
一种基于上述的电荷俘获存储器的制备方法,其特征在于,所述方法包括以下步骤:
步骤(一):在硅衬底(1)顶部生长一层氧化铝材料作为隧穿层(2);
步骤(二):在隧穿层(2)顶部沉积一层掺杂的氧化铪薄膜作为电荷俘获层(3);
步骤(三):在电荷俘获层(3)上生长氧化铝材料作为阻挡层(4);
步骤(四):在阻挡层(4)顶部覆盖二硫化钼材料作为沟道层(5);
步骤(五):在沟道层(5)上形成控制电极(6)。
进一步地,所述步骤(一)中生长氧化铝材料作为隧穿层(2)的方法为原子层沉积;所述隧穿层(2)的厚度为3nm-6nm。
进一步地,所述步骤(二)中沉积一层掺杂的氧化铪薄膜作为电荷俘获层(3)的方法为原子层沉积,所述电荷俘获层(3)的厚度为15nm-20nm。
进一步地,所述步骤(二)中掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物。
进一步地,所述步骤(三)中生长氧化铝材料作为阻挡层(4)的制备方法为原子层沉积,所述阻挡层(4)厚度为8nm-12nm。
进一步地,所述步骤(四)中覆盖二硫化钼材料作为沟道层(5)的方法为微机械剥离法或CVD(化学气象沉积),所述沟道层(5)的厚度为0.5nm至2nm。
进一步地,所述步骤(五)中在沟道层(5)上形成控制电极(6)的制备方法为磁控溅射技术。
本发明的有益技术效果,本发明提供一种基于二维材料的电荷俘获存储器及其制备方法,采用掺杂的氧化铪材料作为电荷俘获层,可以有效提高电荷俘获效率,有助于在低电压下获得足够大的存储窗口;采用二维材料(具体为二硫化钼材料)作为沟道层,能够进一步提高器件的存储窗口。
附图说明
图1是本发明的电荷俘获存储器的结构示意图;
图2是低电压范围内器件存储窗口与扫描电压关系曲线。
具体实施方式
下面结合附图和具体实施方式对本发明进行详细说明。
如图1所示,一种基于二维材料的电荷俘获存储器,包括:自下而上依次设置的硅衬底1、隧穿层2、电荷俘获层3、阻挡层4、沟道层5、控制电极6;即在硅衬底1上通过原子层沉积形成氧化铝作为隧穿层2,在隧穿层顶部沉积掺杂的氧化铪作为电荷俘获层3,在电荷俘获层3顶部覆盖氧化铝作为阻挡层4,而后覆盖沟道层5,最后形成控制电极6;其中,隧穿层2和阻挡层4均为氧化铝材料,电荷俘获层3为掺杂的氧化铪薄膜,掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物,沟道层5为二硫化钼材料。
本发明的一种电荷俘获存储器的制备方法,包括以下步骤:
步骤(一):在硅衬底1上生长一层氧化铝材料作为隧穿层2;生长氧化铝的方法为原子层沉积;隧穿层2的厚度为3nm-6nm;
步骤(二):在隧穿层2的顶部沉积一层掺杂的氧化铪薄膜作为电荷俘获层3,其中,掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物;沉积掺杂的氧化铪电荷俘获层的方法为原子层沉积,电荷俘获层的厚度为15nm-20nm;
步骤(三):在电荷俘获层3上利用原子层沉积技术沉积氧化铝作为阻挡层4;阻挡层的4厚度为8nm-12nm;
步骤(四):在阻挡层4顶部覆盖二硫化钼作为沟道层5;方法为微机械剥离法或CVD(化学气象沉积),沟道层5的厚度为0.5nm至2nm。
步骤(五):利用磁控溅射技术在沟道层5上制备控制电极6。
实施例1
本发明的一种电荷俘获存储器的制备方法,包括以下步骤:
步骤(一):在P型硅衬底1的顶部生长一层氧化铝材料作为隧穿层2;生长氧化铝的方法为原子层沉积;隧穿层2的厚度为3nm;
步骤(二):在隧穿层2的顶部沉积一层掺杂的氧化铪薄膜作为电荷俘获层3,掺杂的元素为锆;沉积掺杂的氧化铪电荷俘获层的方法为原子层沉积,电荷俘获层的厚度为20nm;
步骤(三):在电荷俘获层3上利用原子层沉积技术沉积氧化铝作为阻挡层4;阻挡层的4厚度为8nm;
步骤(四):在阻挡层4顶部覆盖二硫化钼作为沟道层5;方法为微机械剥离法,沟道层5的厚度为0.5nm。
步骤(五):利用磁控溅射技术在沟道层5上制备控制电极6。
实施例2
本发明的一种电荷俘获存储器的制备方法,包括以下步骤:
步骤(一):在P型硅衬底1上生长一层氧化铝材料作为隧穿层2;生长氧化铝的方法为原子层沉积;隧穿层2的厚度为6nm;
步骤(二):在隧穿层2的顶部沉积一层掺杂的氧化铪薄膜作为电荷俘获层3,掺杂的元素为钛和镝;沉积掺杂的氧化铪电荷俘获层的方法为原子层沉积,电荷俘获层的厚度为15nm;
步骤(三):在电荷俘获层3上利用原子层沉积技术沉积氧化铝作为阻挡层4;阻挡层的4厚度为12nm;
步骤(四):在阻挡层4顶部覆盖二硫化钼作为沟道层5;方法为CVD,沟道层(5)的厚度为2nm。
步骤(五):利用磁控溅射技术在沟道层5上制备控制电极6。
图2是本发明的存储器的存储窗口随扫描电压的变化曲线,可以看出其在低电压下具有足够大的存窗口。
以上所述的仅是本发明的较佳实施例,并不局限发明。应当指出对于本领域的普通技术人员来说,在本发明所提供的技术启示下,还可以做出其它等同改进,均可以实现本发明的目的,都应视为本发明的保护范围。
Claims (9)
1.一种基于二维材料的电荷俘获存储器,其特征在于,所述存储器包括:自下而上依次设置的硅衬底(1)、隧穿层(2)、电荷俘获层(3)、阻挡层(4)、沟道层(5)、控制电极(6);所述隧穿层(2)和阻挡层(4)均为氧化铝材料,所述电荷俘获层(3)为掺杂的氧化铪薄膜,所述沟道层(5)为二硫化钼材料。
2.根据权利要求1所述的存储器,其特征在于,所述电荷俘获层(3)为掺杂的氧化铪薄膜,掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物。
3.一种如权利要求1-2任一所述的电荷俘获存储器的制备方法,其特征在于,所述方法包括以下步骤:
步骤(一):在硅衬底(1)顶部生长一层氧化铝材料作为隧穿层(2);
步骤(二):在隧穿层(2)顶部沉积一层掺杂的氧化铪薄膜作为电荷俘获层(3);
步骤(三):在电荷俘获层(3)上生长氧化铝材料作为阻挡层(4);
步骤(四):在阻挡层(4)顶部覆盖二硫化钼材料作为沟道层(5);
步骤(五):在沟道层(5)上形成控制电极(6)。
4.根据权利要求3所述的制备方法,其特征在于,所述步骤(一)中生长氧化铝材料作为隧穿层(2)的方法为原子层沉积;所述隧穿层(2)的厚度为3nm-6nm。
5.根据权利要求3所述的制备方法,其特征在于,所述步骤(二)中沉积一层掺杂的氧化铪薄膜作为电荷俘获层(3)的方法为原子层沉积,所述电荷俘获层(3)的厚度为15nm-20nm。
6.根据权利要求3所述的制备方法,其特征在于,所述步骤(二)中掺杂的元素为锆、钛、镝、钆、镱中的一种或几种混合物。
7.根据权利要求3所述的制备方法,其特征在于,所述步骤(三)中生长氧化铝材料作为阻挡层(4)的制备方法为原子层沉积,所述阻挡层(4)厚度为8nm-12nm。
8.根据权利要求3所述的制备方法,其特征在于,所述步骤(四)中覆盖二硫化钼材料作为沟道层(5)的方法为微机械剥离法或CVD,所述沟道层(5)的厚度为0.5nm至2nm。
9.根据权利要求3所述的制备方法,其特征在于,所述步骤(五)中在沟道层(5)上形成控制电极(6)的制备方法为磁控溅射技术。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112331668A (zh) * | 2020-10-27 | 2021-02-05 | 复旦大学 | 一种可见-红外波段二维电荷俘获型存储器及其制备方法 |
CN112349787A (zh) * | 2020-10-26 | 2021-02-09 | 复旦大学 | 一种光电双调制的二维柔性神经突触器件及其制备方法 |
CN112436010A (zh) * | 2020-11-17 | 2021-03-02 | 北京理工大学 | 一种基于二维材料的柔性存储器 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1571161A (zh) * | 2003-04-30 | 2005-01-26 | 三星电子株式会社 | 非易失性半导体存储器件及其制造方法 |
CN102593065A (zh) * | 2012-03-14 | 2012-07-18 | 复旦大学 | 一种背栅薄膜晶体管存储器的制备方法 |
US20150122315A1 (en) * | 2013-11-05 | 2015-05-07 | Samsung Electronics Co., Ltd. | Two-dimensional materials, methods of forming the same, and devices including two-dimensional materials |
-
2020
- 2020-04-14 CN CN202010290015.1A patent/CN111463265A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1571161A (zh) * | 2003-04-30 | 2005-01-26 | 三星电子株式会社 | 非易失性半导体存储器件及其制造方法 |
CN102593065A (zh) * | 2012-03-14 | 2012-07-18 | 复旦大学 | 一种背栅薄膜晶体管存储器的制备方法 |
US20150122315A1 (en) * | 2013-11-05 | 2015-05-07 | Samsung Electronics Co., Ltd. | Two-dimensional materials, methods of forming the same, and devices including two-dimensional materials |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112349787A (zh) * | 2020-10-26 | 2021-02-09 | 复旦大学 | 一种光电双调制的二维柔性神经突触器件及其制备方法 |
CN112331668A (zh) * | 2020-10-27 | 2021-02-05 | 复旦大学 | 一种可见-红外波段二维电荷俘获型存储器及其制备方法 |
CN112436010A (zh) * | 2020-11-17 | 2021-03-02 | 北京理工大学 | 一种基于二维材料的柔性存储器 |
CN112436010B (zh) * | 2020-11-17 | 2022-09-13 | 北京理工大学 | 一种基于二维材料的柔性存储器 |
CN115224156A (zh) * | 2022-06-14 | 2022-10-21 | 清华大学 | 一种片上红外感存算一体的光电器件及其制备方法 |
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