CN111463206B

CN111463206B - Memory and forming method thereof

Info

Publication number: CN111463206B
Application number: CN202010322638.2A
Authority: CN
Inventors: 颜逸飞; 冯立伟; 陈凯评
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-04-22
Filing date: 2020-04-22
Publication date: 2022-03-29
Anticipated expiration: 2040-04-22
Also published as: CN111463206A; CN114464622A

Abstract

The invention provides a memory and a forming method thereof, wherein an insulation pattern at least covers the side wall of a first opening of an interval node contact structure and extends upwards to be higher than the node contact structure, the upper surface of the insulation pattern is also sunken into the first opening to form a sunken part, so that the existing insulation pattern formed by two film layers can be replaced by one film layer, the steps of grinding and removing the insulation material layer with partial thickness and reforming a mask material layer in the prior art are omitted, the preparation process of the memory is simplified, the preparation efficiency is improved, and the surface of a substrate is flattened by adopting a plurality of grinding processes when a capacitor structure is formed, so that the performance of the memory cannot be influenced even if the surface of the insulation pattern is uneven.

Description

Memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a memory and a forming method thereof.

Background

A Memory, such as a Dynamic Random Access Memory (DRAM), generally has a Memory cell array including a plurality of Memory cells arranged in an array. The memory is provided with a plurality of word line structures and bit line structures, wherein the word line structures are embedded in a substrate, the bit line structures are formed on the substrate and are electrically connected with corresponding memory units, the memory also comprises a capacitor structure, the capacitor structure is used for storing charges representing stored information, and the memory units can be electrically connected with the capacitor structure through a node contact structure, so that the storage function of each memory unit is realized.

Fig. 1a to fig. 1e are schematic structural diagrams formed by a conventional memory forming method. Referring to fig. 1a to 1d, a method of forming a memory device includes: as shown in fig. 1a, after forming the bit line structure 200 ' on the substrate 100 ', a conductive material layer 300 ' covering the substrate 100 ' and the bit line structure 200 ' is formed. Then, as shown in fig. 1b, the conductive material layer 300 'and the bit line structure 200' are etched to form a first opening 300a ', and the first opening 300 a' separates the remaining conductive material layer 300 'into a plurality of node contact structures 300 b'. Then, as shown in fig. 1c, an insulating material layer 410 'is formed on the plurality of node contact structures 300 b', the insulating material layer 410 'also filling the first openings 300 a'. At this time, since the upper surface of the insulating material layer 410 'may be uneven, as shown in fig. 1d, it is necessary to grind the insulating material layer 410' until the insulating material layer 410 'on the upper surface of the node contact structure 300 b' is removed to make the upper surfaces of the insulating material layer 410 'and the node contact structure 300 b' even. Then, as shown in fig. 1e, a mask material layer 420 ' and a stacked material layer 500 ' are sequentially formed on the insulating material layer 410 ', and finally, the stacked material layer 500 ' and the mask material layer 420 ' are etched to form a second opening 501a ', so that the second opening 501a ' exposes the node contact structure 300b ', and a lower electrode of the capacitor structure can be formed in the second opening 501a ' in a subsequent step. At this time, the remaining insulating material layer 410 ' and the mask material layer 420 ' constitute a plurality of insulating patterns 400 '. Here, each of the insulation patterns 400 'includes two film layers (the stacked insulation material layer 410' and the mask material layer 420 '), functions of which are substantially the same in subsequent steps, so that constructing the insulation patterns 400' using the two film layers results in increased difficulty and complexity of a manufacturing process of the memory and reduced manufacturing efficiency.

Disclosure of Invention

The invention aims to provide a memory and a forming method thereof, which can simplify the forming process of the memory under the condition of not influencing the performance of the memory.

In order to achieve the above object, the present invention provides a memory comprising:

a substrate;

a plurality of node contact structures extending upwardly from the substrate;

a plurality of first openings between adjacent node contact structures to electrically isolate the node contact structures;

the insulating pattern is positioned in the first opening, at least covers the side wall of the first opening and extends upwards to be higher than the node contact structure, and the upper surface of the insulating pattern is also sunken into the first opening to form a sunken part; and the number of the first and second groups,

and the capacitor structure is positioned on the node contact structure and is electrically connected with the node contact structure.

Optionally, the capacitor structure includes:

and a metal oxide layer at least partially on the insulation pattern.

Optionally, the metal oxide layer covers the opening of the recess to form an air gap; alternatively, the metal oxide layer fills a partial depth recess to form an air gap.

Optionally, the metal oxide layer completely fills the recess.

Optionally, the insulating pattern further extends to cover a top portion of the node contact structure.

Optionally, the node contact structure is divided into an upper node contact and a lower node contact by taking the height position of the bottom of the first opening as a limit, and the maximum width dimension of the upper node contact is greater than the maximum width dimension of the lower node contact in the direction perpendicular to the height direction.

The invention also provides a forming method of the memory, which comprises the following steps:

providing a substrate;

forming a plurality of node contact structures on the substrate, the node contact structures extending upward from the substrate;

forming a plurality of first openings between adjacent node contact structures, the first openings electrically isolating the node contact structures;

forming an insulating pattern in the first opening, wherein the insulating pattern at least covers the side wall of the first opening and extends upwards to be higher than the node contact structure, and the upper surface of the insulating pattern is also sunken into the first opening to form a sunken part; and the number of the first and second groups,

and forming a capacitor structure on the node contact structure, and electrically connecting the capacitor structure with the node contact structure.

Optionally, the step of forming the insulation pattern includes:

forming an insulating material layer on the node contact structure, wherein the insulating material layer covers the node contact structure and at least covers the side wall of the first opening, and the upper surface of the insulating material layer is recessed into the first opening corresponding to the first opening to form the recessed portion;

forming a stacked material layer on the insulating material layer; and the number of the first and second groups,

and etching the stacked material layers to form a plurality of second openings corresponding to the node contact structures, wherein the bottom parts of the second openings expose at least partial top parts of the corresponding node contact structures, and the rest of the insulating material layers form a plurality of insulating patterns.

Optionally, the step of forming a capacitor structure on each node contact structure at least includes:

and forming a capacitor structure in the second opening, wherein the bottom of the capacitor structure is electrically connected with the exposed top of the node contact structure, and the metal oxide layer of the capacitor structure is at least partially located on the insulating pattern.

Optionally, the metal oxide layer covers the opening of the recess to form an air gap; or the metal oxide layer fills the recess part of the depth to form an air gap; alternatively, the metal oxide layer completely fills the recess.

In the memory and the forming method thereof provided by the invention, the insulating pattern at least covers the side wall of the first opening of the interval node contact structure and extends upwards to be higher than the node contact structure, the upper surface of the insulating pattern is also sunken into the first opening to form a sunken part, so that the existing insulating pattern formed by two film layers can be replaced by one film layer, the steps of grinding and removing the insulating material layer with partial thickness and reforming the mask material layer in the prior art are omitted, the preparation process of the memory is simplified, the preparation efficiency is improved, and the surface of the substrate is flattened by adopting a plurality of grinding processes when the capacitor structure is formed, so that the performance of the memory cannot be influenced even if the surface of the insulating pattern is uneven; further, parasitic capacitance between node contact structures is reduced by forming an air gap in the first opening.

Drawings

FIGS. 1a to 1e are schematic structural diagrams formed by a conventional memory forming method;

FIG. 2 is a flow chart of a method for forming a memory according to an embodiment of the invention;

FIGS. 3a to 4g are schematic structural diagrams illustrating a memory formed by a method of forming a memory according to an embodiment of the invention;

FIG. 5a is a schematic diagram of a partial structure of a memory according to a second embodiment of the present invention;

FIG. 5b is a schematic diagram of a partial structure of another memory according to a second embodiment of the present invention;

fig. 6a is a schematic diagram of a partial structure of a memory according to a third embodiment of the present invention;

fig. 6b is a schematic partial structure diagram of another memory according to a third embodiment of the present invention;

wherein the reference numerals are:

100' -a substrate; a 200' -bit line structure; 300' -a layer of conductive material; 300 b' -node contact structure; 300 a' -a first opening; 410' -a layer of insulating material; 420' -a layer of masking material; 500' -stacking material layers; 501 a' -a second opening; 400' -an insulating pattern;

100-a substrate; STI-trench isolation structure; a 200-bit line structure; 200 a-node contact window; 300-a layer of conductive material; 300 a-a first opening; 300 b-node contact structure; 400-a layer of insulating material; 400 a-insulating pattern; 500-stacking material layers; 500 a-first oxide layer; 500 b-first support layer; 500 c-a second oxide layer; 500 d-second support layer; 500 e-a second opening; 500 f-third opening; 510 a-a first support structure; 510 b-a second support structure; 600 a-cylindrical lower electrode; 600 b-a metal oxide layer; 600 c-upper electrode; 600-a capacitive structure;

g1, G2-air gap;

x1 — maximum width dimension of upper node contact;

x2-maximum width dimension of lower node contact;

x3-width dimension of the second opening in a direction perpendicular to the height direction.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 4b or fig. 4g is a schematic diagram of a partial structure of the memory in this embodiment. As shown in fig. 4b or fig. 4g, the Memory is, for example, a Memory device such as a Dynamic Random Access Memory (DRAM) device, but not limited thereto. In detail, the memory first includes a substrate 100, and the substrate 100 is, for example, a silicon substrate (silicon substrate), a silicon containing substrate (silicon containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like. A memory cell region (memory cell region) and a peripheral region (peripheral region) are also defined in the substrate 100, and the memory region is only schematically illustrated in the drawings of the present embodiment.

At least one Shallow Trench Isolation (STI) is formed on the substrate 100 to define an active region (not shown) in the substrate 100. The STI is formed by, for example, first forming at least one trench in the substrate 100 by etching, and then filling the trench with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto. In addition, a plurality of buried gates (not shown) may be formed in the active region of the substrate 100, and the buried gates extend in parallel to each other along the same direction and cross the active region to serve as buried word lines (not shown) of the memory.

Further, the active region is used for constituting a storage transistor, for example, a source/drain region may be further formed in the active region, where the source/drain region includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the buried gate, so as to jointly constitute the storage transistor. It is understood that the bottom of the first and second source/drain regions is lower than the top of the buried gate, so that there is an overlapping region between the first and second source/drain regions and the buried gate.

Further, a plurality of bit line structures 200 may be formed on the substrate 100 and extend in parallel to each other along another direction perpendicular to the buried gates so as to simultaneously cross the active regions and the buried gates in the substrate 100. The bit line structure 200 includes a first bit line conductive layer, a second bit line conductive layer, and a third bit line conductive layer stacked in sequence from bottom to top. The first bit line conductive layer is made of doped polysilicon, the second bit line conductive layer is made of titanium nitride, and the third bit line conductive layer is made of tungsten. Further, the bit line structure 200 may further include a bit line shielding layer and an isolation sidewall. The bit line shielding layer is formed above the bit line conducting layers which are stacked in sequence, and the isolation side walls at least cover the side walls of the bit line conducting layers which are stacked in sequence and the side walls of the bit line shielding layer.

The bitline structure 200 may define a node contact 200a, the node contact 200a being configured to receive a node contact structure 300 b. Wherein, at least a portion of the bottom of the node contact 200a may further extend into the substrate 100. The defined node contacts 200a are aligned in the direction in which the bit line structure 200 and the buried gate extend, and the node contacts 200a are arranged in an array, for example, to form an array of node contacts 200 a. At this time, it can be considered that the plurality of node contacts 200a are arranged in a plurality of rows in the direction in which the bit line structure 200 and the buried gate extend.

With continued reference to fig. 4b or fig. 4g, the node contact structures 300b fill the node contact windows 200a and are correspondingly arranged in a plurality of rows, and the node contact structures 300b are electrically connected to the corresponding active regions.

In this embodiment, the node contact structures 300b fill the node contact windows 200a, and the top positions of the node contact structures 300b are further higher than the top positions of the node contact windows 200 a. Further, in the present embodiment, the node contact structure 300b is located on the substrate 100, and as an alternative embodiment, the node contact structure 300b may also extend into an active region of the substrate 100 and be electrically connected to the active region.

As an alternative embodiment, the node contact structure 300b includes a conductive contact layer filling the node contact window 200a to electrically connect with the active region. Further, the node contact structure 300b further includes an electrically conductive layer filling the node contact 200a and formed on the electrically conductive contact layer to be electrically connected to the electrically conductive contact layer.

With continued reference to fig. 4b or fig. 4g, the node contact structures 300b are separated by first openings 300 a. In the present embodiment, the first opening 300a extends into the bit line structure 200 from a position flush with the top of the node contact structure 300b (and a portion of the bit line shielding layer on the top of the bit line structure 200 is cut), so that the adjacent node contact structures 300b can be electrically insulated.

With reference to fig. 4b or fig. 4g, in this embodiment, the first opening 300a is located on the bit line structure 200, but in the direction perpendicular to the height direction, the position of the bit line structure 200 is not directly opposite to the position of the first opening 300a, but is shifted to the right by a certain distance with respect to the bit line structure 200, so that the area can be saved, and the device size can be reduced. Of course, in other embodiments, the position of the bit line structure 200 in the direction perpendicular to the height direction may also be opposite to the position of the first opening 300a, and the invention is not limited thereto.

In this embodiment, the node contact structure 300b includes an upper node contact portion located above the height position of the bottom of the first opening 300a, and a lower node contact portion located below the height position of the bottom of the first opening 300 a. It can also be understood that the node contact structure 300b is divided into an upper node contact and a lower node contact by using the height position of the bottom of the first opening 300a as a boundary, the maximum width dimension X1 of the upper node contact is greater than the maximum width dimension X2 of the lower node contact in the direction perpendicular to the height direction, and the width dimension of the upper node contact is greater, so that the difficulty in manufacturing the node contact structure 300b can be reduced.

Further, an insulating pattern 400a is formed in each of the first openings 300a, and the insulating pattern 400a covers at least sidewalls of the first openings 300a and extends upward to be higher than the node contact structure 300 b. Specifically, the top of the insulation pattern 400a is located at a first height position, and the top of the node contact structure 300b is located at a second height position, and the first height position is higher than the second height position.

With continuing reference to fig. 4b or fig. 4g, in the present embodiment, the insulation pattern 400a is a single layer of nitride, such as silicon nitride, etc., as an alternative embodiment, the insulation pattern 400a may also be a single layer of carbon-doped nitride (such as carbon-doped silicon nitride), carbide (such as silicon carbide), or oxide (such as tantalum oxide, titanium oxide), etc., and the present invention is not limited thereto. Of course, the insulation pattern 400a may also be a combination of at least two film layers, such as a composite film layer of oxide and nitride, and the invention is not limited thereto.

Further, the insulating pattern 400a of the present invention has a portion filling the first opening 300a and a portion extending upward to be higher than the node contact structure 300b, so that compared to the insulating pattern 400a formed by using two layers in the prior art, the present invention is equivalent to using one layer instead of two layers with the same function, and the structure is simpler, the manufacturing process is simplified, and no influence is generated on the performance of the memory.

As shown in fig. 4b or fig. 4g, the upper surface of the insulation pattern 400a is further recessed into the first opening 300a to form a recess. In this embodiment, the insulation pattern 400a covers only the inner wall of the first opening 300a, and the insulation pattern 400a between the sidewalls of the first opening 300a has a gap, which may be regarded as a recess formed by the upper surface of the insulation pattern 400a being recessed into the first opening 300a, and in this case, the recess is linear as a whole. As an alternative embodiment, the insulation pattern 400a may fill the first opening 300a, and the upper surface of the insulation pattern 400a is still recessed into the first opening 300a, but the bottom of the recess is higher than the top of the first opening 300a, so that the recess is only located in the portion of the insulation pattern 400a higher than the top of the first opening 300a, and at this time, the recess is in a horn shape with a large top and a small bottom. It is understood that the recess is not limited to a line shape or a horn shape, but may be other shapes such as a rectangle, a trapezoid, etc., and the present invention is not limited thereto.

As shown in fig. 4b or fig. 4g, the width dimension of the insulating pattern 400a in the direction perpendicular to the height direction is also larger than the width dimension of the first opening 300a, so that the top of the insulating pattern 400a also extends laterally to the top of the portion of the node contact structure 300b covering both sides of the first opening 300 a. Of course, as an alternative embodiment, the width dimension of the insulating pattern 400a in the direction perpendicular to the height direction may also be smaller than or equal to the width dimension of the first opening 300a, so that the insulating pattern 400a covers only a portion of the top of the node contact structure 300b on either side of the first opening 300a, or so that the insulating pattern 400a is only located in the first opening 300 a.

Referring to fig. 4b, the insulating pattern 400a is formed thereon with stacked structures separated by second openings 500e, one of the second openings 500e is positioned above one of the node contact structures 300b, and the second opening 500e exposes at least a portion of the top of the node contact structure 300 b. The sidewall of the second opening 500e is formed by the sidewall of the insulating pattern 400a and the sidewall of the stack structure, and the sidewall of the insulating pattern 400a is flush with the sidewall of the stack structure, so that the second opening 500e has a straight groove structure, but, as an alternative embodiment, the sidewall of the insulating pattern 400a and the sidewall of the stack structure may not be flush, so that the second opening 500e has a stepped groove structure.

As shown with continued reference to fig. 4b, the air gap G1 may be located between the insulation pattern 400a and the stacked structure. Specifically, the stack structure sequentially includes a first oxide layer 500a, a first support layer 500b, a second oxide layer 500c, and a second support layer 500d from bottom to top, the first oxide layer 500a covers the opening of the recess, and the first support layer 500b, the second oxide layer 500c, and the second support layer 500d are sequentially stacked above the first oxide layer 500 a. It should be understood that, since the stacked structure is separated by the second opening 500e, the first oxide layer 500a, the first support layer 500b, the second oxide layer 500c and the second support layer 500d are also patterned film layers at this time.

Referring to fig. 4g, a cylindrical lower electrode 600a may be further formed on the node contact structure 300b, and a metal oxide layer 600b covers the plurality of insulation patterns 400a and conformally covers the surface of the cylindrical lower electrode 600 a.

Specifically, the bottom of the cylindrical bottom electrode 600a contacts and is electrically connected to the node contact structure 300b, and the cylindrical bottom electrode 600a extends upward through the second opening 500 e. Each or at least one of the cylindrical lower electrodes 600a has a cylindrical shape with a closed bottom.

The sidewall of the cylindrical lower electrode 600a has a first support structure 510a and a second support structure 510b spaced apart from each other in the height direction, the first support structure 510a is used for supporting the sidewall of the lower end of the cylindrical lower electrode 600a, and the second support structure 510b is used for supporting the sidewall of the upper end of the cylindrical lower electrode 600a, which may be the end of the cylindrical lower electrode 600a away from the surface of the substrate 100, so as to prevent the cylindrical lower electrode 600a from tilting.

With continued reference to fig. 4g, a portion of the cylindrical lower electrode 600a has no first support structure 510a and no second support structure 510b on one sidewall, such that a third opening 500f is formed between adjacent cylindrical lower electrodes 600a, and the third opening 500f exposes the insulation pattern 400 a. The metal oxide layer 600b may conformally cover the first support structure 510a, the second support structure 510b, and the cylindrical lower electrode 600 a. That is, the metal oxide layer 600b covers the exposed surfaces of the cylindrical lower electrode 600a, the first support structure 510a, and the second support structure 510b, and the metal oxide layer 600b also needs to cover the insulation pattern 400 a.

Further, as shown in fig. 4G, the portion of the metal oxide layer 600b covering the insulation pattern 400a covers the recess to form an air gap G1. Of course, the metal oxide layer 600b may also extend into the recess, so that the upper portion of the recess is filled, and at this time, the recess is not filled, and the air gap G1 is preserved.

With continued reference to fig. 4g, an upper electrode 600c is also formed on the metal oxide layer 600b, the upper electrode 600c partially facing the cylindrical lower electrode 600a with the metal oxide layer 600b sandwiched therebetween. The upper electrode 600c also extends to cover the top of the second support structure 510b and fills the second opening 500e and the third opening 500f, and the cylindrical lower electrode 600a, the metal oxide layer 600b and the upper electrode 600c together form a capacitor structure 600.

In this embodiment, two node contact structures 300b are respectively disposed on two sides of the air gap G1, so that the air gap G1 with a low dielectric constant can reduce the parasitic capacitance between the adjacent node contact structures 300b, and improve the performance of the memory.

In this embodiment, the width dimension X3 of the second opening 500e in the direction perpendicular to the height direction is smaller than the maximum width dimension X1 of the upper node contact, and at this time, the second opening 500e only exposes a part of the top of the node contact structure 300 b. It should be understood that the width dimension X3 of the second opening 500e perpendicular to the height direction may be smaller than or equal to the maximum width dimension X1 of the upper node contact, in practice, the second opening 500e is completely exposed at the top of the node contact structure 300b, and the insulation pattern 400a is only located in the first opening 300a or only covers a part of the top of the node contact structure 300b at one side of the first opening 300 a.

The method for forming the memory device according to the present embodiment will be described in detail with reference to fig. 2 and fig. 3a to 4 g. Fig. 2 is a schematic flow chart of a method for forming a memory according to an embodiment of the present invention, and fig. 3a to 4g are schematic structural diagrams of a semiconductor structure formed in a manufacturing process of the memory according to an embodiment of the present invention.

As shown in fig. 2, the method for forming the memory includes:

step S100: providing a substrate 100;

step S200: forming a plurality of node contact structures 300b on the substrate 100, the node contact structures 300b extending upward from the substrate 100;

step S300: forming a plurality of first openings 300a between adjacent node contact structures 300b, the first openings 300a electrically isolating the adjacent node contact structures 300 b;

step S400: forming an insulation pattern 400a in the first opening 300a, wherein the insulation pattern 400a at least covers a sidewall of the first opening 300a and extends upward to be higher than the node contact structure 300b, and an upper surface of the insulation pattern 400a is further recessed into the first opening 300a to form a recessed portion; and the number of the first and second groups,

step S500: and forming a capacitor structure on the node contact structure, and electrically connecting the capacitor structure with the node contact structure.

Specifically, referring to fig. 3a, step S100 is performed to provide a substrate 100, where the substrate 100 has a trench isolation structure STI formed therein, and a plurality of active regions are defined by the trench isolation structure SIT. A plurality of buried gates are also formed in the active region as word line symbols, but not limited thereto. In some embodiments, other types of word line structures may be formed as desired. In addition, the material of the electrode of the buried gate may include aluminum (Al), tungsten (W), copper (Cu), titanium aluminum (TiAl) or other suitable conductive material, and the dielectric covering the electrode of the buried gate may include silicon nitride, silicon oxynitride, silicon carbonitride or other suitable insulating material.

Further, a source/drain region is also formed in the active region of the substrate 100, a side edge boundary of the source/drain region extends to a sidewall of the buried gate near the top opening, and a bottom boundary of the source/drain region is lower than a top position of the buried gate, so that there is a mutually opposite overlapping region between the source/drain region and the buried gate. Specifically, the source/drain region includes a first source/drain region and a second source/drain region, and the first source/drain region and the second source/drain region are respectively located at two sides of the buried gate. In this embodiment, the side edge boundary of the first source/drain region further extends to the sidewall of the trench isolation structure STI.

It should be noted that, the source/drain region may be prepared after the buried gate is formed, or the source/drain region may be preferentially formed and then the buried gate is prepared, which is not limited herein.

A bit line structure 200 is also formed on the substrate 100, and the bit line structure 200 includes three conductive material layers stacked in sequence. Based on this, the formed bit line structure 200 may include a first bit line conductive layer, a second bit line conductive layer, and a third bit line conductive layer. Further, the bit line structure 200 further includes a bit line shielding layer, which may be a patterned film layer and formed above the three conductive material layers. In an alternative, for example, the patterned bit line shielding layer is used to sequentially perform a patterning process on the conductive material layer thereunder. In this embodiment, the method for forming the bit line structure 200 further includes: and forming isolation side walls on the side walls of the first bit line conducting layer, the second bit line conducting layer, the third bit line conducting layer and the bit line shielding layer.

As shown in fig. 3a, in the bit line structure 200, a portion is located on the substrate 100, and a portion extends from the substrate 100 to an active region of the substrate 100. The bit line structure 200 defines a plurality of node contact windows 200a on the substrate 100.

Referring to fig. 3b, steps S200 and S300 are performed to form a conductive material layer 300 on the substrate 100, wherein the conductive material layer 300 covers and fills the node contact 200a and extends to cover the top of the bit line structure 200. The conductive material layer 300 is used to form a node contact structure, and the material thereof may include a conductive material containing silicon, such as amorphous silicon, polysilicon, and other conductive materials, such as a metal conductive material. For example, the lower portion of the conductive material layer 300 may be a conductive material containing silicon, and the upper portion of the conductive material layer 300 may be a lower resistivity metal conductive material such as tungsten, but not limited thereto. In addition, a metal silicide layer may be optionally formed between the lower portion and the upper portion of the conductive material layer 300 to reduce the contact resistance between the conductive material containing silicon and the metal conductive material, but not limited thereto.

Referring to fig. 3b and 3c, the conductive material layer 300 and at least a portion of the height of the bit line structure 200 are etched to form a plurality of first openings 300a, wherein the first openings 300a correspond to the bit line structures 200 one to one. As shown in fig. 3, the first opening 300a separates the remaining conductive material layer 300, and the remaining conductive material layer 300 may constitute a plurality of node contact structures 300b, each node contact structure 300b being electrically isolated from each other.

In this embodiment, the node contact window 200a is located on the substrate 100, so that the node contact structure 300b is also formed on the substrate 100. As an alternative embodiment, before forming the conductive material layer 300, the bottom of the node contact window 200a may be etched, so that the node contact window 200a extends into the active region of the substrate 100, and thus the node contact structure 300b may extend from the substrate 100 into the active region and be electrically connected with the active region.

Referring to fig. 3c, in the present embodiment, the position of the bit line structure 200 and the first opening 300a is offset (shifted to the right) in the direction perpendicular to the height direction (i.e., the thickness direction of the substrate 100), so that the process window of the first opening 300a is widened and the area is saved. Of course, as an alternative embodiment, the positions of the bit line structure 200 and the first opening 300a may also be opposite, and the invention is not limited thereto.

With reference to fig. 3c, the node contact structure 300b is divided into an upper node contact and a lower node contact by taking the height position of the bottom of the first opening 300a as a boundary, the maximum width dimension X1 of the upper node contact is greater than the maximum width dimension X2 of the lower node contact in the direction perpendicular to the height direction, and the manufacturing difficulty of the node contact structure 300b can be reduced by increasing the width dimension of the node contact structure 300b near the top of the first opening 300 a.

Referring to fig. 3d, an insulating material layer 400 is formed on the node contact structure 300b, the insulating material layer 400 covers the node contact structure 300b and extends to the sidewall of the first opening 300a covering the first opening 300a, the insulating material layer 400 between the sidewalls of the first opening 300a has a gap, and the gap can also be regarded as a recess formed by the portion of the upper surface of the insulating material layer 400 corresponding to the first opening 300a being recessed into the first opening 300 a.

As can be seen from fig. 3d, the recessed portion extends from the highest position of the insulating material layer 400 in the height direction into the first opening 300a, so that the recessed portion has a linear shape. However, it should be understood that when the thickness of the insulating material layer 400 is increased on the basis of fig. 3d, the insulating material layer 400 can fill the first opening 300a, and the surface of the insulating material layer 400 is only recessed to the area above the first opening 300a, so that the bottom height of the recessed portion is higher than or equal to the top height of the first opening 300a, and the recessed portion is in the shape of a horn with a large opening and a small opening.

In this embodiment, the insulating material layer 400 is a single layer of silicon nitride, and as an alternative embodiment, the material of the insulating material layer 400 may also be a carbon-doped nitride (e.g., carbon-doped silicon nitride) or a carbide (e.g., silicon carbide), but is not limited thereto.

It should be understood that, after the insulating material layer 400 is formed, the present embodiment does not perform a grinding process, and in this case, the surface of the substrate 100 may be uneven but have a rugged profile.

Referring to fig. 4a, step S500 is performed to form a first oxide layer 500a, a first supporting layer 500b, a second oxide layer 500c and a second supporting layer 500d on the insulating material layer 400 from bottom to top in sequence, wherein the first oxide layer 500a, the first supporting layer 500b, the second oxide layer 500c and the second supporting layer 500d are stacked to form a stacked material layer 500. The thickness of the second supporting layer 500d is preferably greater than that of the first supporting layer 500b, so as to prevent the excessively thick first supporting layer 500b from affecting the size of the region where the capacitor structure can be formed, and the thicker second supporting layer 500d can ensure the supporting effect. In some embodiments, only the first oxide layer 500a and the first support layer 500b may be formed without forming the second oxide layer 500c and the second support layer 500d, if necessary. In addition, the first oxide layer 500a and the second oxide layer 500c may respectively include a single layer or multiple layers of oxide materials, such as silicon oxide, tetraethyl orthosilicate (TEOS), or boro-phospho-silicate-glass (BPSG), and the first support layer 500b and the second support layer 500d may respectively include a single layer or multiple layers of materials, such as nitride (e.g., silicon nitride), carbon-doped nitride (e.g., carbon-doped silicon nitride), carbide (e.g., silicon carbide), or oxide (e.g., tantalum oxide, titanium oxide), etc., but are not limited thereto.

Referring to fig. 4b, in step S400, an etching process may be performed by using a patterned mask layer (not shown) to pattern the stacked material layer 500 and the insulating material layer 400. Specifically, the second support layer 500d, the second oxide layer 500c, the first support layer 500b, the first oxide layer 500a, and the insulating material layer 400 are sequentially etched using the patterned mask layer as a mask, thereby forming a plurality of second openings 500 e. The position of one of the second openings 500e matches the position of one of the node contact structures 300b, and the second opening 500e exposes at least a portion of the top of the node contact structure 300 b.

With continued reference to fig. 4b, the second opening 500e separates the remaining stacked material layers 500 to form a plurality of stacked structures, and the second opening 500e also separates the remaining insulating material layers 400 to form a plurality of insulating patterns 400a, and the insulating patterns 400 a. Each of the stacked structures is positioned directly above the corresponding insulation pattern 400a, and a width dimension of the stacked structure is equal to a width dimension of the insulation pattern 400a in a direction perpendicular to a height direction, that is, sidewalls of the second opening 500e are constituted by sidewalls of the stacked structure and sidewalls of the insulation pattern 400 a.

Referring to fig. 4b, in the present embodiment, a deposition process with poor trench filling capability is used to form the first oxide layer 500a, such that the formed first oxide layer 500a only covers the recess opening, and an air gap G1 is formed between the first oxide layer 500a and the insulation pattern 400 a. Of course, a deposition process with better trench filling capability may be used to form the first oxide layer 500a, but the reaction speed is increased by controlling the process parameters, so that the formed first oxide layer 500a only covers the recess opening. Further, the first oxide layer 500a may extend into the recess, filling the upper portion of the recess, and the air gap G1 may be formed as long as the recess is not filled.

It is to be understood that the air gap G1 is located between each of the stacked structures and the corresponding insulation pattern 400a after the second opening 500e is formed.

With reference to fig. 4b, in the present embodiment, the width dimension X3 of the second opening 500e is smaller than the maximum width dimension X1 of the upper node contact in the direction perpendicular to the height direction, such that only a portion of the top of the node contact structure 300b is exposed by the second opening 500e, and a portion of the insulating material layer 400 covering the top of the node contact structure 300b is retained, such that the formed insulating pattern 400a further extends from the first opening 300a to a portion of the node contact structure 300b covering both sides of the first opening 300 a.

As an alternative embodiment, the width dimension X3 of the second opening 500e may be greater than or equal to the maximum width dimension X1 of the upper node contact, such that the portion of the insulating material layer 400 covering the top of the node contact structure 300b is completely removed, such that the formed insulating pattern 400a exists only in the first opening 300a and extends upward to be higher than the first opening 300a (and naturally also higher than the node contact structure 300 b). Further, by changing the position of the second opening 500e in the direction perpendicular to the height direction, the insulating pattern 400a may be formed to extend from the first opening 300a to a portion of the node contact structure 300b covering either side of the first opening 300a, which is not illustrated herein.

Further, the method for forming the memory may further include the steps of:

referring to fig. 4c, after the second opening 500e is formed, the patterned mask layer is removed, and a cylindrical lower electrode 600a is formed in the second opening 500e, wherein the cylindrical lower electrode 600a sequentially penetrates through the second supporting layer 500d, the second oxide layer 500c, the first supporting layer 500b, the first oxide layer 500a and a portion of the insulating pattern 400a, but not limited thereto. In addition, the cylindrical lower electrode 600a is electrically connected to the corresponding node contact structure 300 b. As shown in fig. 4c, the second supporting layer 500d, the second oxide layer 500c, the first supporting layer 500b and the first oxide layer 500a are all located on the side of the first electrode 61.

Referring to fig. 4d, the second support layer 500d is patterned by using a patterned mask layer, and a plurality of third openings 500f are formed on the second support layer 500d (only one third opening 500f is schematically shown). The planar shape of the third opening 500f may be a triangle, a diamond, or the like, and the third opening 500f defines the range of the second support layer 500d and the first support layer 500b to be subsequently removed. It is noted that the shape of the third openings 500f or the arrangement of the third openings 500f will affect the strength of the first and second support layers 500b and 500d for supporting the cylindrical bottom electrode 600a and the efficiency of removing the first and

second oxide layers

500a and 500 c. Therefore, by adjusting the shape of the third openings 500f and the arrangement of the third openings 500f, the cylindrical bottom electrode 600a can be supported more strongly and the oxide layer can be removed more efficiently.

Referring to fig. 4e, the second oxide layer 500c at the bottom of the third opening 500f is etched, such that the third opening 500f extends downward and exposes a portion of the first supporting layer 500 b. The etching process used in this step may preferably be an isotropic (isotropic) etching process, such as a wet etching process, so that the second oxide layer 500c can be completely removed (the second oxide layer 500c covered by the second support layer 500d can also be removed), but not limited thereto.

Referring to fig. 4e, the first support layer 500b at the bottom of the third opening 500f is removed by an etching process, such that the first support layer 500b is patterned, and the third opening 500f extends further downward to expose the first oxide layer 500 a. The etching process in this step is preferably an anisotropic (anisotropic) etching process, such as a dry etching process, so that only a portion of the first support layer 500b at the bottom of the third opening 500f is removed, and the first support layer 500b covered by the second support layer 500d remains. It is understood that lateral etching due to the anisotropic etching process is less pronounced, thereby leaving a protruding structure like a waistband on the sidewall of the cylindrical lower electrode 600 a.

Finally, the first oxide layer 500a under the third opening 500f is completely removed by using the etching process again, so that the third opening 500f extends to the insulating pattern 400a, and the sidewall of the third opening 500f exposes the sidewall of the cylindrical lower electrode 600 a. The etching process used in this step may preferably be an isotropic (isotropic) etching process, such as a wet etching process, so that the first oxide layer 500a (the second oxide layer 500c covered by the second support layer 500d and the first support layer 500b may also be removed) may be completely removed, but not limited thereto.

In some embodiments, the first support layer 500b, the first oxide layer 500a, the second support layer 500d, and the second oxide layer 500c may be etched sequentially by a single etching step, or the first support layer 500b, the first oxide layer 500a, the second support layer 500d, and the second oxide layer 500c may be etched separately by etching steps including a plurality of different manufacturing process conditions as needed. For example, when the first support layer 500b and the second support layer 500d are nitride layers, a plasma etching (plasma etching) may be performed on the first support layer 500b and the second support layer 500d, and the reaction gas used for the plasma etching may include, but is not limited to, oxygen, nitrogen, hydrogen, nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), and/or methane (CH 4). The etching selectivity of the plasma etching to different materials can be controlled by adjusting the composition ratio of the reaction gases, for example, in some embodiments, the etching rate of the plasma etching to the first support layer 500b and the second support layer 500d can be greater than the etching rate to the first oxide layer 500a and the second oxide layer 500c, but not limited thereto. In addition, the etching steps performed on the first oxide layer 500a and the second oxide layer 500c may also have a higher etching selectivity ratio for the first support layer 500b and the second support layer 500d, thereby improving the control condition of the etching process for the formed etching pattern.

Referring to fig. 4e, after removing the first oxide layer 500a, the second oxide layer 500c, a portion of the first support layer 500b, and a portion of the second support layer 500d, the surface of the insulation pattern 400a is exposed, the remaining first support layer 500b forms the first support structure 510a, the remaining second support layer 500d forms the second support structure 510b, and the first support structure 510a and the second support structure 510b may be used to support the top region and the middle region of the cylindrical lower electrode 600a, respectively, and when the height of the cylindrical lower electrode 600a is larger, may serve to support the cylindrical lower electrode 600a and prevent the cylindrical lower electrode 600a from tilting.

Referring to fig. 4f, a metal oxide layer 600b is fully deposited on the substrate 100, and the metal oxide layer 600b covers the insulation pattern 400a and conformally covers the exposed surface of the cylindrical lower electrode 600 a. As shown in fig. 4f, the metal oxide layer 600b covers the upper surface of the cylindrical lower electrode 600a in the second opening 500e, the upper surface of the insulating pattern 400a in the third opening 500f, and extends to cover the upper surface of the second support structure 510b, and at the same time, the metal oxide layer 600b also covers the lower surface of the second support structure 510b, the upper and lower surfaces of the first support structure 510a, and the surface of the insulating pattern 400a covered by the first support structure 510a and the second support structure 510 b. It is alternatively understood that the metal oxide layer 600b includes a first portion similar to a square wave pattern covering the inner surface of the cylindrical lower electrode 600a, the upper surface of the second support structure 510b, and a portion of the upper surface of the insulation pattern 400a, and a second portion similar to a rectangle covering the upper portion of the outer surface of the cylindrical lower electrode 600a, the lower surface of the second support structure 510b, and the upper surface of the first support structure 510a, and the remaining second portion covering the lower portion of the outer surface of the cylindrical lower electrode 600a, the lower surface of the first support structure 510a, and a portion of the surface of the insulation pattern 400 a.

Referring to fig. 4f, in the present embodiment, since the surface of the insulation pattern 400a has a recess, and a deposition process with poor trench filling capability is adopted when forming the metal oxide layer 600b, the formed metal oxide layer 600b only covers the recess opening, so as to form an air gap G1 between the metal oxide layer 600b and the insulation pattern 400 a. Of course, a deposition process with better trench filling capability may be used to form the metal oxide layer 600b, but the reaction speed is increased by controlling the process parameters, so that the formed metal oxide layer 600b only covers the recess opening, thereby forming the air gap G1. Further, the metal oxide layer 600b may also extend into the recess, filling the upper portion of the recess, and forming an air gap as long as the recess is not filled.

Referring to fig. 4g, an upper electrode 600c is formed on the metal oxide layer 600b, and the upper electrode 600c covers a portion of the upper surface of the metal oxide layer 600b and fills the second opening 500e and the third opening 500f, but not limited thereto. At least a portion of the metal oxide layer 600b is located between the cylindrical lower electrode 600a and the cylindrical upper electrode 600c to form the capacitor structure 600, and a portion of the capacitor structure 600 may be located on the node contact structure 300b, but not limited thereto. In some embodiments, the cylindrical lower electrode 600a and the cylindrical upper electrode 600c can be regarded as the lower electrode and the upper electrode 600c in the capacitor structure 600, but not limited thereto.

It is understood that the material of the cylindrical lower electrode 600a may include impurity-doped silicon, metal such as tungsten or copper, and/or conductive metal compound such as titanium nitride, and the material of the upper electrode 600c may include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba, Sr) RuO), cro (catuo), bauro, La (Sr, Co) O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof, but is not limited thereto. The metal oxide layer 600b may be any suitable high dielectric constant dielectric layer, such as TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba, Sr) TiO), sto (srtio), bto (batio), PZT (Pb (Zr, Ti) O), (Pb, La) (Zr, Ti) O, Ba (Zr, Ti) O, Sr (Zr, Ti) O, or combinations thereof.

It is conceivable that a polishing process is inevitably used in forming the stacked material layer 500, the cylindrical lower electrode 600a and/or the upper electrode 600c, so that even after the insulating material layer 400 is formed as shown in fig. 3d, the surface of the substrate 100 has an uneven profile, and the surface of the substrate 100 can be completely planarized by a polishing process used in a subsequent process, so that the step of removing the insulating material layer 400 having a partial thickness by polishing and re-forming a mask material layer is omitted in the present embodiment, which does not affect the performance of the memory at all, simplifies the manufacturing process of the memory, and improves the manufacturing efficiency.

Example two

As shown in fig. 5a or 5b, unlike the first embodiment, in the present embodiment, the metal oxide layer 600b fills the recess of a partial depth, thereby forming an air gap G2 between the metal oxide layer 600b and the insulation pattern 400 a. That is, the bottom of the metal oxide layer 600b extends from the top of the insulation pattern 400a into the first opening such that the bottom of the metal oxide layer 600b is lower than the top of the insulation pattern 400 a.

Specifically, referring to fig. 5a, when the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulation pattern 400a, but also completely fills the recess with a partial depth. Referring to fig. 5b, when the metal oxide layer 600b is formed to cover a portion of the insulation pattern 400a, the metal oxide layer 600b not only covers the insulation pattern 400a but also fills the recess portion with a partial depth. Thus, the upper portion of the recess is filled with the medium, and the remaining portion of the recess constitutes an air gap G2.

The method for forming the memory in this embodiment may be the same as the method for forming the memory in the first embodiment except that the first oxide layer 500a and the metal oxide layer 600b are formed such that the first oxide layer 500a and the metal oxide layer 600b fill the recess with a partial depth.

In this embodiment, the first oxide layer 500a and the metal oxide layer 600b are filled in the recess by controlling the process parameters for preparing the first oxide layer 500a and the metal oxide layer 600 b. For example, the first oxide layer 500a and the metal oxide layer 600b are formed by a deposition process with better trench filling capability, or the speed of the deposition process for preparing the first oxide layer 500a and the metal oxide layer 600b is reduced, and after the first oxide layer 500a and the metal oxide layer 600b fill the recess with a partial depth, the reaction is stopped immediately, so that the recess is not completely filled, and the remaining recess forms the air gap G2.

It should be understood that the present embodiment is not limited to the first oxide layer 500a and the metal oxide layer 600b both filling the recess, the first oxide layer 500a may also fill the recess or only cover the recess, and the metal oxide layer 600b fills the recess with a partial depth.

EXAMPLE III

As shown in fig. 6a or 6b, unlike both the first and second embodiments, in the present embodiment, the metal oxide layer 600b completely fills the recess, so that no air gap is formed between the metal oxide layer 600b and the insulation pattern 400 a.

Specifically, referring to fig. 6a, when the first oxide layer 500a is formed, the first oxide layer 500a not only covers the insulation pattern 400a, but also completely fills the recess. Referring to fig. 6b, when the metal oxide layer 600b is formed to cover a portion of the insulation pattern 400a, the metal oxide layer 600b not only covers the insulation pattern 400a but also completely fills the recess. In this way, the recesses are filled with the medium, so that no air gaps are present.

The method for forming the memory in this embodiment may be the same as the method for forming the memory in the first embodiment except that the first oxide layer 500a and the metal oxide layer 600b are formed such that the first oxide layer 500a and the metal oxide layer 600b fill the recess.

In this embodiment, the first oxide layer 500a and the metal oxide layer 600b are filled in the recess by controlling the process parameters for preparing the first oxide layer 500a and the metal oxide layer 600 b. For example, the first oxide layer 500a and the metal oxide layer 600b are formed by a deposition process with better trench filling capability, or the speed of the deposition process for preparing the first oxide layer 500a and the metal oxide layer 600b is reduced, so that the first oxide layer 500a and the metal oxide layer 600b can better fill the recess.

It should be understood that the present embodiment is not limited to the first oxide layer 500a and the metal oxide layer 600b both filling the recess, the first oxide layer 500a may also fill a part of the depth of the recess or only cover the recess, and the metal oxide layer 600b fills the recess.

In summary, in the memory and the forming method thereof provided by the present invention, the insulating pattern covers at least the sidewall of the first opening of the spaced node contact structure and extends upward to be higher than the node contact structure, and the upper surface of the insulating pattern is further recessed into the first opening to form a recessed portion, so that the existing insulating pattern formed by two film layers can be replaced by one film layer, thereby omitting the steps of grinding and removing the insulating material layer with a partial thickness and re-forming the mask material layer, simplifying the manufacturing process of the memory, improving the manufacturing efficiency, and because the surface of the substrate is usually planarized by adopting a multiple grinding process when forming the capacitor structure, the performance of the memory is not affected.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory, comprising:

a substrate;

a plurality of node contact structures extending upwardly from the substrate;

a capacitor structure located on the node contact structure and electrically connected to the node contact structure;

the material of the insulation pattern is nitride, carbide or oxide.

2. The memory of claim 1, wherein the capacitive structure comprises:

and a metal oxide layer at least partially on the insulation pattern.

3. The memory of claim 2, wherein the metal oxide layer covers an opening of the recess to form an air gap; alternatively, the metal oxide layer fills a partial depth recess to form an air gap.

4. The memory of claim 2, wherein the metal oxide layer completely fills the recess.

5. The memory of any of claims 1-4, wherein the insulating pattern further extends to cover a top portion of the node contact structures.

6. The memory of claim 1, wherein the node contact structure is divided into an upper node contact and a lower node contact bounded by a height position of a bottom of the first opening, a maximum width dimension of the upper node contact being greater than a maximum width dimension of the lower node contact in a direction perpendicular to the height direction.

7. A method for forming a memory, comprising:

providing a substrate;

8. The method of forming a memory device according to claim 7, wherein the step of forming the insulating pattern includes:

9. The method of claim 8, wherein the step of forming a capacitor structure on each of the node contact structures comprises:

10. The method of claim 9, wherein the metal oxide layer covers the opening of the recess to form an air gap; or the metal oxide layer fills the recess part of the depth to form an air gap; alternatively, the metal oxide layer completely fills the recess.