CN111463130A - Power semiconductor device and method of forming a power semiconductor device - Google Patents

Power semiconductor device and method of forming a power semiconductor device Download PDF

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Publication number
CN111463130A
CN111463130A CN202010052976.9A CN202010052976A CN111463130A CN 111463130 A CN111463130 A CN 111463130A CN 202010052976 A CN202010052976 A CN 202010052976A CN 111463130 A CN111463130 A CN 111463130A
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region
semiconductor body
recessed
regions
raised source
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Inventor
E.格里布尔
M.贝宁格-比纳
M.戴内泽
I.迪恩施托费尔
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Infineon Technologies Dresden GmbH and Co KG
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Infineon Technologies Dresden GmbH and Co KG
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

A method of forming a power semiconductor device includes providing a semiconductor body; providing a control electrode arranged on or in the semiconductor body; forming a plurality of raised source regions of the first conductivity type in the semiconductor body adjacent the control electrode, the forming of the raised source regions comprising: implanting a dopant of a first conductivity type into the semiconductor body; forming a recessed mask layer on a surface of the semiconductor body; and removing portions of the semiconductor body not covered by the recessed mask layer by a first etch process to form raised source regions and recessed body regions adjacent the raised source regions, the recessed body regions being disposed between the raised source regions. The method further includes forming a dielectric layer on the surface of the semiconductor body; forming a contact hole mask layer on the dielectric layer; removing a portion of the dielectric layer not covered by the contact hole mask layer by a second etching process to form a contact hole; and filling the contact holes with a conductive material to establish electrical contact with at least a portion of the raised source regions and at least a portion of the recessed body regions.

Description

Power semiconductor device and method of forming a power semiconductor device
Technical Field
The present description relates to embodiments of a method of forming a power semiconductor device and embodiments of a power semiconductor device. In particular, the present description relates to aspects of a process of forming an elevated source region of a power semiconductor device and to a corresponding device.
Background
Many functions of modern equipment in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor switches. For example, Insulated Gate Bipolar Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to power converters and switches in power supplies, to name a few.
A power semiconductor device typically includes a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. Further, in a power semiconductor device having a transistor configuration, the load current path may be controlled by an insulated control electrode sometimes referred to as a gate electrode. For example, the control electrode may set the power semiconductor device in one of a conducting state and a blocking state by selectively opening or closing a conducting channel for a load current upon receiving a corresponding control signal from, for example, a driver unit. A conductive channel is typically formed in the body region adjacent to the insulated control electrode and connects the source region separated by the body region with the drift region. In some cases, the gate electrode may be included within a trench of the power semiconductor switch, where the trench may assume, for example, a stripe configuration or a needle configuration.
It is generally desirable to ensure high reliability of power semiconductor devices. For example, it is desirable to provide a certain robustness of the power semiconductor transistor with respect to latch-up induced damage. For example, it is therefore desirable to provide a method of forming reliable source and/or body contact regions and a corresponding power semiconductor device.
Disclosure of Invention
According to one embodiment, a method of forming a power semiconductor device includes: providing a semiconductor body having a surface; providing a control electrode arranged at least partially on or inside the semiconductor body and configured to control a load current in the semiconductor body; forming a plurality of raised source regions of the first conductivity type in the semiconductor body adjacent to the control electrode, wherein forming the raised source regions comprises at least the steps of: implanting dopants of a first conductivity type into the semiconductor body; forming a recess mask layer on the surface of the semiconductor body, wherein the recess mask layer covers at least the region of the intended source region; and removing portions of the semiconductor body not covered by the recessed mask layer by a first etch process to form raised source regions and recessed body regions adjacent to the raised source regions, wherein the recessed body regions are at least partially disposed between the raised source regions. The method further comprises the following steps: forming a dielectric layer on a surface of the semiconductor body; forming a contact hole mask layer on the dielectric layer; removing the part of the dielectric layer which is not covered by the contact hole mask layer through a second etching process so as to form a contact hole; and at least partially filling the contact hole with a conductive material so as to establish electrical contact with at least a portion of the raised source region and at least a portion of the recessed body region.
It should be noted that in some embodiments, the aforementioned steps involving the recess masking layer and the steps involving the contact hole masking layer may also be performed in the reverse order, i.e., in some embodiments, the contact holes may be formed prior to forming the raised source regions and the recessed body regions by the first etch process.
According to another embodiment, a power semiconductor device is presented. The power semiconductor device includes:
-a semiconductor body having a surface;
-a control electrode arranged at least partially on or inside the semiconductor body and configured to control a load current in the semiconductor body;
-a plurality of raised source regions of a first conductivity type arranged in the semiconductor body adjacent to the control electrode;
-a plurality of recessed body regions arranged adjacent to the raised source regions; and
-a dielectric layer arranged on a portion of the semiconductor body surface and defining a contact hole, the contact hole being at least partially filled with a conductive material establishing an electrical contact with at least a portion of the raised source region and at least a portion of the recessed body region;
wherein at least one first contact surface between the at least one of the raised source regions and the dielectric layer extends in a first horizontal plane and at least one second contact surface between the at least one of the recessed body regions and the dielectric layer substantially extends in a second horizontal plane, the second horizontal plane being located vertically below the first horizontal plane.
According to another embodiment, a power semiconductor device includes:
-a semiconductor body having a surface;
-a control trench extending from the surface in a vertical direction into the semiconductor body;
-a control electrode arranged at least partially within the control trench and configured to control a load current in the semiconductor body;
-at least two raised source regions of a first conductivity type arranged in the semiconductor body adjacent to the control electrode;
-a recessed body region of a second conductivity type arranged adjacent to and extending at least partially between the raised source regions; and
-a conductive layer arranged on top of the semiconductor body and establishing electrical contact with at least a part of the raised source region and at least a part of the recessed body region;
wherein at least one third contact surface between at least one of the raised source regions and the conductive layer extends substantially in a third horizontal plane and a fourth contact surface between the recessed body region and the conductive layer extends substantially in a fourth horizontal plane, the fourth horizontal plane being located vertically below the third horizontal plane.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
Drawings
The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. In the drawings:
FIGS. 1 (a) - (f) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments;
2 (a) - (f) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments;
FIGS. 3 (a) - (f) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments;
FIGS. 4 (a) - (f) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments;
FIGS. 5 (a) - (f) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments;
fig. 6 schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;
fig. 7A schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;
fig. 7B schematically and exemplarily shows a portion of a horizontal cross section of the power semiconductor device according to the embodiment of fig. 7A;
fig. 8 schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments; and
fig. 9 (a) - (c) schematically and exemplarily show stages of a semiconductor device processing method according to one or more embodiments.
Detailed Description
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.
In this regard, directional terminology, such as "top," "bottom," "below," "front," "back," "head," "tail," "up," etc., may be used with reference to the orientation of the figure(s) being described. Because portions of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to the various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For instance, features illustrated or described as part of one embodiment, can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The figures are not drawn to scale and are for illustrative purposes only. For clarity, identical elements or manufacturing steps are denoted by the same reference numerals in different figures, if not otherwise specified.
The term "horizontal" as used in this specification intends to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, the surface of a semiconductor wafer or die or chip. For example, the first transverse direction X and the second transverse direction Y described below may each be a horizontal direction, wherein the first transverse direction X and the second transverse direction Y may be perpendicular to each other.
The term "vertical" as used in this specification intends to describe an orientation arranged substantially perpendicular to a horizontal surface, i.e. parallel to the normal direction of the surface of the semiconductor wafer/chip/die. For example, the extension direction Z mentioned below may be an extension direction perpendicular to both the first lateral direction X and the second lateral direction Y. The direction of extension Z is also referred to herein as the "vertical direction Z".
In this specification, n-doping is referred to as "first conductivity type", and p-doping is referred to as "second conductivity type". Alternatively, the opposite doping relationship may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.
In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmic connection" and "electrical connection" are intended to describe the presence of a low ohmic electrical connection or a low ohmic current path between two regions, portions, zones, portions or components of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a portion or part of a semiconductor device. Furthermore, in the context of the present specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, and the like.
Furthermore, in the context of the present specification, the term "electrically isolated" is used in the context of its generally valid understanding, if not otherwise stated, and is therefore intended to describe that two or more components are located apart from each other and that there is no ohmic connection connecting these components. However, components that are electrically isolated from each other may still be coupled to each other, e.g. mechanically and/or capacitively and/or inductively. To give an example, the two electrodes of the capacitor may be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, e.g. by an insulator such as a dielectric.
The specific embodiments described in this specification relate to, but are not limited to, power semiconductor switches in a strip cell or cell configuration, such as power semiconductor devices that may be used within a power converter or power supply. Thus, in one embodiment, such a device may be configured to carry a load current to be fed to a load and/or (or) provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor cells, such as monolithically integrated diode cells (e.g. monolithically integrated cells of two anti-series connected diodes), monolithically integrated transistor cells (e.g. monolithically integrated IGBT cells and/or derivatives thereof). Such a diode/transistor cell may be integrated in a power semiconductor module. A plurality of such cells may constitute a cell field arranged together with an active region of the power semiconductor device.
The term "power semiconductor device" as used in this specification intends to describe a semiconductor device on a single chip with high voltage blocking and/or high current carrying capability. In other words, such power semiconductor devices are intended for high currents (typically in the ampere range, e.g. up to several tens or hundreds of amperes) and/or high voltages (typically above 15V, more typically 100V and above, e.g. up to at least 500V or even higher, e.g. up to at least 6 kV or higher).
For example, the power semiconductor devices described below may be semiconductor devices exhibiting a stripe cell configuration or a honeycomb (pillar/pin) cell configuration, and may be configured to be used as power components in low, medium, and/or high voltage applications.
For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and/or other types of semiconductor-based data processing.
Fig. 1 (a) - (f) schematically and exemplarily show stages of a power semiconductor device processing method according to one or more embodiments. In each of fig. 1 (a) - (f), the left figure shows a portion of a vertical cross section of the power semiconductor device 1 produced at a respective processing stage, while the right figure shows a corresponding top view of the power semiconductor device 1.
As shown in fig. 1 (a), a semiconductor body 10 having a surface 100 is provided, for example in the form of a wafer. At the processing stage shown in fig. 1 (a), the semiconductor body 10 may have been subjected to several processing steps, which are known in principle to a person skilled in the art and therefore will not be described in detail here. For example, a plurality of trenches 14, 15 may be formed, for example by an etching process, extending from the surface 100 into the semiconductor body 10 in the vertical direction Z. Further, respective trench insulation structures 142, 152, such as oxide, may be formed within the trenches 14, 15, and the trenches 14, 15 are filled with a conductive material, such as polysilicon, so as to form the trench electrodes 141, 151.
In the present exemplary embodiment, a control trench 14 is provided, wherein the control trench 14 comprises a control electrode 141 (also referred to as gate electrode) configured for controlling a load current in the semiconductor body 10 in dependence on a control signal. For example, in the power semiconductor device 1 being processed, the control electrode 141 may be electrically connected with a control terminal structure (not shown) configured to receive a control signal from outside the power semiconductor device 1, as is known in principle in the art.
Furthermore, a source trench 15 is provided on each side of the control trench 14, such that two trench sidewalls 144, 154 of two adjacent trenches 14, 15 facing each other laterally define a mesa region 105 of the semiconductor body 10 in the first lateral direction X. The source trenches 15 comprise in each case a source electrode 151. For example, in the power semiconductor device 1 to be processed, the source electrode 151 may be electrically connected with the first load terminal structure 11 (see, for example, fig. 6). For example, the first load terminal structure 11 may be a source terminal structure in case the power semiconductor device 1 is or comprises a MOSFET, or the first load terminal structure 11 may be an emitter terminal structure in case the power semiconductor device 1 is or comprises an IGBT.
It should be noted that fig. 1 (a) - (f) only show a small part of the semiconductor body 10 and, in practice, there may also be provided a plurality of such control trenches 14 and/or source trenches 15, which may be arranged in various combinations and patterns (i.e. which determine whether the electrodes 141, 151 are connected to the control terminal structure or to the first load terminal structure 11, according to various so-called contact schemes).
For example, in some embodiments, the two trench sidewalls 144, 154 of respective adjacent control trenches 14 and/or source trenches 15 may be spaced apart from each other along the first lateral direction X by at most 5 μm, such as at most 2 μm, at most 1 μm, at most 600 nm, or only at most 200 nm.
As further shown in fig. 1 (a), one or more body regions 102 of a second conductivity type (e.g. p-type) may have been formed in the semiconductor body 10, for example by a first implantation of a dopant of the second conductivity type through the semiconductor body surface 100. Such a body implant may be performed, for example, as an unmasked implant of dopants of the second conductivity type. Exemplary dopant atoms/molecules of the second conductivity type that may be suitable for bulk implantation include boron, aluminum, gallium, indium, and composite molecules of these species. For example, boron difluoride (BF)2) Or other boron-fluorine compounds (BF)x) May be used as a dopant of the second conductivity type. The implant dose for the body implant may be, for example, 1E11 cm-2To 1E16 cm-2Is selected within the range of (1).
For example, the first implant may be performed by a relatively thin stray oxide 7 disposed on the surface, as is well known in the art (see fig. 1 (a)). In the right drawing of fig. 1 (a), the stray oxide 7 is not shown.
In the present exemplary embodiment, a respective body region 102 is formed in each mesa region 105, wherein the body region 102 extends laterally throughout the entire mesa region 105. For example, a first implantation of dopants of the second conductivity type may be followed by a diffusion step (e.g. at elevated temperature) in order to extend the body region 102 from the surface 100 further into the semiconductor body 10. This may result, for example, in the body region 102 extending downward from the surface 100 along the vertical direction Z to a diffusion depth in the range of 0.4 μm to 3 μm.
It should be noted that the formation of the body region 102 as described above may also be achieved at a later processing stage.
In the right diagram of fig. 1 (a), the dashed line marks the region 104-1 of the intended source region. In other words, a region of the first conductivity type which may be used as source region 104 of power semiconductor device 1 will be formed in particular in the portion located within mesa region 105 in the region defined by the dashed line and trench sidewalls 144 of control trench 14.
As shown in the figure, in a top view of the semiconductor body surface 100, it is contemplated that the regions 104-1 of the source regions may be distributed along the control trenches 14, for example according to a regular pattern. Furthermore, said regions 104-1 may be spaced apart from each other along a main lateral extension direction of the control trench 14, which direction is in this embodiment the second lateral direction Y.
In the exemplary embodiment shown in fig. 1 (a), it is contemplated that the region 104-1 of source regions comprises a plurality of island-shaped source regions covering only a portion of the mesa 105. For example, the island-shaped source regions may be substantially rectangular as shown in fig. 1 (a), wherein it is understood that the corners of the rectangular islands may be rounded to some extent during subsequent processing. In other embodiments, it is contemplated that the region 104-1 of the source region may instead take the form of, for example, a rectangular source bar extending continuously through the plurality of mesa regions 105, wherein again, the corners of the rectangular source bar may be somewhat rounded during subsequent processing. This will be explained in further detail below with reference to fig. 4 (a) - (f).
In an embodiment, it is contemplated that the extension L Y of the region 104-1 of the source region along the main lateral extension direction Y of the control trench 14 may amount to at most 5 μm, such as at most 2 μm, or even only at most 1 μm, for example, said extension L Y is measured at the trench sidewalls 144, i.e. at the location where the respective region 104-1 is in contact with the control trench 14.
Hereinafter, a process of forming a plurality of raised source regions 104 in said region 104-1 of intended source regions will be explained with reference to fig. 1 (b) -1 (f).
The left diagram of fig. 1 (b) schematically shows the formation of a source implant region 104-2 in the semiconductor body 10. For this purpose, an implantation mask layer 4 may be arranged at the semiconductor body surface 100. The implantation mask layer 4 is or comprises, for example, a structured resist layer.
Then, dopants of the first conductivity type (e.g. n-type) can be implanted in the semiconductor body 10 in the region in which the implantation mask layer 4 exposes the semiconductor body surface 100. For example, the implantation mask layer 4 exposes at least the region 104-1 of the intended source region 104. According to the present exemplary embodiment, the implantation mask layer 4 may expose a relatively large connection surface (including the several trenches 14, 15 and mesa regions 105). In other embodiments, the implantation mask layer 4 may have a plurality of smaller openings, including the region 104-1 of the intended source region, as will be explained further below with reference to, for example, fig. 2 (b).
Exemplary dopant atoms of the first conductivity type that may be suitable for this source implant step include arsenic, phosphorous, antimony, selenium and hydrogen. For example, the source implant may be at 1E13cm-2To 1E17 cm-2At a dopant dose or doses in the range, such as for example at 6E15 cm-2Or 8E15 cm-2Is performed at a single dose. Furthermore, a relatively low implantation energy may be applied, such as an implantation energy in the range of 1 keV to 100 keV (e.g., 30 keV). For example, the above-mentioned stray oxide may still be arranged on the semiconductor body surface 100 during the source implantation and may only be removed afterwards.
The right diagram of fig. 1 (b) shows a top view of the semiconductor surface 100 after the source implant step and before the resist strip, i.e. before removal of the implanted mask layer 4. Thus, fig. 1 (b) shows a relatively large connected source implant region 104-2 extending in two mesa regions 105, which is still covered by the mask layer 104. In fig. 1 (b) and the following drawings, the hatched area marks a region including the dopant of the first conductivity type implanted in the source implantation step.
As a next processing step, fig. 1 (c) shows the formation of a recessed mask layer 2 on the semiconductor body surface 100 after removal of the implantation mask layer 4. The recessed mask layer 2 may be provided, for example in the form of a structured resist layer 2, which may cover at least the region 104-1 of the intended source region (see the right image of fig. 1 (c)).
Then, portions of the semiconductor body 10 not covered by the recessed mask layer 2 may be removed by a first etching process, thereby forming a plurality of raised source regions 104 and recessed body regions 1021 adjacent to the raised source regions 104 within the mesa region 105, wherein the recessed body regions 1021 are at least partially arranged between the raised source regions 104 (see the right image of fig. 1 (d)). In other words, when moving from one raised source region 104 to an adjacent raised source region 104 (arranged adjacent to the same trench 14), it passes through the recessed body region 1021. Raised source regions 104 abut trench sidewalls 144 of control trenches 14. A recessed body region 1021 is included in body region 102. Thus, the recessed mask layer 2 defines the lateral position and lateral extension of the intended source region 104-1 (e.g. in the form of a regular source region pattern as shown in the right-hand drawing of fig. 1 (a)), and the portion of the source implant region 104-2 that laterally extends beyond the region 104-1 of the intended source region is then removed during the first etch process. In other words, in order to form the raised source regions 104, some parts of the semiconductor body 10 are "sacrificed". Accordingly, the first etching process may also be referred to as a "sacrificial etching process".
The result of this first etching process is schematically shown in fig. 1 (d), wherein the recessed mask layer 2 has been removed, i.e. resist stripping has been achieved. For example, as a result of the first etch process, the semiconductor surface 100 may exhibit a step S (see also fig. 6) at a lateral transition between each raised source region 104 and an adjacent recessed body region 1021. For example, the cross-section of the step S may be substantially vertical, as schematically shown in each of fig. 1 (d) and 6. In other embodiments, the cross-section of the step may be less steep and may, for example, be inclined with respect to the vertical direction Z. The step S, as shown for example in the left hand drawing in fig. 1 (d) and in fig. 6, extends parallel to the second lateral direction Y, i.e. along the main lateral extension direction Y of the grooves 14, 15. It should be noted, however, that similar steps may also be formed at the lateral transitions between the raised source regions 104 and the portions of the adjacent recessed body regions 1021 extending between the raised source regions 104 (not visible in fig. 1 (d) and 6). Correspondingly, such steps may not extend parallel, but for example extend substantially orthogonal to the main transverse direction of extension Y of the trenches 14, 15. For example, such steps may extend substantially along the first transverse direction X.
In other words, the first etch process may result in at least two different mesa heights of the mesa region 105, wherein the raised source regions 104 are located in portions of the mesa 105 having a higher mesa height compared to the adjacent recessed body region 1021. Further details of the lateral transition between the raised source regions 104 and the adjacent recessed body regions 1021 will be described further below with reference to fig. 6.
In one embodiment, the first etching process is performed in such a way that the portions of the semiconductor body 10 not covered by the recessed mask layer 2 are etched away at least down to an etch depth corresponding to the projected extent of the source implant. In this context, it should be noted that the portion of the source implant region 104-2 does not necessarily need to be completely removed during the first etch process. Instead, it may be sufficient if the portion is mostly removed, i.e. at least up to some residual end-of-range dopant concentration that may lie below the projected range of the source implant. For example, in one embodiment, such residual end-of-range dopants of the first conductivity type may be subsequently over-doped by a second implantation of dopants of the second conductivity type. This will be explained in more detail below.
For example, in an embodiment, the portions of the semiconductor body 10 not covered by the recessed mask layer 2 are etched away at least down to an etch depth of at least 10 nm (such as at least 25 nm, 50 nm or even at least 250 nm) below the semiconductor body surface 100.
For example, the first etching process may be an anisotropic etching process, which may be substantially oriented along the vertical direction Z. In another embodiment, the first etching process may be performed as an isotropic etching process.
According to one embodiment, a temperature annealing step may be performed after the first etching process. It should be noted that one or more additional steps, such as the deposition of glass, may be performed between the first etching process and the temperature annealing step. For example, the temperature annealing step may be performed at a temperature in the range of 800 ℃ to 1100 ℃ and for a duration in the range of 1 second to several hours (such as, for example, 4 hours). As a result of the temperature step, the implanted dopants of the first conductivity type may diffuse further into the semiconductor body 10, resulting in a larger vertical extension of the raised source regions 104. For example, the vertical extension of the raised source regions 104 after the temperature anneal step may be larger than the step S, as schematically shown in each of fig. 1 (d) and 6, for example.
As previously mentioned, said first implantation of dopants of the second conductivity type forming the body region 102 may also be performed at a subsequent processing stage, i.e. for example after the source implantation and even after the first etching process. However, in one embodiment, said first implantation of dopants of the second conductivity type to form the body region 102 is performed (at the latest) before the temperature annealing step of the raised source region 104 as described above is affected.
Further, in one embodiment, a second implantation of dopants of the second conductivity type may be performed after the first etching process. For example, dopants of the second conductivity type may thus be implanted at least into a portion of the recessed body region 1021. In an embodiment, during said second implantation step, dopants of the second conductivity type are implanted at least in the portions of the semiconductor body 10 not covered by the recessed mask layer 2, i.e. the second implantation step may be performed before the recessed mask 2 is stripped. Alternatively, the second implantation may be performed after the removal of the recess mask 2.
For example, potential residual dopants of the first conductivity type that may originate from the source implant step may be over-doped by a second implant of dopants of the second conductivity type. For example, as described above, some residual end-of-range dopant concentration may be located below the projected range of the source implant. Correspondingly, relatively low dopant doses (such as, for example, at 1E13 cm)-2To 5E15 cm-2In) may be sufficient to over-dope the residual dopants of the first conductivity type by a second implantation of dopants of the second conductivity type. For example, in one embodiment, during the second implantation step, may be performed, for example, at 1E15 cm-2Dose implanting boron atoms or BF2A molecule. For example, implantation energies in the range of 1 keV to 100 keV, such as, for example, 5 keV, may be applied. Furthermore, the second implantation of dopants of the second conductivity type may be performed without arranging a stray oxide on the semiconductor surface 100. In one embodiment, the second implantation of dopants of the second conductivity type is performed after the first etching process and before the above-described temperature annealing step.
Referring to fig. 1 (e), as a further processing step, a dielectric layer 18, such as an oxide layer, may be formed on the semiconductor body surface 100. For example, in one embodiment, the dielectric layer 18 may cover at least the raised source regions 104 and the recessed body regions 1021.
A contact hole mask layer (not shown) may then be formed on dielectric layer 18. The contact hole mask layer may be structured to define a contact hole region, for example, over one or more mesa regions 105.
Then, the portion of the dielectric layer 18 not covered by the contact hole mask layer may be removed by a second etching process to form at least one contact hole 185. For example, in one embodiment, a plurality of contact holes 185 may thus be formed, such as at least one contact hole 185 per active mesa 105. The result of this second etching process is schematically shown in fig. 1 (e). For example, in the embodiment according to fig. 1 (e), the contact hole 185 may expose at least a portion of the raised source region 104 and at least a portion of the recessed body region 1021. In another embodiment, one large contact hole may be provided exposing a plurality of mesa regions 105, such as the entirety of the active cell field of the power semiconductor device 1, as will be explained in further detail below with reference to fig. 5 (f).
Fig. 1 (f) shows a stage of processing after filling the contact 185 holes with a conductive material 111, such as a metal. The conductive material 111 establishes electrical contact with a portion of the raised source regions 104 and a portion of the recessed body regions 1021. For example, the conductive material 111 filling the contact hole 185 may form part of the first load terminal structure 11, such as for example the front side metallization of the power semiconductor device 1.
Fig. 2 (a) - (f) schematically show process stages of a variant of the power semiconductor device forming method explained above with reference to fig. 1 (a) - (f). Differences occur with respect to the implantation mask layer 4 for the source implantation. As schematically shown in fig. 2 (b), in this embodiment the implantation mask layer 4 exposes at least a region 104-1 of the intended source region, but covers at least a portion of the semiconductor body 10, i.e. such a portion of the body region 1021 in which the recess is to be formed. The implantation mask layer 4 has a plurality of openings including regions 104-1 of the intended source regions. In the present exemplary embodiment, the opening has an island shape (e.g., a substantially rectangular shape, optionally with rounded corners) and is slightly larger than the region 104-1 of the intended source region. Accordingly, a plurality of rectangular source implant regions 104-2 slightly larger than the region 104-1 of the intended source region are formed, as shown in the right drawing of fig. 2 (b). In another embodiment, not shown in the figures, the opening in the implantation mask layer 4 may be slightly smaller than the region 104-1 of the intended source region. The subsequent processing steps shown in fig. 2 (c) - (f) are completely similar to the steps explained above with reference to fig. 1 (c) - (f).
Fig. 3 (a) - (f) schematically show a further variant of the power semiconductor formation method, in which the implantation mask layer 4 for the source implantation has a plurality of openings in the form of rectangular strips extending in each case over several trenches 14, 15 and mesa regions 15, see fig. 3 (b). The subsequent processing steps shown in fig. 3 (c) - (f) are completely similar to the steps explained above with reference to fig. 1 (c) - (f).
Fig. 4 (a) - (f) schematically illustrate yet another variation of the power semiconductor forming method. As shown in fig. 4 (b), the present exemplary embodiment uses a source implant mask layer 4 similar to or the same as the source implant mask layer of fig. 3 (b). However, a difference occurs with respect to the region 104-1 of the intended source region. As shown in fig. 4 (a) (right drawing), it is contemplated that the region 104-1 of the source region may instead take the form of a rectangular source strip extending continuously through the plurality of mesa regions 105. For example, as illustrated, it is contemplated that rectangular source bars may be oriented transverse (such as, for example, orthogonal) to the trenches 14, 15 and mesas 105. As shown in fig. 4 (c), the recessed mask layer 2 further includes a plurality of such extension bars corresponding to the region 104-1 of the intended source region. The further processing steps shown in fig. 4 (d) - (f) are completely similar to the steps explained above with reference to fig. 1 (d) - (f).
Fig. 5 (a) - (f) schematically and exemplarily show stages of a further semiconductor device processing method according to one or more embodiments.
Initially, as shown in fig. 5 (a) and similar to what was explained above with reference to fig. 1 (a), a plurality of trenches 14, 15 extending from the surface 100 in the vertical direction Z into the semiconductor body 10 are formed, for example by an etching process. Further, respective trench insulation structures 142, 152, such as oxide, may be formed within the trenches 14, 15, and the trenches 14, 15 are filled with a conductive material, such as polysilicon, so as to form the trench electrodes 141, 151.
Furthermore, in this exemplary embodiment, an insulating cover layer 19 (or cap layer 19) is provided at least partially within the trenches 14, 15 so as to close the trenches 14, 15 at the top. As shown in fig. 5 (a), the insulating cover layer 19 may be formed, for example, by depositing an oxide on top of the trench electrodes 141, 151 near the semiconductor surface. For example, a portion of the deposited oxide may be removed by a Chemical Mechanical Polishing (CMP) process. For example, a CMP process may be performed to remove the deposited oxide down to the semiconductor surface 100.
The left diagram of fig. 5 (b) schematically shows a processing stage after such a CMP processing step and after body conditioning, wherein a body implantation may be performed as explained above with reference to fig. 1 (a). The right diagram of fig. 5 (b) indicates a region 104-1 of the intended source region, which is similar (except for the presence of the insulating cap 19) to the region 104-1 of the intended source region depicted in fig. 2 (b), for example.
The further processing steps leading to the respective processing stages shown in fig. 5 (c) - (e) are similar to those of fig. 1 (b) - (d). Within this scope, reference is made to the above detailed explanation.
However, one difference occurs with respect to contact hole formation. In this embodiment, one large contact hole 185 exposing a plurality of entire mesa regions 105 (such as the entirety of the active cell field of the power semiconductor device 1) may be formed, for example, by forming a dielectric layer and then removing most of the dielectric layer above the active cell field. For example, only a peripheral portion of the dielectric layer, such as the portion located inside the edge termination region, may thus be retained thereon (not shown) and define the extended contact hole 185.
As a result of filling the contact hole 185 with a conductive material, fig. 5 (f) thus shows that a conductive layer 1111, such as for example a front metallization layer, is arranged on top of the mesa region 105 and establishes electrical contact with the raised source region 104 and the recessed body region 1021. Further details in this regard will be explained below with reference to fig. 8.
Fig. 6 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device 1 according to one or more embodiments. For example, the power semiconductor device 1 of fig. 6 may be produced by the method explained above with reference to, for example, fig. 1 (a) - (f). Actually, fig. 6 is an enlarged view of fig. 1 (f).
The power semiconductor device 1 of fig. 6 has a vertical power transistor configuration. For example, the power semiconductor device 1 may be or include at least one of an IGBT and a MOSFET. Fig. 6 depicts only a part of the power semiconductor device 1 near its front side, comprising two control units, wherein the control electrodes 141 are arranged in the control trenches 14. Further, two source trenches 15 are disposed adjacent to the control trench 14.
A plurality of raised source regions 104 of the first conductivity type are arranged in the semiconductor body 10 adjacent to the control electrode 141, as already explained above with regard to the formation method. Further, as described above, a plurality of recessed body regions 1021 is arranged adjacent to raised source regions 104.
A dielectric layer 18 is arranged on a portion of the semiconductor body surface 100 and defines contact holes 185 filled with a conductive material 111, which establish electrical contact with the raised source regions 104 and with the recessed body regions 1021.
As shown in fig. 6, the first contact surface 1048 between the raised source region 104 and the dielectric layer 18 extends in a first horizontal plane H1. Furthermore, the second contact surface 1028 between the recessed body region 1021 and the dielectric layer 18 extends substantially in a second level H2, wherein the second level H2 is located vertically below the first level H1. For example, the mesa 105 may thus exhibit at least two different mesa heights, which may be due to the above-mentioned first etching process, for example.
For example, the first vertical distance DZ1 between the first level H1 and the second level H2 amounts to at least 10 nm, such as at least 25 nm, at least 50 nm or even at least 250 nm additionally or as an alternative, the first vertical distance DZ1 may be smaller than the first vertical extension L Z1 of the source region 104 with the respective elevation of said contact surface 1048 of the dielectric layer 18.
As further shown in fig. 6, in some embodiments, the semiconductor body surface 100 may exhibit a substantially vertical step S at a lateral transition between each raised source region 104 and an adjacent recessed body region 1021, wherein the step S may be laterally spaced apart from a lateral boundary 185-1 of the contact hole 185. For example, the step S may be generated by the above-described first etching process.
Fig. 7A-B illustrate another exemplary embodiment of a power semiconductor device 1 formed by a forming method according to the present invention. In contrast to the above mentioned embodiments, the power semiconductor device 1 comprises vertical power transistor cells, each having a planar control electrode 141, as can best be seen in the vertical cross-sectional view of fig. 7A.
What has been explained above in relation to the formation of the raised source regions 104 and the recessed body regions 1021 arranged therebetween in the embodiment with trench cells applies analogously to the present exemplary embodiment with planar control electrodes 141. The horizontal cross section of fig. 7B shows an exemplary arrangement of the raised source regions 104 within the semiconductor body 10. For example, the raised source regions may be staggered along the main lateral extension direction Y of the planar control electrode 141, as depicted.
Fig. 8 schematically and exemplarily shows a part of a vertical cross section of a power semiconductor device 1 according to one or more further embodiments. For example, the power semiconductor device 1 of fig. 8 may be produced by the method explained above with reference to fig. 5 (a) - (f). Actually, fig. 8 is an enlarged view of the left drawing of fig. 5 (f). Therefore, the respective portions of the power semiconductor device 1 shown in fig. 8 have already been explained above with reference to fig. 5 (a) - (f), and will therefore not be explained here.
As shown in fig. 8, a third contact surface 1049 between the raised source region 104 and the conductive layer 1111 extends in a third horizontal plane H3. Furthermore, a fourth contact surface 1029 between the recessed body region 1021 and the conductive layer 1111 substantially extends in a fourth level H4, wherein the fourth level H4 is located vertically below the third level H3. For example, the mesa 105 may thus exhibit at least two different mesa heights, which may be due to the above-mentioned first etching process, for example. For example, the semiconductor body surface 100 may exhibit a step S (such as, for example, a substantially vertical step S or a slanted step) at a lateral transition between each raised source region 104 and an adjacent recessed body region 1021.
For example, the second vertical distance DZ2 between the third level H3 and the fourth level H4 amounts to at least 10 nm, such as at least 25 nm, at least 50 nm or even at least 250 nm additionally or as an alternative, the second vertical distance DZ2 may be smaller than the second vertical extension L Z2 with a correspondingly raised source region 104 with said third contact surface 1049 of the conductive layer 1111.
Fig. 9 schematically and exemplarily shows a further variant of the method according to the invention, in which the recessed mask layer 2 covers the control trench 14 along its longitudinal extension (at least in the active cell region). For example, a plurality of such control trenches 14 (not shown) may be provided, each covered by a recessed mask layer 2. For example, the processing stages depicted in fig. 9 (a) may correspond to the processing stages explained above with respect to fig. 2 (b). In a subsequent step, in contrast to fig. 2 (c), the recessed mask layer 2 is formed such that it also covers the control trench 14 (see the right drawing of fig. 9 (b)). The control trench 4 can thus be protected in further processing steps. For example, in one embodiment, all trenches including the electrode receiving the control signal may thus be protected by the recessed mask layer 2 during the first etch process. This is further illustrated in fig. 9 (c), which fig. 9 (c) shows the situation after the first etching process and before the removal of the recessed mask layer 2. In one embodiment, so-called dummy trenches may also be covered by respective portions of the recessed mask layer 2 and may thus be protected during a subsequent etching process.
Embodiments of the above-described method of forming a power semiconductor device correspond to the embodiments of the above-described power semiconductor device, and vice versa. Thus, for example, the features of the embodiments of the power semiconductor device described above may be realized by performing corresponding processing method steps.
The above embodiments include the following recognition: the reliability of the power semiconductor device, such as its robustness with respect to latch-up induced damage, may be significantly improved by a dedicated mask etch process that reliably defines the location and lateral extension of the source regions of the device.
In accordance with one or more embodiments, a plurality of raised source regions of the first conductivity type may be formed at a surface of the semiconductor body adjacent to the control electrode, wherein forming the raised source regions comprises:
-implanting dopants of a first conductivity type into the semiconductor body;
-forming a recess mask layer on the surface of the semiconductor body, wherein the recess mask layer covers at least the region of the intended source region; and
-removing portions of the semiconductor body not covered by the recessed mask layer by a first etching process to form the raised source regions and recessed body regions adjacent to the raised source regions.
By such a sacrificial etching process, defects in the form of source islands having an excessively large area can be corrected. Therefore, latch-up due to, for example, excessive width of the defective source islands can be avoided. In other words, the first etching process may provide a redundant measure of increasing the reliability of the power semiconductor devices being processed. For example, in some embodiments, as a result of this redundancy measure, two defects will need to occur independently at the same location of the semiconductor body surface that renders the device susceptible to destructive latch-up: i.e. defects in the structured source implant, e.g. source stripes or source islands, and defects in the structured sacrificial etch process according to the invention are defined. Therefore, the probability of failure can be effectively reduced by the proposed additional etching process.
In the above, embodiments relating to power semiconductor switches and corresponding processing methods are explained. These semiconductor devices are based on silicon (Si), for example. Thus, a single-crystal semiconductor region or layer (e.g., semiconductor body 10 and regions/zones thereof, such as regions, etc.) may be a single-crystal Si region or layer. In other embodiments, polysilicon or amorphous silicon may be used.
It should be understood, however, that the semiconductor body 10 and its regions/zones may be made of any semiconductor material suitable for the manufacture of semiconductor devices. Examples of such materials include, but are not limited to, base semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and cadmium mercury telluride (HgCdTe), to name a few. The above semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN) -aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) -gallium nitride (GaN), aluminum gallium nitride (AlGaN) -gallium nitride (GaN), indium gallium nitride (InGaN) -aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC 1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switching applications, Si, SiC, GaAs and GaN materials are mainly used at present.
Spatially relative terms, such as "below," "lower," "upper," "above," and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the various devices in addition to different orientations than those depicted in the figures. Furthermore, terms such as "first," "second," and the like, are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.
As used herein, the terms "having," "containing," "including," "presenting," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features.
In view of the above-described range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims (20)

1. A method of forming a power semiconductor device (1), comprising:
-providing a semiconductor body (10) having a surface (100);
-providing a control electrode (141) arranged at least partially on or inside the semiconductor body (10) and configured to control a load current in the semiconductor body (10);
-forming a plurality of raised source regions (104) of a first conductivity type in the semiconductor body (10) adjacent to the control electrode (141), wherein forming the raised source regions (104) comprises at least the steps of:
implanting dopants of a first conductivity type into the semiconductor body (10);
forming a recessed mask layer (2) on the surface (100) of the semiconductor body, wherein the recessed mask layer (2) covers at least a region (104-1) of an intended source region;
removing portions of the semiconductor body (10) not covered by the recessed mask layer (2) by a first etch process to form raised source regions (104) and recessed body regions (1021) adjacent to the raised source regions (104), wherein the recessed body regions (1021) are at least partially arranged between the raised source regions (104);
-forming a dielectric layer (18) on the semiconductor body surface (100);
-forming a contact hole mask layer on the dielectric layer (18);
-removing the portion of the dielectric layer (18) not covered by the contact hole mask layer by a second etching process to form a contact hole (185); and
-at least partially filling the contact hole (185) with a conductive material (111) so as to establish an electrical contact with at least a part of the raised source region (104) and at least a part of the recessed body region (1021).
2. The method of claim 1, wherein implanting dopants of said first conductivity type into said semiconductor body (10) comprises a mask implantation step using an implantation mask layer (4), said implantation mask layer (4) having a plurality of separate openings comprising at least a region (104-1) of said intended source region.
3. The method according to any of the preceding claims, further comprising a temperature annealing step performed after the first etching process.
4. A method according to claim 3, wherein during the etching process the portions of the semiconductor body (10) not covered by the recessed mask layer (2) are etched away down to an etch depth which is smaller than the final vertical extension of the raised source regions (104) after the temperature annealing step.
5. Method according to any of the preceding claims, wherein during the etching process the portion of the semiconductor body (10) not covered by the recessed mask layer (2) is etched away at least down to an etch depth corresponding to the projected extent of the implantation of the dopants of the first conductivity type.
6. The method according to any of the preceding claims, further comprising forming a body region (102) in the semiconductor body (10) by a first implantation of a dopant of a second conductivity type complementary to the first conductivity type, wherein the recessed body region (1021) is comprised in the body region (102).
7. The method of claim 6, further comprising second implanting dopants of the second conductivity type into at least a portion of the recessed body region (1021) after the first etching process.
8. The method according to any of the preceding claims, further comprising forming at least two trenches (14, 15), the trenches (14, 15) extending from the surface (100) into the semiconductor body (10) along a vertical direction (Z), wherein two trench sidewalls (144, 154) of two adjacent ones of the trenches (14, 15) facing each other laterally define a mesa region (105) of the semiconductor body (10) along a first lateral direction (X); and is
Wherein the raised source regions (104) and the recessed body regions (1021) are formed inside the mesa regions (105).
9. The method of claim 8, wherein, in a top view on the semiconductor body surface (100), the regions (104-1) of intended source regions are distributed along at least one of the trenches (14, 15) and are spaced apart from each other along a main lateral extension direction (Y) of the respective trench (14, 15).
10. The method of claim 9, wherein, in the top view, the region (104-1) of the intended source region comprises a plurality of source stripes and/or source islands.
11. The method of claim 9 or 10, wherein an extension (L Y) of the region (104-1) of the intended source region along the main lateral extension direction (Y) of the trench (14, 15) amounts to at most 5 μ ι η.
12. The method according to any one of claims 8 to 11, wherein the at least two adjacent trenches (14, 15) are formed as
-a control trench (14) comprising the control electrode (141); and
-a source trench (15) comprising a source electrode (151).
13. The method according to any of the preceding claims, wherein the two trench sidewalls (144, 154) are spaced apart along the first lateral direction (X) by at most 5 μm.
14. Method according to any of the preceding claims, wherein the recessed mask layer (2) covers a plurality of control trenches (14).
15. A power semiconductor device (1) comprising:
-a semiconductor body (10) having a surface (100);
-a control electrode (141) arranged at least partially on or inside the semiconductor body (10) and configured to control a load current in the semiconductor body (10);
-a plurality of raised source regions (104) of a first conductivity type arranged in the semiconductor body (10) adjacent to the control electrode (141);
-a plurality of recessed body regions (1021) arranged adjacent to the raised source regions (104); and
-a dielectric layer (18) arranged on a portion of the semiconductor body surface (100) and defining a contact hole (185), the contact hole (185) being at least partially filled with a conductive material (111) establishing an electrical contact with at least a portion of the raised source region (104) and at least a portion of the recessed body region (1021);
wherein at least one first contact surface (1048) between at least one of the raised source regions (104) and the dielectric layer (18) extends in a first level (H1), and at least one second contact surface (1028) between at least one of the recessed body regions (1021) and the dielectric layer (18) extends substantially in a second level (H2), the second level (H2) being located vertically below the first level (H1).
16. Power semiconductor device (1) according to claim 15, wherein a first vertical distance (DZ 1) between the first level (H1) and the second level (H2) amounts to at least 10 nm.
17. The power semiconductor device (1) according to any one of claims 15 or 16, wherein a first vertical distance (DZ 1) between the first level (H1) and the second level (H2) is smaller than a first vertical extension (L Z1) of the at least one raised source region (104) with the contact surface (1048) of the dielectric layer (18).
18. A power semiconductor device (1) comprising:
-a semiconductor body (10) having a surface (100);
-a control trench (14) extending from the surface (100) into the semiconductor body (10) along a vertical direction (Z);
-a control electrode (141) arranged at least partially inside the control trench (14) and configured to control a load current in the semiconductor body (10);
-at least two raised source regions (104) of a first conductivity type arranged in the semiconductor body (10) adjacent to the control electrode (141);
-a recessed body region (1021) of a second conductivity type arranged adjacent to the raised source regions (104) and extending at least partially between the raised source regions (104); and
-a conductive layer (1111) arranged on top of the semiconductor body (10) and establishing electrical contact with at least a part of the raised source region (104) and with at least a part of the recessed body region (1021);
wherein at least one third contact surface (1049) between at least one of the raised source regions (104) and the conductive layer (1111) extends substantially in a third level (H3), and a fourth contact surface (1029) between the recessed body region (1021) and the conductive layer (1111) extends substantially in a fourth level (H4), the fourth level (H4) being located vertically below the third level (H3).
19. Power semiconductor device (1) according to claim 18, wherein a second vertical distance (DZ 2) between the third level (H3) and the fourth level (H4) amounts to at least 10 nm.
20. The power semiconductor device (1) according to any of claims 18 or 19, wherein a second vertical distance (DZ 2) between the third level (H3) and the fourth level (H4) is smaller than a second vertical extension (L Z2) of the at least one raised source region (104) with the contact surface (1049) of the conductive layer (1111).
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US11888061B2 (en) 2024-01-30
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