CN111460755A - Method for generating any angle graph in IC layout design - Google Patents
Method for generating any angle graph in IC layout design Download PDFInfo
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- CN111460755A CN111460755A CN202010342969.2A CN202010342969A CN111460755A CN 111460755 A CN111460755 A CN 111460755A CN 202010342969 A CN202010342969 A CN 202010342969A CN 111460755 A CN111460755 A CN 111460755A
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Abstract
The invention discloses a method for generating an arbitrary angle graph in IC layout design, which comprises the following steps: 1) determining a rotation angle and a stage number; 2) calculating the electronic turning radius and angle; 3) drawing two concentric rings on the channel stop layer; 4) drawing rays rotating at equal angles; 5) generating a pattern of gaps; 6) the desired corner element is obtained. According to the method, a user can draw corner units of any number of stages in Virtuoso software by combining with a graphics processing tool carried by Virtuoso to form a fan-shaped graphic of any angle from 0 degree to 360 degrees, and areas occupied by different layers in the graphic can be distributed in proportion.
Description
Technical Field
The invention relates to the field of EDA (electronic design automation) design, in particular to a method for generating an arbitrary angle graph in IC (integrated circuit) layout design.
Background
Virtuoso (integrated circuit design software) is a circuit, layout design tool introduced by Cadence (some EDA software vendor). Layout designers can fully utilize the tool to complete various layout designs by relying on process libraries provided by various process manufacturers. In the layout design of an EMCCD (electron multiplying charge coupled device), in order to realize the turning of the flow of electrons, a corner unit is needed, the effective area of a polycrystalline silicon gate electrode in the unit needs to be large enough, and the charge capacity is larger than a certain value; and according to the process requirements, the width of the polycrystalline silicon at the inner angle is also larger than a certain value; the polysilicon width of each level is uniform. Due to the limitation of Virtuoso software, the graphics with special requirements at any angle are inconvenient to draw, and only by a method of drawing circles first and then cutting, the graphics drawn by the method at each level cannot be consistent, the size of each level cannot be controlled, and after the layout is drawn, if the graphics need to be modified at the later stage, the situation of pulling the whole body occurs, and the time is particularly wasted.
Disclosure of Invention
Aiming at the problems, the invention provides a method for generating a graph with any angle in IC layout design, a user can draw corner units with any number of stages according to the method and a graph processing tool carried by Virtuoso to form a fan-shaped graph with any angle from 0 degree to 360 degrees, and the areas occupied by different layers in the graph can be distributed in proportion.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method for generating any angle graph in IC layout design comprises the following steps:
1) determining angle of rotation and number of stages
Determining the angle of the electron to be rotated and the stage number of the electron to flow through according to the actual requirements of the layout and the process;
2) calculating electronic turning radius and angle
Calculating the inner radius R1 and the outer radius R2 of a sector for electronic turning on the layout, determining the number of the polysilicon rays of each layer according to the stage number of the step 1), and adding one to the stage number; determining the rotation angle of the ray for different polysilicon, wherein the rotation angle is the length of the middle ring line of each stage divided by (R1 + R2)/2, and is in a local and overall relation with the rotation angle of the electron in the step 1);
3) drawing two concentric rings
Drawing two concentric rings on the channel stop layer;
4) drawing rays with equal angles of rotation
Determining the width of the ray according to the process requirement, and drawing the overlapping part of the polycrystalline silicon in the layout by combining the rotation angle of the ray obtained in the step 2);
5) pattern for generating gaps
Adding some auxiliary layers, carrying out NAND operation with rays to obtain graphs of gaps, and modifying the attributes of the graphs of the gaps to obtain graphs of each level;
6) to obtain the required corner unit
And cutting the pattern of the gap, and deleting redundant polysilicon of the inner and outer circular rings to obtain the required corner unit.
Further, in step 1), the number of stages is determined by dividing the distance traveled by the electrons on the middle ring line when the electrons are turned by the width of each stage.
Further, step 4) draws the ray with the equal angle of rotation, and the specific steps are as follows:
(1) calling a tool box generated by a program, namely selecting an EMCCD _ TOO L pull-down menu from a layout interface menu of Virtuoso, and inputting parameters in a popped user input menu for creating rays;
(2) an angularly uniform ray of a set width emanating from the origin is automatically generated.
Further, the parameters input in step (1) include: the number of rays to be drawn, the width of the rays, the length of the rays, the start coordinate and the angle to be rotated are required within the range of 180 degrees.
Further, the step (1) of generating the tool box by the program is as follows:
(1.1) writing a program: writing a program for drawing rays with equal width and equal angle rotation from an original point to form a program file program; writing a program for embedding a user input menu for creating a ray into a Virtuoso software menu;
(1.2) program configuration: configuring a program file program to a Virtuoso software environment, and automatically loading the program file program when the Virtuoso software is started;
(1.3) generating a tool box: generating a user input menu for creating a ray in a pull-down menu in a layout interface of Virtuoso; and when the user input menu is clicked, popping up a dialog box for creating the ray, so that the user can set the input parameters.
Further, in step 5), the pattern of the gap is a wedge-shaped pattern.
Further, in step 6), the multiple layers of polysilicon form a stage, and the area of each stage and the overlapping of polysilicon and polysilicon are all the same.
The invention achieves the following beneficial effects:
the invention discloses a method for generating a graph at any angle in IC layout design, wherein a user can draw corner units of any number of stages according to the method by Virtuoso in combination with a graph processing tool carried by Virtuoso to form a fan-shaped graph at any angle from 0 degree to 360 degrees, and the areas occupied by different layers in the graph can be distributed in proportion.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a schematic diagram of a program in-line menu in virtuoso;
FIG. 3 is a parameter setting menu (for the user to input the numerical value of the incident ray) after the "create path in recipient angle" menu in virtuoso is clicked, and the description of each parameter;
FIG. 4 is an example of virtuoso with 3 sets of rays, 6 per set;
fig. 5 is a general diagram obtained after the respective hierarchical operations in virtuoso.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The invention is described in detail below with reference to the actual process, layout and drawings. The invention relates to extended function development based on Virtuoso software. Through the Skill program interface of the software, the improvement of the layout drawing function can be realized by combining with the tool carried by Virtuoso through certain sequential operation.
In this embodiment, in a Virtuoso environment, a CCD (charge coupled device) process with 4 layers of polysilicon, double layers of aluminum, and a minimum line width of 1um is adopted, and a corner unit of an EMCCD (electron multiplying charge coupled device) layout is designed, which includes the following specific steps:
1. fixed rotation angle and number of stages
The layout requires that electrons change from the horizontal direction to the vertical direction when flowing, the electrons need to turn 90 degrees, and the stage number is determined according to the distance traveled by the electrons on the middle ring line during turning divided by the width of each stage.
2. Calculating parameters such as radius, angle and the like by combining process requirements
For example, the radius is determined according to the number of reserved turning distances for the electronic devices on the layout, the angle is equal to the width of each layer of polycrystalline silicon divided by the radius of the middle ring line, the number of stages is equal to the arc length of the middle ring line divided by the width of each stage, and the number to be filled in the "inputtche angle" in fig. 3 is 2 times of the number of stages.
3. Drawing two concentric rings
According to the process information requirement, inner and outer Pstop rings are drawn, in the example, only the Pstop ring of the first quadrant is reserved, and the flow of electrons is turned by 90 degrees.
4. Ray drawing rotation with equal angle
(1) Writing a program: because the corner units are in the shape of a sector, the polysilicon has equal-width overlapping, the equal-width overlapping is drawn by a programming method, and when a program is operated, the overlapping presents the appearance of an emergent ray, can be equally divided by 360 degrees and can rotate at a certain angle relative to an X axis. Writing a program for drawing rays with equal width and equal angle rotation from an original point to form a program file program, such as a path _ cir.il file; writing a program for embedding a user-defined menu into a Virtuoso software menu, wherein the program comprises a user input menu, and when the user input menu is clicked, a dialog box is popped up for a user to set parameters;
(2) program configuration: and configuring the program file program to a Virtuoso software environment, wherein the program is automatically loaded when the Virtuoso is started. Configuring a program script file such as path _ cir.il into cdsinit;
(3) calling a tool box generated by a program, namely selecting an EMCCD _ TOO L pull-down menu in a layout interface menu of Virtuoso, and popping up a create path in certain angle option when a mouse is placed on the menu, as shown in FIG. 2;
(4) filling parameters: when the user clicks the create path in the vertex angle with the mouse, the user input menu pops up, fills in the previously calculated parameters, and sets the parameters, as shown in fig. 3, including the number of rays to be drawn in the range of 180 degrees (which is related to the number of stages), the width and length of the rays, the start coordinate, and the angle to be rotated.
(5) Generate a certain width of rays emanating from the origin: after the setting is finished, clicking an OK button, and automatically drawing radial rays with uniform radial angles by the program. Different parameters are filled in different layers, and the effect of drawn rays is as shown in figure 4.
5. Wedge shape for generating ray gap
Filling the wedge area in the middle, drawing a quarter circle by using other layers (such as a Cont layer), copying the Cont (aperture layer) and all rays to one side, changing all copied rays into Si1 (polysilicon 1), carrying out NAND operation on the Cont layer and the Si1 layer, and then translating the generated Cont layer to obtain the wedge area. The shapes of all graphs forming the corner unit are obtained, but the attributes of the graphs do not meet the requirements of layout design, so that a series of attribute modifications are made on each layer of graph in the wedge-shaped area, and a series of attribute modifications are also made on the overlapped rays, so that the graphs meet the requirements of layout design.
6. To obtain the desired unit
The required corner elements are obtained by modifying the pattern appropriately and removing the polysilicon from the origin to the smaller radius Pstop ring, as shown in fig. 5.
The method utilizes an interactive menu by means of a Skill program, enables a user to perform a series of transformations on the generated graph by matching ray parameters typed in a menu input field with a graph processing and level processing tool carried by Virtuoso, can obtain the required layout, and is convenient and quick.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A method for generating any angle graph in IC layout design is characterized by comprising the following steps:
1) determining angle of rotation and number of stages
Determining the angle of the electron to be rotated and the stage number of the electron to flow through according to the actual requirements of the layout and the process;
2) calculating electronic turning radius and angle
Calculating the inner radius R1 and the outer radius R2 of a sector for electronic turning on the layout, determining the number of the polysilicon rays of each layer according to the stage number of the step 1), and adding one to the stage number; determining the rotation angle of the ray for different polysilicon, and dividing the length of the middle ring line of each stage by (R1 + R2)/2;
3) drawing two concentric rings
Drawing two concentric rings on the channel stop layer;
4) drawing rays with equal angles of rotation
Determining the width of the ray according to the process requirement, and drawing the overlapping part of the polycrystalline silicon in the layout by combining the rotation angle of the ray obtained in the step 2);
5) pattern for generating gaps
Adding some auxiliary layers, carrying out NAND operation with rays to obtain graphs of gaps, and modifying the attributes of the graphs of the gaps to obtain graphs of each level;
6) to obtain the required corner unit
And cutting the pattern of the gap, and deleting redundant polysilicon of the inner and outer circular rings to obtain the required corner unit.
2. The method as claimed in claim 1, wherein in step 1), the number of stages is determined by dividing the distance the electrons travel on the middle ring line during electron steering by the width of each stage.
3. The method for generating any angle graph in IC layout design according to claim 1, wherein step 4) draws rays with equal rotation angles, and comprises the following steps:
(1) calling a tool box generated by a program, namely selecting an EMCCD _ TOO L pull-down menu from a layout interface menu of Virtuoso, and inputting parameters in a popped user input menu for creating rays;
(2) an angularly uniform ray of a set width emanating from the origin is automatically generated.
4. A method as claimed in claim 3, wherein the parameters input in step (1) include: the number of rays to be drawn, the width of the rays, the length of the rays, the start coordinate and the angle to be rotated are required within the range of 180 degrees.
5. A method as claimed in claim 3, wherein the step (1) of generating the tool box comprises the steps of:
(1.1) writing a program: writing a program for drawing rays with equal width and equal angle rotation from an original point to form a program file program; writing a program for embedding a user input menu for creating a ray into a Virtuoso software menu;
(1.2) program configuration: configuring a program file program to a Virtuoso software environment, and automatically loading the program file program when the Virtuoso software is started;
(1.3) generating a tool box: generating a user input menu for creating a ray in a pull-down menu in a layout interface of Virtuoso; and when the user input menu is clicked, popping up a dialog box for creating the ray, so that the user can set the input parameters.
6. The method as claimed in claim 1, wherein in step 5), the pattern of the gap is a wedge-shaped pattern.
7. The method as claimed in claim 1, wherein in step 6), the polysilicon layers form a stage, and the area of each stage and the overlapping of polysilicon and polysilicon are all the same.
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JP2008288360A (en) * | 2007-05-17 | 2008-11-27 | Nuflare Technology Inc | Charged particle beam plotting apparatus and charged particle beam plotting method |
CN107861785A (en) * | 2017-10-30 | 2018-03-30 | 北方电子研究院安徽有限公司 | It is a kind of to interact the online quick method for carrying out redundancy metal filling |
CN107862118A (en) * | 2017-10-30 | 2018-03-30 | 北方电子研究院安徽有限公司 | The domain level of selected figure is quickly modified as to the method for metallograph figure layer time |
CN109271677A (en) * | 2018-08-27 | 2019-01-25 | 北方电子研究院安徽有限公司 | A kind of method that domain lattic point problem is repaired in online stratification |
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Patent Citations (5)
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JP2008085248A (en) * | 2006-09-29 | 2008-04-10 | Nuflare Technology Inc | Method for creation of charged particle beam drawing data and method for conversion of charged particle beam drawing data |
JP2008288360A (en) * | 2007-05-17 | 2008-11-27 | Nuflare Technology Inc | Charged particle beam plotting apparatus and charged particle beam plotting method |
CN107861785A (en) * | 2017-10-30 | 2018-03-30 | 北方电子研究院安徽有限公司 | It is a kind of to interact the online quick method for carrying out redundancy metal filling |
CN107862118A (en) * | 2017-10-30 | 2018-03-30 | 北方电子研究院安徽有限公司 | The domain level of selected figure is quickly modified as to the method for metallograph figure layer time |
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