CN111459741A - Universal memory data and address generation algorithm - Google Patents
Universal memory data and address generation algorithm Download PDFInfo
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- CN111459741A CN111459741A CN202010232345.5A CN202010232345A CN111459741A CN 111459741 A CN111459741 A CN 111459741A CN 202010232345 A CN202010232345 A CN 202010232345A CN 111459741 A CN111459741 A CN 111459741A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
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Abstract
A general memory data and address generation algorithm includes a first step of generating a memory address, a second step of generating memory data, and a third step of writing the memory data into the memory address. The invention generates memory addresses through simple operation and complex operation, and has two methods for generating memory data, wherein one method generates corresponding memory data through the generated memory addresses, and the other method generates memory data by performing function operation again by taking the generated memory addresses as variables.
Description
Technical Field
The invention relates to the technical field of chip detection, in particular to a general memory data and address generation algorithm.
Background
A data memory is an electronic device for writing and/or reading electronic data, and may be classified as a volatile memory that generally requires power to maintain its stored information, such as a random access memory RAM, or a non-volatile memory that can maintain its stored information even when power is turned off, such as a read only memory ROM, and may write and/or read electronic data to and/or from an array of memory cells accessible through respective control lines. The memory is composed of a plurality of memory units, each memory unit is numbered for distinguishing, the number is the data address of the memory, each memory unit stores one byte of function data, and the information to be stored is stored in the memory unit in each memory address.
Before a data memory chip leaves a factory, the reliability and the completeness of the function of the data memory chip need to be tested, the reliability test comprises electrical connection performance detection, power consumption detection, reading detection, writing and erasing detection and the like, the existing test method is too complex, the data memories of different interfaces need different interface time sequences to complete the function test work aiming at different data memories, the algorithm of each different data memory has great difference, and different test algorithms need to realize different test codes to complete the function test of the data memory, so that the test work of the data memory is very complex. When incoming material detection needs to be performed on the data memory in some specific occasions, the requirement on the rapidity of the data memory detection is high, a general data memory detection algorithm is too complex, so that the detection time is too long, and the factory efficiency of the whole data memory is affected, and various factors affecting the detection algorithms of the data memory are that the algorithms generated by data and addresses of each data memory are different, so that the detection algorithms are different.
Therefore, in order to make up for the above-mentioned shortcomings of the conventional data memory detection algorithm, it is necessary to design a general memory data and address generation algorithm which can improve the detection efficiency and satisfy the detection requirements of each data memory.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a data and address generation algorithm which can meet the normal functions of all memories.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a universal memory data and address generation algorithm comprising the steps of:
a first step of generating a memory address, said memory address generation comprising the steps of:
the method comprises the steps of variable processing, namely dividing a memory address into a plurality of dimensions, wherein each dimension comprises a plurality of variables;
the variable operation processing, the generation of the memory address comprises simple operation and complex operation, and the complex operation is function operation;
address spelling processing, when the memory address is an ultra-wide address, a plurality of dimensions can be combined to obtain a wider memory address space;
address output, each dimension can select the result of simple operation or function operation to output;
a second step of generating memory data, said memory data generation comprising the steps of:
generating simple data, and generating memory data corresponding to simple operation and complex operation of the memory address in the first step;
generating function data, and performing function operation by taking the memory address as a variable to generate memory data;
data output, wherein each dimension can select the results in the simple data generation step and the function data generation step for output;
and thirdly, writing the memory data into the memory address.
Preferably, the operators of the simple operation include set, increment, decrement, hold, and the like, and the simple operation simultaneously and respectively performs operator processing on each variable in each dimension.
Preferably, the function operation includes an operator and an operation function, the operator is selected from a plurality of variables, and the operator of the operation function includes addition, subtraction, bitwise and, bitwise or, and left and right shift, etc.
Preferably, the writing of the memory data into the memory address in the third step includes the following steps:
selecting variables, setting memory data or memory addresses to be N dimensions, arbitrarily selecting one dimension from the N dimensions and naming the dimension as X, arbitrarily selecting one variable from the dimension X and naming the dimension as a, naming the memory data or memory address containing the dimension X and the variable a as Xa, and initializing the Xa;
operation, memory data or memory address Xa calls simple operator in each unit clock cycle, and then outputs the effective memory data or memory address Xa in each clock cycle;
and (4) triggering storage, namely generating a completion mark and waiting for next triggering after dimension X in the data or the address Xa of the storage is completely accumulated through addition operation.
Preferably, the address stitching processing steps are as follows: when the generated memory data or memory address exceeds Xa, another dimension named Y is combined with the variable named b in the dimension and spliced with Xa to form a memory data or memory address space XaYb which is larger than the address range of Xa, data or address mapping is carried out, if the address range is still larger, the operation can be repeated, namely, a variable named c is selected in another dimension named Z and spliced and combined with XaYb until the requirement of all memory data or memory address access is met.
The invention has the advantages and positive effects that:
1. the invention generates memory addresses through simple operation and complex operation, and has two methods for generating memory data, one method generates corresponding memory data through the generated memory addresses, and the other method generates memory data by performing function operation again by taking the generated memory addresses as variables.
2. When the length of the generated memory address or memory data exceeds the range of the original dimension variable, the invention can adopt the address splicing processing step to splice the variable in the other dimension with the original dimension variable to generate a larger address space for address mapping until the requirement of all memory address access is met.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The embodiments of the invention are described in further detail below:
the invention relates to a general memory data and address generating algorithm, which comprises the following steps:
a first step of generating a memory address, said memory address generation comprising the steps of:
the method comprises the steps of variable processing, namely dividing a memory address into a plurality of dimensions, wherein each dimension comprises a plurality of variables;
the variable operation processing, the generation of the memory address comprises simple operation and complex operation, and the complex operation is function operation;
address spelling processing, when the memory address is an ultra-wide address, a plurality of dimensions can be combined to obtain a wider memory address space;
address output, each dimension can select the result of simple operation or function operation to output;
a second step of generating memory data, said memory data generation comprising the steps of:
generating simple data, and generating memory data corresponding to simple operation and complex operation of the memory address in the first step;
generating function data, and performing function operation by taking the memory address as a variable to generate memory data;
data output, wherein each dimension can select the results in the simple data generation step and the function data generation step for output;
and thirdly, writing the memory data into the memory address.
Further, the operators of the simple operation include setting, increasing, decreasing, holding and the like, and the simple operation simultaneously and respectively performs operator processing on each variable in each dimension.
Furthermore, the function operation comprises an operator and an operation function, the operator is selected from a plurality of variables, and the operator of the operation function comprises addition, subtraction, bitwise AND, bitwise OR, XNOR, left-right shift and the like.
Further, the process of writing the memory data into the memory address in the third step includes the following steps:
selecting variables, setting memory data or memory addresses to be N dimensions, arbitrarily selecting one dimension from the N dimensions and naming the dimension as X, arbitrarily selecting one variable from the dimension X and naming the dimension as a, naming the memory data or memory address containing the dimension X and the variable a as Xa, and initializing the Xa;
operation, memory data or memory address Xa calls simple operator in each unit clock cycle, and then outputs the effective memory data or memory address Xa in each clock cycle;
and (4) triggering storage, namely generating a completion mark and waiting for next triggering after dimension X in the data or the address Xa of the storage is completely accumulated through addition operation.
Further, the address splicing processing steps are as follows: when the generated memory data or memory address exceeds Xa, another dimension named Y is combined with the variable named b in the dimension and spliced with Xa to form a memory data or memory address space XaYb which is larger than the address range of Xa, data or address mapping is carried out, if the address range is still larger, the operation can be repeated, namely, a variable named c is selected in another dimension named Z and spliced and combined with XaYb until the requirement of all memory data or memory address access is met.
Further, in this embodiment, a moving diagonal algorithm is applied to check whether the decoding of the row address and the decoding of the column address are correct, and the moving diagonal algorithm includes the following steps:
setting a diagonal line, writing all backgrounds of memory addresses into 0, and writing 1 into one diagonal line of the background;
reading comparison, namely reading the stored data content of the memory address, comparing the read data content with the background of the memory address, moving the diagonal line of the background of the memory address, repeatedly comparing the diagonal line, and comparing the comparison result with a preset result, wherein the test is successful if the preset result is met, and otherwise, the test is failed;
and repeatedly comparing, writing all backgrounds of the memory address into 1, writing 0 into one diagonal line of the background, repeating the reading and comparing steps, comparing the compared result with a preset result, and if the preset result is met, the test is successful, otherwise, the test is failed.
Further, in this embodiment, a walker walking algorithm is applied to detect whether a generated memory address is correct, where the walker walking algorithm writes each memory address into a specific numerical value in a memory in which all 0 or all 1 background data already exist, and then reads out and compares the values, and then writes back the background data, where the walker walking algorithm includes the following steps:
setting a background, namely writing all backgrounds of memory addresses into 0;
the method comprises the following steps of variable instantiation, selecting a group of variables from memory addresses storing data, sequentially naming the variables as Xa and Xb, instantiating the variables Xa and Xb, respectively performing accumulation operation, selecting Xa to output the memory addresses and 1 to output the memory data when the variables Xa are instantiated, and selecting Xb to output the memory addresses when the variables Xb are instantiated;
data comparison, when the factorization of the variable Xa accumulated at each time is equal to the variable Xb, the memory address output is 0, and when the variable Xa is equal to the variable Xb, the memory address output is 1;
and outputting the test, and repeating the variable instantiating step and the data comparing step until all the stored data in the data memory are tested.
The invention generates memory addresses through simple operation and complex operation, and has two methods for generating memory data, one method generates corresponding memory data through the generated memory addresses, and the other method generates memory data by performing function operation again by taking the generated memory addresses as variables. When the length of the generated memory address or memory data exceeds the range of the original dimension variable, the invention can adopt the address splicing processing step to splice the variable in the other dimension with the original dimension variable to generate a larger address space for address mapping until the requirement of all memory address access is met.
It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but other embodiments derived from the technical solutions of the present invention by those skilled in the art are also within the scope of the present invention.
Claims (5)
1. A universal memory data and address generation algorithm, characterized by: the method comprises the following steps:
a first step of generating a memory address, said memory address generation comprising the steps of:
the method comprises the steps of variable processing, namely dividing a memory address into a plurality of dimensions, wherein each dimension comprises a plurality of variables;
the variable operation processing, the generation of the memory address comprises simple operation and complex operation, and the complex operation is function operation;
address spelling processing, when the memory address is an ultra-wide address, a plurality of dimensions can be combined to obtain a wider memory address space;
address output, each dimension can select the result of simple operation or function operation to output;
a second step of generating memory data, said memory data generation comprising the steps of:
generating simple data, and generating memory data corresponding to simple operation and complex operation of the memory address in the first step;
generating function data, and performing function operation by taking the memory address as a variable to generate memory data;
data output, wherein each dimension can select the results in the simple data generation step and the function data generation step for output;
and thirdly, writing the memory data into the memory address.
2. A universal memory data and address generation algorithm as claimed in claim 1, wherein: the operators of the simple operation comprise setting, increasing, decreasing, keeping and the like, and the simple operation simultaneously and respectively carries out operator processing on each variable in each dimension.
3. A universal memory data and address generation algorithm as claimed in claim 1, wherein: the function operation comprises an operator and an operation function, the operator is selected from a plurality of variables, and the operator of the operation function comprises addition, subtraction, bitwise AND, bitwise OR, XNOR, left and right shift and the like.
4. A universal memory data and address generation algorithm as claimed in claim 1, wherein: the process of writing the memory data to the memory address in the third step comprises the steps of:
selecting variables, setting memory data or memory addresses to be N dimensions, arbitrarily selecting one dimension from the N dimensions and naming the dimension as X, arbitrarily selecting one variable from the dimension X and naming the dimension as a, naming the memory data or memory address containing the dimension X and the variable a as Xa, and initializing the Xa;
operation, memory data or memory address Xa calls simple operator in each unit clock cycle, and then outputs the effective memory data or memory address Xa in each clock cycle;
and (4) triggering storage, namely generating a completion mark and waiting for next triggering after dimension X in the data or the address Xa of the storage is completely accumulated through addition operation.
5. A universal memory data and address generation algorithm as claimed in claim 4, wherein: the address splicing processing steps are as follows: when the generated memory data or memory address exceeds Xa, another dimension named Y is combined with the variable named b in the dimension and spliced with Xa to form a memory data or memory address space XaYb which is larger than the address range of Xa, data or address mapping is carried out, if the address range is still larger, the operation can be repeated, namely, a variable named c is selected in another dimension named Z and spliced and combined with XaYb until the requirement of all memory data or memory address access is met.
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| CN104123231A (en) * | 2013-04-24 | 2014-10-29 | 晨星半导体股份有限公司 | Memory controller and memory address generating method |
| US20160188206A1 (en) * | 2014-12-29 | 2016-06-30 | Sandisk Technologies Inc. | Non-Volatile Memory Systems Utilizing Storage Address Tables |
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