CN111459559A

CN111459559A - Improved system and method for rapidly waking up processor based on RISC-V architecture

Info

Publication number: CN111459559A
Application number: CN202010237778.XA
Authority: CN
Inventors: 胡振波; 周在新
Original assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Current assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2020-07-28

Abstract

The invention discloses an improved system and a method for rapidly waking up a processor based on a RISC-V architecture, which comprises an wfe _ en register used for switching a wake-up mechanism of the processor after a wifi instruction is executed. The design of the register in the invention can change the wake-up condition of the wifi instruction, thereby achieving the purpose that the processor can be woken up in different modes.

Description

Improved system and method for rapidly waking up processor based on RISC-V architecture

Technical Field

The invention relates to the field of low-power-consumption kernel interrupt processing technology and low power consumption, in particular to an improved system and method for rapidly waking up a processor based on a RISC-V architecture.

Background

With the increasing complexity of SoC design, the power consumption of consumer electronics is now required to be higher and higher, and with the low power consumption technology developed in the chip design industry, the attention of each large chip company is also higher and higher.

Most low power consumption technologies enable a processor to enter a sleep state to achieve the purpose of saving power, but in many application scenarios, the processor needs to be woken up in various ways, in a RISC-V instruction architecture, a wfi instruction is generally executed to enable the processor to be in a sleep mode, and the wakening of the wfi instruction is generally in an interrupt, non-maskable interrupt (NMI) or Debug mode, but these wakening mechanisms are limited, and the wakening speed is slow, and after wakening, subsequent programs cannot be directly executed, so that the processor executes many operations which are not to be executed. In many application scenarios, the user needs to make the processor enter the sleep mode quickly, wake up quickly, and continue to execute the subsequent instruction program after waking up, so that the wifi instruction of the RISC-V standard cannot completely satisfy the application scenarios, and therefore a mechanism is needed to solve the problem. The invention is an improved technology with low power consumption based on a wifi instruction in a RISC-V standard instruction architecture.

Disclosure of Invention

In order to solve the technical problem, the invention provides an improved system and a method for rapidly waking up a processor based on a RISC-V architecture, a low-power-consumption register design of the processor is added based on the RISC-V architecture, the register is named as an wfe _ en register, and the design of the register can change the behavior of a wfi instruction, so that the processor can be wakened in different modes. The technical scheme of the invention is that a self-defined register wfe _ en is added based on a RISC-V instruction architecture.

In order to achieve the purpose, the technical scheme of the invention is as follows:

the improved system for rapidly waking up the processor based on the RISC-V architecture is characterized by comprising an wfe _ en register, wherein the wfe _ en register is used for switching a wake-up mechanism of the processor after a wifi instruction is executed.

Preferably, the wfe _ en register is 64-bit or 32-bit wide.

Preferably, the 0 th bit of the wfe _ en register is a valid bit.

Preferably, the wfe _ en register is a writable register readable in both user mode and machine mode.

An improved method for rapidly waking up a processor based on RISC-V architecture is characterized in that,

s1: wfe _ en register is added in the RISC-V architecture, and the wfe _ en register is used for switching a wake-up mechanism of the processor after the execution of the wifi instruction;

s2: when the processor needs to be awakened when entering the sleep mode, if the wfe _ en register is configured to be 0, the wfe _ en register indicates that the processor can be awakened by an interrupt, a non-maskable interrupt or a Debug; if the wfe _ en register is configured as 1, the wfi instruction wake request mode is changed to wfe instruction wake request mode, which indicates that the processor can be woken by an external event, a non-maskable interrupt, or a Debug.

Preferably, the wfe _ en register is 64-bit or 32-bit wide.

Preferably, the 0 th bit of the wfe _ en register is a valid bit.

Based on the technical scheme, the invention has the beneficial effects that:

(1) the wake-up mode of the processor is added, the processor can receive the external event signal to wake up, the wake-up mechanism of the wfi instruction can be changed only by configuring wfe _ en registers, and the wake-up mode is simple and easy to operate;

(2) compared with the traditional interrupt wakeup, the invention can directly start execution from the instruction after the wfe instruction without entering the interrupt processing function by the program.

Drawings

FIG. 1 is a diagram of the storage information format of the wfe _ en register for a RISC-V architecture according to the present invention;

FIG. 2 is a wake-up flow diagram of a wfi instruction when the wfe _ en register is configured as 0 and 1 according to the present invention;

FIG. 3 is a diagram illustrating a wake-up process for performing a wfi wait for an external event when the wfe _ en register is configured as 1 according to the present invention;

FIG. 4 is a diagram of a wake-up process for performing wfi wait for NMI when the wfe _ en register is configured as 1 according to the present invention;

FIG. 5 is a diagram of a process for performing a wfi wait Debug wakeup process when the wfe _ en register is configured as 1 according to the present invention;

FIG. 6 is a circuit diagram of an wfe _ en register for RISC-V architecture implementing the wfi instruction wake-up switch according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific embodiments.

Example one

The technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and the improved system and method for quickly waking up a processor based on a RISC-V architecture of the present invention adds a design of a low power consumption register of the processor based on the RISC-V architecture, and names the register as wfe _ en register, and the design of the register can change the wake-up condition of a wfi instruction, so that the processor can be woken up in different ways. The technical scheme of the invention is as follows, the invention adds a custom register wfe _ en register.

Further, the wfe _ en register is described in detail as follows:

an wfe en register is added, which can change the instruction behavior of wfi,

the processor will enter sleep mode when executing the wifi instruction.

The wfe _ en register is used to change the wake-up mode of the processor after the execution of the wifi instruction.

As shown in FIG. 2, when the wfe _ en register is configured as 0, when the wfi instruction is executed, the processor goes to sleep, and when the wake-up condition of the wfi instruction is reached, the processor is woken up, which is the same as the wake-up condition defined by the standard RISC-V instruction architecture, i.e. it can be woken up by interrupt, NMI, Debug.

When the wfe _ en register is configured to be 1, when a wfi instruction is executed, the processor enters a sleep state, and if the wfe _ en register is configured to be 1, the wfi instruction wake-up request mode is changed to be a wfe instruction wake-up request mode, which indicates that the processor can be woken up by an external event request, a non-maskable interrupt request, or a Debug request. The wfe instruction is a virtual instruction, the wfe instruction is not in the standard instruction set, and the wfe instruction is used to illustrate the wake-up condition of the wfi instruction when the wfe _ en register is configured as a 1. When executing wfe instructions, the processor enters sleep mode and is able to wake up wfe instructions by either:

(1) when an external event is input from the outside of the processor, if the MIE of mstatus is 0, the processor will be woken up to continue executing the stopped instruction stream, as shown in fig. 3. If mstatus has an MIE of 1, the processor will wake up and may begin executing from an enabled and suspended interrupt service routine, or from an instruction following the wfe instruction.

The mstatus register is the same as defined in the RISC-V Standard instruction architecture Manual.

The MIE field is a global interrupt enabling field in the mstatus and is used for controlling the opening or closing of the global interrupt, when the MIE is 0, the external interrupt is shielded, the interrupt cannot be responded, and when the MIE is 1, the external interrupt global enabling field is opened.

Firstly, the wfe _ en register is configured as 1, then a wfi instruction is executed, the processor enters a sleep state, now, assuming that only an external event request can enter, the processor waits for the external event request to arrive, is awakened, and then continues to execute the subsequent program, and if the MIE is 0, the processor wakes up and then continues to execute the subsequent instruction; if the MIE is 1 and there is an interrupt waiting during sleep, the processor will enter interrupt handling after waking up.

(2) When an NMI interrupt is received, the processor will wake up and begin execution from the first instruction of the NMI handler, as shown in fig. 4.

The wfe en register is first configured to 1 and then the wfi instruction is executed and the processor goes to sleep, now assuming only non-maskable interrupts (NMIs) can be entered, the incoming processor will wake up and then go to the non-maskable interrupt (NMI) handler.

(3) When a debug signal is received from the debug module, the processor will wake up and enter debug mode, as shown in fig. 5.

The wfe en register is first configured to be 1 and then the wfi instruction is executed and the processor goes to sleep, now assuming only Debug requests can be entered, then the Debug request will come to the processor and wake up and go to Debug mode.

The specific circuit design of the present invention and the behavior of the processor when wfe _ en is configured as 0 and 1 are illustrated in several specific embodiments below.

As shown in fig. 6, a specific circuit implementation for implementing the wfi instruction wakeup switch for the wfe _ en register of the present invention is shown. The signal includes alu _ exp _ i _ wfi signal, cmt _ ena signal, wfi _ cmt _ ena signal, alu _ exp _ i _ pc _ vld signal, wfi _ hash _ req signal, wfi _ mie _ disable signal, status _ mie _ real signal, csr _ wfe _ bit signal, wfe _ waiting signal, dbg _ req _ raw signal, irq _ req _ raw signal, rx _ ext _ raw signal, nmi _ req _ raw signal, irq _ req _ signal, wherein:

the alu _ exp _ i _ wfi signal indicates that the current instruction code is a wfi instruction;

the cmt _ ena signal indicates that the current instruction has cmmint;

the wifi _ cmt _ ena signal represents a wifi instruction enable signal;

the alu _ exp _ i _ pc _ vld signal represents that the current pc instruction is an effective instruction;

the wifi _ halt _ req signal indicates that the current pc initiates a wifi instruction request;

the wifi _ mie _ disable signal indicates that a wifi instruction is currently occurring and global interrupt enable is off or a wifi instruction is currently occurring, and wfe _ en is configured as 1;

the status _ mie _ real signal, representing a current global interrupt enable flag signal;

the csr _ wfe _ bit signal, indicating that wfe _ en is configured as either 1 or 0;

the wfe _ waiting signal indicates that the current wfi instruction is switched to wfe;

the dbg _ req _ raw signal indicates that a debug request has occurred;

the irq _ req _ raw signal, indicating that an interrupt request has occurred;

the rx _ ext _ raw signal indicates that an external event request has occurred;

the NMI _ req _ raw signal, indicating that an NMI request has occurred;

the irq _ req signal indicates that a wake-up request has occurred.

Further, the circuit implements wfe _ en register to control the switching of the wake-up request mode when wfi is executed. First, as shown, when alu _ exp _ i _ wfi is valid and cmt _ ena is valid, i.e. a wfi instruction is currently committed, when alu _ exp _ i _ pc _ vld is valid, i.e. the current wfi instruction pc is valid pc, thus issuing a wfi instruction request,

further, we judge whether the present wfi instruction can be interrupted and woken up, and we get a signal wfi _ mie _ disable to indicate that the present wfi instruction cannot be interrupted and woken up. The conditions that cannot be awakened by interrupt are two, status _ mie _ real global interrupt is 0 or csr _ wfe _ bit is configured as 1, the csr _ wfe _ bit signal is controlled by wfe _ en register, so when wfe _ en register is configured as 1, wfi instruction will not be awakened by interrupt, if wfi _ mie _ disable is 1 and csr _ wfe _ bit is configured as 1, a signal with signal name wfe _ waiting is obtained, the signal effectively indicates that the current wfi instruction is switched to wfe instruction awakening behavior, and wfe instruction behavior cannot be awakened by interrupt.

Further, according to external debug, interrupt, external event, and non-maskable interrupt (NMI), signals are divided into two groups, which are dbg _ req _ raw signal, irq _ req _ raw signal, NMI _ req _ raw signal, dbg _ req _ raw signal, rx _ ext _ raw signal, and NMI _ req _ raw signal, respectively, and the signals pass through two or gates, and then pass through an alternative selector, wherein the enable signal of the selector is wfe _ waiting signal, and when the signal is valid, the selector selects a group of dbg _ req _ raw signal, rx _ ext _ raw signal, and NMI _ req _ raw signal, and finally outputs an irq _ req signal, which is used to wake up the processor.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by the present specification, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. The improved system for rapidly waking up the processor based on the RISC-V architecture is characterized by comprising an wfe _ en register, wherein the wfe _ en register is used for switching a wake-up mechanism of the processor after a wifi instruction is executed.

2. An improved RISC-V architecture fast wake-up processor based system according to claim 1, wherein said wfe en register bit width is 64 bits or 32 bits.

3. An improved RISC-V architecture fast wake-up processor based system according to claim 1, wherein the 0 th bit of the wfe _ en register is a valid bit.

4. An improved RISC-V architecture fast wake-up processor based system according to claim 1, characterised in that said wfe en register is a writable register readable in both user mode and machine mode.

5. The improved method for rapidly waking up the processor based on the RISC-V architecture is characterized by comprising the following steps:

6. An improved method for RISC-V architecture based fast wake-up processor of claim 5, wherein the wfe _ en register bit width is 64 bits or 32 bits.

7. An improved method for RISC-V architecture based fast wake-up processor of claim 5, wherein the 0 th bit of the wfe _ en register is a valid bit.

8. An improved method for RISC-V architecture based fast wake-up processor as claimed in claim 5, characterized in that said wfe en register is a writable register readable in both user mode and machine mode.