CN111446848B - Power supply circuit with adjustable channel switch impedance and electronic equipment - Google Patents

Power supply circuit with adjustable channel switch impedance and electronic equipment Download PDF

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Publication number
CN111446848B
CN111446848B CN202010348985.2A CN202010348985A CN111446848B CN 111446848 B CN111446848 B CN 111446848B CN 202010348985 A CN202010348985 A CN 202010348985A CN 111446848 B CN111446848 B CN 111446848B
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mos tube
main channel
source
voltage
current
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CN111446848A (en
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黄雷
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Shanghai Yaohuo Microelectronics Co Ltd
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Shanghai Yaohuo Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

Abstract

The invention provides a power circuit with adjustable channel switch impedance and an electronic device, comprising: the device comprises N main channel MOS tubes, a control module, an execution module and a detection module, wherein the execution module comprises a first MOS tube; the detection module comprises a detection resistor and a second MOS tube; the gate-source voltage of the main channel MOS tube is configured to be consistent with the gate-source voltage of the first MOS tube, and the source-drain voltage of the main channel MOS tube is consistent with the source-drain voltage of the second MOS tube; the control module is connected with the detection resistor and is used for: detecting the voltage drop information at two ends of the detection resistor; the voltage drop information is capable of characterizing a current of the load; and adjusting the current between the source electrode and the drain electrode of the first MOS tube according to the voltage drop information so as to adjust the source-drain voltage of the first MOS tube, so that the gate-source voltage of the main channel MOS tube is correspondingly changed, and the impedance formed by the N main channel MOS tubes is adjusted accordingly.

Description

Power supply circuit with adjustable channel switch impedance and electronic equipment
Technical Field
The present invention relates to power circuits, and particularly to a power circuit with adjustable channel switch impedance and an electronic device.
Background
In a power supply circuit of the electronic equipment, the adjustment of the main current channel can be realized by controlling the on-off of a switch device in the main current channel. The power supply circuit can be applied to the power supply output side or the power supply input side of the electronic equipment.
In the prior art, a current detection resistor and an MOS transistor for controlling the on-off of a main current channel can be connected in series in the main current channel, and further, the current of the main current channel can be determined based on the voltage of the current detection resistor. Meanwhile, the existing circuit can only realize on-off control of the channel, has a single control means, and is difficult to meet various circuit requirements.
Disclosure of Invention
The invention provides a power supply circuit with adjustable channel switch impedance and electronic equipment, which are used for solving the problems of heat loss, single control means and difficulty in meeting various circuit requirements.
According to a first aspect of the present invention, there is provided a channel switch impedance adjustable power supply circuit comprising: the device comprises N main channel MOS tubes, a control module, an execution module and a detection module, wherein N is an integer greater than or equal to 1; the execution module comprises a first MOS tube; the detection module comprises a detection resistor and a second MOS tube;
the first end of the second MOS tube and the first end of the main channel MOS tube are both connected with a first power supply, the second end of the main channel MOS tube is connected with the ground through a load, and the second end of the second MOS tube is directly or indirectly connected with the ground through the detection resistor; the grid electrode of the second MOS tube and the grid electrode of the main channel MOS tube are connected to the same circuit position, the first MOS tube is directly or indirectly connected between an execution side power supply and the ground, and the execution side power supply is the first power supply or a second power supply different from the first power supply;
the gate-source voltage of the main channel MOS tube and the gate-source voltage of the first MOS tube are configured to be consistent, the voltage between the grid electrode and the second end of the main channel MOS tube and the voltage between the grid electrode and the second end of the second MOS tube are consistent, and the parameters of the main channel MOS tube, the first MOS tube and the second MOS tube are the same;
the control module is connected with the detection resistor and is used for:
detecting the voltage drop information at two ends of the detection resistor; the voltage drop information is capable of characterizing a current of the load;
and adjusting the current between the source electrode and the drain electrode of the first MOS tube according to the voltage drop information so as to adjust the source-drain voltage of the first MOS tube, so that the gate-source voltage of the main channel MOS tube is correspondingly changed, and the impedance formed by the N main channel MOS tubes is adjusted accordingly.
Optionally, the execution module further includes a first holding unit; the first holding unit is further connected to a drain electrode of the first MOS transistor, and the first holding unit is configured to: and controlling the drain electrode of the first MOS tube to be kept at a first reference voltage.
Optionally, the first holding unit includes a first current source;
the first current source is connected between the execution side power supply and the ground after being connected with the first MOS tube in series, the first current source is connected with the drain electrode of the first MOS tube, and the control end of the first current source is also connected with the control module;
when the control module adjusts the current between the source electrode and the drain electrode of the first MOS transistor, the control module is specifically configured to: adjusting a current of the first current source.
Optionally, the first holding unit includes a first operational amplifier, a first input end of the first operational amplifier is connected to the drain of the first MOS transistor, and a second input end of the first operational amplifier is connected to the first reference voltage; the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, so that the voltage of the drain electrode of the first MOS tube is kept at the first reference voltage through the control of the first MOS tube.
Optionally, the first holding unit further includes a second current source and a reference resistor, the second current source is connected in series with the reference resistor and then connected between the execution-side power supply and ground, and the second input terminal of the first operational amplifier is connected between the second current source and the reference resistor, so as to collect a voltage of a potential between the second current source and the reference resistor as the first reference voltage.
Optionally, when the control module adjusts the current between the source and the drain of the first MOS transistor, the control module is specifically configured to: adjusting the first reference voltage;
when the control module adjusts the first reference voltage, the control module is specifically configured to adjust at least one of: the resistance value of the reference resistor, the current of the second current source, and the voltage of the potential between the second current source and the reference resistor;
when the control module adjusts the first reference voltage, the control module is specifically configured to adjust at least one of: the resistance value of the reference resistor, the current of the second current source, and the voltage of the potential between the second current source and the reference resistor.
Optionally, the main channel MOS transistor and the first MOS transistor are both PMOS, the execution side power supply is the first power supply, the drain electrode of the first MOS transistor is directly or indirectly grounded, the first end of the main channel MOS transistor is the source electrode of the main channel MOS transistor, and the second end of the main channel MOS transistor is the drain electrode of the main channel MOS transistor.
Optionally, the main channel MOS transistor and the first MOS transistor are both NMOS, the first end of the main channel MOS transistor is the drain electrode of the main channel MOS transistor, the second end of the main channel MOS transistor is the source electrode of the main channel MOS transistor, the drain electrode of the first MOS transistor is connected to the execution side power supply, and the source electrode of the first MOS transistor is directly or indirectly connected to the ground.
Optionally, the execution module further includes a gate-source voltage copying unit;
the two ends of the first side of the grid-source voltage copying unit are respectively connected with the source electrode and the grid electrode of the first MOS tube, and the voltage of the two ends of the second side of the grid-source voltage copying unit is consistent with the grid-source voltage of the main channel MOS tube;
the grid-source voltage copying unit is configured to enable the voltage across the first side and the voltage across the second side to be consistent, so that the grid-source voltage of the first MOS tube and the grid-source voltage of the main channel MOS tube are consistent.
Optionally, the detection module further includes a second holding unit;
the second holding unit is used for controlling the second end of the second MOS tube to be consistent with the voltage of the second end of the main channel MOS tube.
Optionally, the third MOS transistor is connected in series between the second end of the second MOS transistor and the detection resistor or between the detection resistor and ground, and two input ends of the second operational amplifier are respectively connected to the second end of the second MOS transistor and the second end of the main channel MOS transistor; the output end of the second operational amplifier is connected with the grid electrode of the third MOS tube, so that the voltage of the second end of the second MOS tube is consistent with that of the second end of the main channel MOS tube through the control of the third MOS tube.
Optionally, the control module adjusts the current between the source and the drain of the first MOS transistor according to the voltage drop information to adjust the source-drain voltage of the first MOS transistor, so that the gate-source voltage of the main channel MOS transistor changes correspondingly, and when the impedance formed by the N main channel MOS transistors is adjusted accordingly, the control module is specifically configured to:
determining the current of the load according to the voltage drop information;
according to the current range of the current of the load and the corresponding relation between different current ranges and different impedances of the main channel MOS tube, adjusting the current between the source electrode and the drain electrode of the first MOS tube so as to enable the impedance of the main channel MOS tube to be in the impedance corresponding to the current range;
in the correspondence, at least one of the following is satisfied:
the impedance of the main channel MOS tube corresponding to the overcurrent protection current range is the impedance of the main channel MOS tube when the main channel MOS tube is switched off, and the overcurrent protection current range refers to the current range larger than an overcurrent protection point;
for at least part of the current range, the lower limit value of the current range is smaller, and the impedance of the corresponding main channel MOS tube is larger;
for at least part of the current range, the smaller the upper limit value of the current range is, the larger the impedance of the corresponding main channel MOS tube is.
According to a second aspect of the present invention there is provided an electronic device comprising the channel switch impedance adjustable power supply circuit of the first aspect and its alternatives.
In the power supply circuit with the adjustable channel switch impedance and the electronic equipment, because the source-drain voltages of the second MOS tube and the main channel MOS tube with the same parameters are configured to be the same, and the grid electrodes are connected together, the voltage of the detection resistor can be ensured to be matched with the current of the load, so that the determination of the load current is convenient to realize under the condition that the current detection resistor is not connected in series with the main channel.
Meanwhile, as the gate-source voltages of the first MOS tube and the main channel MOS tube with the same parameters are configured to be the same, the control module adjusts the source-drain current of the first MOS tube, so that the impedance of the first MOS tube can be adjusted, further, the impedance formed by the N main channel MOS tubes can be adjusted, various circuit requirements can be met by adjusting the main channel impedance, for example, the main channel is turned off, the impedance is increased and decreased, and the like. Furthermore, based on the mechanism of main channel impedance adjustment, the alternative scheme of the invention can realize the turn-off control during overcurrent, and can also be used for realizing the effective control of the heat loss of the main channel, thereby being convenient for achieving lower heat loss, and being convenient for keeping the voltage of the MOS tube of the main channel in a reasonable range, thereby achieving better current detection precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a first schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 3 is a third schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 4 is a fourth schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 5 is a fifth schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 6 is a sixth schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 7 is a seventh schematic diagram illustrating a configuration of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
FIG. 8 is a first schematic circuit diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention;
fig. 9 is a second circuit schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the invention.
Description of reference numerals:
1-main channel MOS tube;
2-a control module;
3-an execution module;
31-a first MOS transistor;
32-a first current source;
33-a first holding unit;
331-a second current source;
34-a gate source voltage replica unit;
4-a detection module;
41-a second MOS tube;
42-a second holding unit;
421-third MOS tube;
rload-load;
rdet-detection resistance;
rref-reference resistance;
AMP 1-first operational amplifier;
AMP 2-second operational amplifier;
pr-a first MOS tube;
pc-a second MOS tube;
p1, … …, Pn-main channel MOS tube;
pd-third MOS tube;
nr-a first MOS tube;
nc-a second MOS tube;
n1, … …, Nn-main channel MOS tube.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a first schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention.
Referring to fig. 1, a power circuit with adjustable channel switch impedance includes: the device comprises N main channel MOS tubes 1, a control module 2, an execution module 3 and a detection module 4, wherein N is an integer greater than or equal to 1; the execution module 3 comprises a first MOS transistor 31; the detection module 4 includes a detection resistor Rload and a second MOS transistor 41.
The main channel may also be characterized as a switch channel, a main current switch channel, etc., which may be understood as a channel from a power source to a load.
The first end of the second MOS transistor 41 and the first end of the main channel MOS transistor 1 are both connected to a first power source VIN, and then the voltages of the first end of the second MOS transistor 41 and the first end of the main channel MOS transistor 1 may be the same, the second end of the main channel MOS transistor 1 is connected to ground through a load Rload, and the second end of the second MOS transistor 41 is connected to ground through the detection resistor Rdet directly or indirectly.
The first MOS 31 is directly or indirectly connected between an execution-side power supply VDD and ground, where the execution-side power supply VDD may be the first power supply VIN or may be a second power supply different from the first power supply VIN.
The first MOS transistor 31 may be a PMOS or an NMOS;
when the main channel MOS transistor 1 is a PMOS, the first end of the main channel MOS transistor 1 may be a source, and correspondingly, the second end of the main channel MOS transistor 1 may be a drain, the first end of the second MOS transistor 41 is a source, and the second end of the second MOS transistor 41 is a drain;
when the main channel MOS transistor 1 adopts an NMOS, the first end of the main channel MOS transistor 1 may be a drain, correspondingly, the second end of the main channel MOS transistor 1 may be a source, the first end of the second MOS transistor 41 is a drain, and the second end of the second MOS transistor 41 is a source.
Besides, the MOS transistor mentioned above can be made of PMOS and NMOS, and can be made of other switching transistors with similar functions made of gan or sin process.
Regardless of the type, the MOS transistor according to the embodiment of the present invention satisfies the following conditions:
the gate of the second MOS transistor 41 and the gate of the main channel MOS transistor 1 are connected to the same circuit location, and further, the gate potentials of the two (or, as understood, the voltage between the gate and the ground) are the same, and the gate potential of the first MOS transistor 31 may also be the same, for example, directly or indirectly connected together; and:
the gate-source voltage of the main channel MOS transistor 1 is configured to be consistent with the gate-source voltage of the first MOS transistor 31, and the source-drain voltage of the main channel MOS transistor 1 is configured to be consistent with the source-drain voltage of the second MOS transistor 41.
The gate-source voltage can be understood as the voltage between the gate and the source of the corresponding MOS transistor, and the source-drain voltage can be understood as the voltage between the source and the drain of the corresponding MOS transistor.
In addition, the number of the first MOS transistor 31 and the second MOS transistor 41 may be one, or may be plural, and if the number of the first MOS transistors 31 is plural, the plural first MOS transistors 31 may be connected in parallel; if the number of the second MOS transistors 41 is plural, the plural second MOS transistors 41 may be connected in parallel with each other.
Any improvement or existing solution in the art that can make the circuit voltage consistent does not depart from the description of the embodiments of the present invention, for example, corresponding potential nodes may be connected to the same circuit unit so as to be consistent under the control of the circuit unit (for example, the second holding unit referred to later), and for example, corresponding potential nodes may be connected to each other so as to make the voltage consistent.
In the embodiment of the present invention, the parameters of the main channel MOS transistor 1, the first MOS transistor 31 and the second MOS transistor 41 are the same; the parameters of the MOS transistors are the same, and further, the formed impedances (impedances between the source and the drain) are the same under the condition that the gate-source voltages are the same.
The control module 2 is connected to the detection resistor Rdet, and may specifically be connected to an ungrounded end of the detection resistor Rdet, and meanwhile, the embodiment of the present invention does not exclude a scheme in which both ends of the detection resistor Rdet are connected to the control module 2.
In the above scheme, it can be ensured that the voltage of the detection resistor can be matched with the current of the load, and further, the determination of the load current can be conveniently realized under the condition that the current detection resistor is not connected in series with the main channel.
In the embodiment of the present invention, the control module 2 is configured to:
detecting the voltage drop information at two ends of the detection resistor; the voltage drop information is capable of characterizing a current of the load;
according to the voltage drop information, adjusting the current between the source and the drain of the first MOS transistor to adjust the source-drain voltage of the first MOS transistor, so that the gate-source voltage of the main channel MOS transistor changes correspondingly, and the impedance formed by the N main channel MOS transistors is adjusted accordingly, which can also be understood as: through the adjustment of the source leakage current of the first MOS tube, the voltage between the source electrode and the drain electrode (or between the drain electrode and the source electrode) of the first MOS tube is adjusted, and the grid source voltage of the main channel is changed, so that the aim of adjusting the impedance formed by the N main channel MOS tubes is fulfilled.
Because the gate-source voltage of the first MOS tube with the same parameters is configured to be the same as the gate-source voltage of the main channel MOS tube, the control module adjusts the source-drain current of the first MOS tube, so that the impedance of the first MOS tube can be adjusted, further, the impedance formed by the N main channel MOS tubes can be adjusted, various circuit requirements can be met by adjusting the main channel impedance, for example, the main channel is turned off, the impedance is increased and decreased, and the like. Furthermore, based on the mechanism of main channel impedance adjustment, the alternative scheme of the invention can realize the turn-off control during overcurrent, and can also be used for realizing the effective control of the heat loss of the main channel, thereby being convenient for achieving lower heat loss, and being convenient for keeping the voltage of the MOS tube of the main channel in a reasonable range, thereby achieving better current detection precision.
Specifically, the control module 2 adjusts the current between the source and the drain of the first MOS transistor according to the voltage drop information to adjust the source-drain voltage of the first MOS transistor, so that the gate-source voltage of the main channel MOS transistor changes correspondingly, and when the impedance formed by the N main channel MOS transistors is adjusted accordingly, the control module is specifically configured to:
determining the current of the load according to the voltage drop information;
according to the current range of the current of the load and the corresponding relation between different current ranges and different impedances of the main channel MOS tube, adjusting the current between the source electrode and the drain electrode of the first MOS tube so as to enable the impedance of the main channel MOS tube to be in the impedance corresponding to the current range;
in an example, for at least partial correspondence relationship among the main channel MOS transistors, the smaller the lower limit value of the current range is, the larger the impedance of the corresponding main channel MOS transistor is, and/or: the smaller the upper limit value of the current range is, the larger the impedance of the corresponding main channel MOS tube is.
The at least partial correspondence may be, for example, other current ranges excluding an overcurrent protection current range referred to later, wherein an upper limit value and a lower limit value of the at least partial correspondence may be much smaller than an overcurrent protection point.
Therefore, in the control process, aiming at different load currents, the impedance can be matched with the load currents, so that the voltage of the main channel MOS tube in the main channel can be in a proper range, and the problem that accurate detection cannot be carried out when the current is small due to the adoption of the current detection resistor with a fixed resistance value is avoided.
In one example, each current range can include, for example, a first current range of 1-10A, a second current range of 0.1-1A, and a third current range of 0.010-0.1A;
the impedance of the main channel MOS transistor corresponding to the first current range (1-10A) may be, for example, 10m Ω;
the impedance of the main channel MOS transistor corresponding to the second current range (0.1-1A) can be, for example, 100m Ω;
the impedance of the main channel MOS transistor corresponding to the third current range (0.01-0.1A) may be, for example, 1 Ω.
It can be seen that in the above example, the ratio between the upper limits of the current ranges is the same as the ratio between the corresponding impedances, and the ratio between the lower limits of the current ranges is the same as the ratio between the corresponding impedances.
In one example, the current range may include an overcurrent protection current range corresponding to the overcurrent protection point (e.g., a current range greater than the overcurrent protection point), and the impedance corresponding to the overcurrent protection current range may be understood as the impedance when the main channel MOS transistor is turned off.
In specific examples, some or all of the above current ranges may be used, and any other current ranges may be used or combined without being limited to the above examples.
Specifically, if the current ranges exemplified above are combined, then: if the load current is extremely large, namely the load current exceeds an overcurrent protection point, the main channel can be cut off, so that the impedance of the MOS tube of the main channel is extremely large; if the load current is large but not exceeding the overcurrent protection point, the impedance of the first MOS tube can be controlled to be extremely small, so that the voltage drop of the system on the switch channel is extremely small, and the heat loss is reduced. When the load current is gradually reduced, the impedance of the main channel MOS tube can be gradually increased by adjusting the first MOS tube, so that the obtained voltage value of the main channel MOS tube is kept in a reasonable range, and the detection accuracy of the load current is ensured.
Compared with the prior art, for example, in the application of dc fast charging control of some small-capacity batteries or detection of insertion or extraction of some electric devices, current judgment needs to be performed in real time, and if the detection is inaccurate, control is poor or detection misjudgment is likely to be caused, even in the application of measuring a larger current, the current measurement accuracy cannot be improved by the conventional method like the method capable of adjusting the current detection impedance in multiple stages.
FIG. 2 is a second schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention; FIG. 3 is a third schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention; fig. 4 is a schematic diagram of a configuration of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention.
In one embodiment, referring to fig. 2 and fig. 3, the execution module 3 further includes a first holding unit 32; the first holding unit 32 is further connected to the drain of the first MOS transistor 31, and the first holding unit 32 is configured to: and controlling the drain of the first MOS tube 31 to be kept at a first reference voltage.
The first holding unit 32 may be any existing or improved circuit unit capable of maintaining the drain voltage of the first MOS transistor 31.
The first reference voltage may be any preset or adjustable voltage.
It can be seen that, in order to control the current of the first MOS transistor 31, in one scheme, the current of the line where the first MOS transistor is located may be directly adjusted, and in another scheme, the current may be controlled and changed by adjusting the voltage at a certain position in the line, for example: since the source-drain impedance of the first MOS transistor is related to both the current and the voltage thereof, further, by adjusting the variation of the first reference voltage, the current between the source and the drain of the first MOS transistor 31 can also be adjusted, that is: when the control module adjusts the current between the source electrode and the drain electrode of the first MOS transistor, the control module is specifically configured to: adjusting the first reference voltage. In other examples, voltages at other locations in the line may be adjusted.
In one embodiment, in order to directly adjust the current of the line, referring to fig. 3, the first holding unit 3 includes a first current source 33.
The first current source 33 is connected between the execution side power supply VDD and the ground after being connected in series with the first MOS transistor 31, the first current source 33 is connected to the drain of the first MOS transistor 31, and the control end of the first current source is further connected to the control module 2.
Based on the above circuit configuration, the control module 2, when adjusting the current between the source and the drain of the first MOS transistor 31, is specifically configured to: the current of the first current source 33 is regulated.
Wherein, according to the type of the first MOS transistor 31, the connection position of the first current source 33 may be changed accordingly, for example: when the first MOS transistor 31 is a PMOS, the first current source may be connected between the drain of the first MOS transistor 31 and ground; when the first MOS transistor 31 is an NMOS, the first current source can be understood between the drain of the first MOS transistor 31 and the execution-side power supply VDD. In addition, in the circuit, other devices may be connected in series or in parallel, and as long as the current change of the first current source 33 can change the impedance of the first MOS transistor 31, the scope of the above scheme is not deviated.
Referring to fig. 4 and fig. 5, in one embodiment, the first holding unit 32 includes a first operational amplifier AMP1, a first input terminal of the first operational amplifier AMP1 is connected to the drain of the first MOS transistor 31, and a second input terminal of the first operational amplifier AMP1 is connected to the first reference voltage; the output end of the first operational amplifier AMP1 is connected to the gate of the first MOS transistor 31, so that the voltage of the drain of the first MOS transistor is kept at the first reference voltage through the control of the first MOS transistor 31.
The first input terminal of the first operational amplifier AMP1 may be, for example, a positive terminal, and the second input terminal may be, for example, an inverting terminal, and in other examples, the first input terminal may also be an inverting terminal, and the second input terminal may also be a positive terminal.
In a specific implementation process, referring to fig. 4, the first holding unit 33 further includes a second current source 321 and a reference resistor Rref, the second current source 321 and the reference resistor Rref are connected in series and then connected between the execution-side power supply and the ground, and a second input terminal of the first operational amplifier AMP1 is connected between the second current source 321 and the reference resistor Rref to collect a voltage between the second current source 321 and the reference resistor Rref as the first reference voltage.
When adjusting the first reference voltage, the control module 2 is specifically configured to adjust at least one of:
the resistance value of the reference resistor Rref;
the current of the second current source 321;
the voltage of the potential between the second current source 321 and the reference resistor 32 (i.e., the voltage between the potential and ground).
It can be seen that the above scheme utilizes the voltage division of the second current source 321 and the reference resistor Rref to provide the first reference voltage, and further, based on the circuit shown in fig. 4, the first reference voltage can be adjusted in any one of the above manners.
In other embodiments, if the first reference voltage is provided in other manners, the manner of adjusting the first reference voltage may also be changed accordingly, for example: if the first reference voltage is provided by dividing two or more resistors, then: the first reference voltage can also be adjusted by adjusting the resistance value or the voltage of any at least one resistor used for voltage division.
No matter which way is used to provide the first reference voltage, no matter which way is used to adjust the first reference voltage, or whether the first reference voltage is adjusted, do not depart from the description of the embodiments of the present invention.
In addition, the above manner of providing the first reference voltage may be applied to a scheme that the first MOS transistor 31 adopts a PMOS, and may also be applied to a scheme that the first MOS transistor 31 adopts an NMOS.
In one embodiment, in order to make the gate-source voltage of the first MOS transistor 31 consistent with the gate-source voltage of the main channel MOS transistor 1, the corresponding gates and/or sources may be connected together. Furthermore, the gate of the first MOS transistor 31 and the gate of the main channel MOS transistor 1 are connected together.
In a specific scheme, the source of the first MOS transistor 31 and the source of the main channel MOS transistor 1 can be connected together, so that the gate-source voltages of the two transistors are kept consistent.
Taking the first MOS transistor 31 and the main channel MOS transistor 1 both using PMOS as an example, the execution-side power supply VDD may be the first power supply, the drain of the first MOS transistor 31 is directly or indirectly grounded (for example, grounded via the first current source), the first end of the main channel MOS transistor 1 is the source of the main channel MOS transistor 1, and the second end of the main channel MOS transistor 1 is the drain of the main channel MOS transistor 1.
In the case that the first MOS transistor 31 and the main channel MOS transistor 1 both use NMOS, the source of the first MOS transistor 31 and the source of the main channel MOS transistor 1 may also be connected together, so that the gate-source voltages of the two transistors are kept the same. In another specific scheme, a configuration shown in fig. 5 may be adopted to make the gate-source voltage of the first MOS transistor 31 and the gate-source voltage of the main channel MOS transistor 1 consistent.
Fig. 5 is a schematic diagram of a configuration of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention.
Referring to fig. 5, the execution module 3 further includes a gate-source voltage replication unit 34. The gate-source voltage replica cell 34 therein can also be characterized as: VGS Copy.
The two ends of the first side of the gate-source voltage copying unit 34 are respectively connected with the source and the gate of the first MOS transistor 31, and the voltage of the two ends of the second side of the gate-source voltage copying unit 34 is consistent with the gate-source voltage of the main channel MOS transistor; specifically, the reset units may be connected together by direct connection, or may be implemented by a reset unit (for example, a second reset unit described later).
The gate-source voltage copying unit 34 is configured to keep the voltage across the first side and the voltage across the second side consistent, so that the gate-source voltage of the first MOS transistor 31 and the gate-source voltage of the main channel MOS transistor 1 are kept consistent.
The above gate-source voltage replica unit 34 may be any existing or modified circuit unit that can make the voltage difference between the two terminals of the first side and the voltage difference between the two terminals of the second side consistent.
It can be seen that no matter how the first MOS transistor 31 and the main channel MOS transistor 1 are made to have the same far-field voltage, the scope of the embodiment of the present invention is not departed.
FIG. 6 is a sixth schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention; fig. 7 is a seventh schematic diagram illustrating a configuration of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention.
Referring to fig. 6, the detecting module 4 further includes a second holding unit 42.
The second holding unit 42 is configured to control the second end of the second MOS transistor 41 to be consistent with the second end of the main channel MOS transistor 1 in voltage.
The second holding unit 42 may have a similar circuit configuration to that of the first holding unit 32, or may have another circuit configuration different from that of the first holding unit.
Specifically, referring to fig. 7, the second holding unit 42 includes a second operational amplifier AMP2 and a third MOS transistor 421.
When the third MOS transistor 421 adopts a PMOS, the third MOS transistor 421 is connected in series between the second end of the second MOS transistor 41 and the detection resistor Rdet; when the third MOS transistor 421 adopts an NMOS, the third MOS transistor 421 is connected in series between the detection resistor Rdet and the ground.
Two input ends of the second operational amplifier AMP2 are respectively connected to the second end of the second MOS transistor 41 and the second end of the main channel MOS transistor; the output end of the second operational amplifier AMP2 is connected to the gate of the third MOS transistor 421, so that the voltage of the second end of the second MOS transistor 41 is kept consistent with the voltage of the second end of the main channel MOS transistor 1 by controlling the third MOS transistor 421.
Meanwhile, when the first MOS transistor uses an NMOS, the circuit configuration shown in fig. 7 is combined with the circuit configuration shown in fig. 5, and then: the second side of the gate-source voltage duplicating unit 34 is further connected to the gate and the second end of the second MOS transistor 41, and further, when the second holding unit holds the voltage of the second end of the second MOS transistor 41 to be consistent with the voltage of the second end of the main channel MOS transistor 1 through the second holding unit 42, the voltage between the gate and the second end of the main channel MOS transistor 1 and the voltage between the two ends of the second side of the gate-source voltage duplicating unit 34 can also be consistent, and further, the gate-source voltage of the first MOS transistor 31, the gate-source voltage of the main channel MOS transistor 1, and the gate-source voltage of the second MOS transistor 41 can be consistent.
In addition, the third MOS transistor 421 may adopt a PMOS transistor or an NMOS transistor, and correspondingly, when different MOS transistors are adopted, the connection positions of the two input terminals with respect to the second operational amplifier may be opposite.
In combination with the above-mentioned solutions, a specific solution (as shown in fig. 8) in which the main channel MOS transistor, the first MOS transistor, and the second MOS transistor adopt PMOS, and another specific solution (as shown in fig. 9) in which the main channel MOS transistor, the first MOS transistor, and the second MOS transistor adopt PMOS may be formed.
FIG. 8 is a first schematic circuit diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the present invention; fig. 9 is a second circuit schematic diagram of a power circuit with adjustable channel switch impedance according to an embodiment of the invention.
With respect to the physical quantities therein:
the current of the load may be characterized as I0, the current of the sense resistor Rdet may be characterized as I1, the output voltage of the first operational amplifier AMP1 may be characterized as OUT1, and the output voltage of the second operational amplifier AMP2 may be characterized as OUT 2; the current of the second current source 321 may be characterized as Iref, the current of the first current source 33 may be characterized as I2; the source-drain impedance of the first MOS tube is characterized as Rds2, the source-drain impedance of the second MOS tube is characterized as Rds1, the source-drain impedance of the main channel MOS tube is characterized as Rds, the impedance of the N main channel MOS tubes connected in parallel is characterized as Rds0, the drain voltage of the first MOS tube is characterized as Vd2, the drain voltage of the second MOS tube is characterized as Vd1, and the drain voltage of the main channel MOS tube is characterized as Vd 0. Meanwhile, the reference resistor Rref, the detection resistor Rdet and the load Rload can also represent the resistance values.
Referring to fig. 8, the main channel MOS, the first MOS and the second MOS are PMOS, so the first MOS can be characterized as Pr, the second MOS as Pc, the main channel MOS as P1, … …, Pn, and the third MOS as Pd.
Main channel MOS transistors P1 to Pn (i.e., N identical PMOS) are connected in parallel to form a main current channel, where impedance of the main current channel is Rds0, and N is an integer greater than or equal to 1, there are:
Rds0＝Rds/N。
since the first MOS transistor Pr is the same as the PMOS transistor, then:
Rds2＝Rds＝N*Rds0。
the combination of the first current source with current I2, the second current source with current Iref, the resistor Rref and the first operational amplifier AMP1 together form a rough circuit for the execution block 4 that regulates the main current channel switching impedance Rds 0.
The control module 2 can perform a decision operation based on the obtained voltage Vdet of the sensing resistor Rdet and then Adjust the current I2 of the first current source, which is indicated in fig. 8 by the marked arrow of Adjust I2.
According to the working characteristics of the operational amplifier circuit, the circuit has the following functions after the balance is adjusted: vd2 is Vref, Vd2 is VIN-I2 is Rds2, Vref is VIN-Iref is Rref, so the following:
I2*Rds2＝Iref*Rref。
considering that the output voltage OUT1 of the first operational amplifier AMP1 drives the gate of the first MOS transistor Pr and simultaneously drives the gates of each of the N main channel MOS transistors P1 to Pn in parallel, and the Source terminals (Source terminals) of these PMOS transistors are connected to the first power supply VIN, and at the same time, ensuring that the parameters of the first MOS transistor Pr and the N PMOS transistors of the main channel in fig. 8 are all made to be consistent, Rds2 is N Rds0, and combining equation I2 Rds2 is Iref Rds ref, it can be obtained:
Rds0＝Iref*Rref/(I2*N)。
for simplicity, in the design, N may be fixed after selecting a suitable value, and the reference resistor Rref and the current Iref of the second current source may also be fixed after selecting a suitable value, then the control module may adjust Rds0 by adjusting I2, that is: the adjustment of the channel impedance of the main current switch is realized.
With respect to the detection module 4, the control module 2 can decide how to adjust the value of I2 according to the voltage magnitude of Vdet in fig. 8.
In fig. 8, a mirror circuit is constructed by the second MOS transistor Pc, the second operational amplifier AMP2, the third MOS transistor Pd, and the parallel main channel MOS transistors P1 to Pn, and according to the operating characteristics of the second operational amplifier AMP2, Vd0 is Vd1 when the circuit is in stable operation, and the source-drain voltages of the second MOS transistor Pc are VIN-Vd1 is VSD1, and the source-drain voltages of P1 to Pn are VIN-Vd0 is VSD0, so that VSD0 is VIN-Vd0 is VSD1 is VIN-1, that is, the source-drain voltages of both are equal, and the gate-source voltages VGS of both are OUT1-VIN, and at the same time, it is ensured that the parameters of the PMOS transistors in the second diagram and the N PMOS transistors of the main current channel are identical, and when the gate-source voltages of both are the same, Rds1 is Rds, Rds0 is Rds:
Rds1＝N*Rds0。
the source-drain voltages of the two are combined to be equal, namely VSD1 is VSD0, and: VSD0 ═ I0 × Rds0, VSD1 ═ I1 × Rds 1;
so, I0 ═ N × I1 is available;
and because Vdet ═ I1 × Rdet (where Rdet can be fixed by selecting a suitable resistance), we can obtain:
I0＝N*Vdet/Rdet。
therefore, when the control module 2 detects Vdet, the current value of the main current channel, i.e. I0, can be obtained by using the equation I0 ═ N × Vdet/Rdet.
As can be seen, the combination: the Rds0 ═ Iref Rref/(I2 × N) and I0 ═ N × Vdet/Rdet, the control module 2 can adjust the size of I2 according to the obtained size of I0, wherein the conversion or judgment logic from I0 to I2 can be determined according to actual needs, and further the adjustment of the main current switch channel impedance Rds0 can be realized.
In one example, when I0 is 1 to 10A, I2 may be adjusted to a certain value so that Rds0 is 10m Ω, and I0 is 0.1 to 1A, I2 may be adjusted to a certain value so that Rds0 is 100m Ω, and I0 is 0.01 to 0.1A, I2 may be adjusted to a certain value so that Rds0 is 1 Ω, and thus, according to reasonable needs, the main current channel switch impedance Rds0 may be appropriately adjusted according to the current value I0 passed at that time, so as to keep VSD0 within an appropriate voltage value range during normal current detection operation, and further improve the detection accuracy of the current I0 in a larger operating range.
Referring to fig. 9, the main channel MOS, the first MOS and the second MOS are NMOS, wherein the first MOS can be characterized as Nr, the second MOS can be characterized as Nc, the main channel MOS can be characterized as N1, … …, Nn, and the third MOS can be characterized as Pd if PMOS, or Nd if NMOS.
Referring to fig. 9, most of the circuit structure thereof can be referred to fig. 8, and the differences between PMOS and NMOS are comprehensively considered. Therefore, the following emphasizes the differences between fig. 9 and fig. 8.
In consideration of the characteristics of NMOS gate driving, the gate-source voltage replica unit 34 is added to fig. 9 in order to ensure that the gate-source driving voltage of the first MOS transistor Nr, i.e., VGS and the second MOS transistor Nc, and the gate-source driving voltages of the main channel MOS transistors N1 to Nn can be kept uniform. The first reference voltage at the inverting terminal of the first operational amplifier AMP1 in fig. 9 is not provided by the circuit composed of the second current source and the reference resistor Rref shown in fig. two, but is directly provided by the voltage source Vref.
In the circuit shown in fig. 9, Rds2 ═ Rds1 ═ N × Rds 0; i0 ═ N × I1, and Vref ═ I2 × Rds2, so that: rds0 ═ Vref/(I2 × N).
In addition, since Vdet — I1 × Rdet and I0 — N × Vdet/Rdet, the control module 2 may obtain I0 according to the measured Vdet and the predetermined N and Rdet, and make an appropriate decision to control the adjustment of I2 according to the current magnitude of I0, so that Rds0 varies to meet the application requirement, for example:
when I0 is particularly large, i.e. when I0 exceeds the overcurrent protection point, the main current channel can be shut off so that Rds0 is very large, e.g. I0 is very large, but not exceeding the overcurrent protection point, I2 can be adjusted so that Rds0 is very small and the voltage drop of the system over the switching channel is very small, so as to reduce the heat loss. If I0 becomes smaller, Rds0 can be made larger by adjusting I2 so that the voltage value obtained by I0 Rds0 is kept within a reasonable range to ensure the detection accuracy of I0 current.
As can be seen, in the above scheme:
by adjusting an executing module of the impedance of the main current switch channel, namely by constructing an MOS tube which is the same as each MOS tube of the main current switch channel, and ensuring that the MOS tube and the MOS tube of the main current switch channel always adopt the same gate-source driving Voltage (VGS);
the circuit for adjusting the gate-source driving voltage of the main current switch channel MOS tube is achieved by adjusting the first current source (namely, the current source with the current I2), and the adjustment of the impedance of the main current switch channel is further achieved through the circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (13)

1. A channel switch impedance adjustable power supply circuit, comprising: the device comprises N main channel MOS tubes, a control module, an execution module and a detection module, wherein N is an integer greater than or equal to 1; the execution module comprises a first MOS tube; the detection module comprises a detection resistor and a second MOS tube;
the first end of the second MOS tube and the first end of the main channel MOS tube are both connected with a first power supply, the second end of the main channel MOS tube is connected with the ground through a load, and the second end of the second MOS tube is directly or indirectly connected with the ground through the detection resistor; the grid electrode of the second MOS tube and the grid electrode of the main channel MOS tube are connected to the same circuit position, the first MOS tube is directly or indirectly connected between an execution side power supply and the ground, and the execution side power supply is the first power supply or a second power supply different from the first power supply;
the gate-source voltage of the main channel MOS tube is configured to be consistent with the gate-source voltage of the first MOS tube, the source-drain voltage of the main channel MOS tube is consistent with the source-drain voltage of the second MOS tube, and the parameters of the main channel MOS tube, the first MOS tube and the second MOS tube are the same;
the control module is connected with the detection resistor and is used for:
detecting the voltage drop information at two ends of the detection resistor; the voltage drop information is capable of characterizing a current of the load;
and adjusting the current between the source electrode and the drain electrode of the first MOS tube according to the voltage drop information so as to adjust the source-drain voltage of the first MOS tube, so that the gate-source voltage of the main channel MOS tube is correspondingly changed, and the impedance formed by the N main channel MOS tubes is adjusted accordingly.
2. The channel switch impedance adjustable power supply circuit of claim 1, wherein the execution module further comprises a first holding unit; the first holding unit is further connected to a drain electrode of the first MOS transistor, and the first holding unit is configured to: and controlling the drain electrode of the first MOS tube to be kept at a first reference voltage.
3. The channel switch impedance adjustable power supply circuit of claim 2, wherein the first holding unit comprises a first current source;
the first current source is connected between the execution side power supply and the ground after being connected with the first MOS tube in series, the first current source is connected with the drain electrode of the first MOS tube, and the control end of the first current source is also connected with the control module;
when the control module adjusts the current between the source electrode and the drain electrode of the first MOS transistor, the control module is specifically configured to: adjusting a current of the first current source.
4. The power supply circuit with adjustable channel switch impedance of claim 2, wherein the first holding unit comprises a first operational amplifier, a first input end of the first operational amplifier is connected with the drain of the first MOS transistor, and a second input end of the first operational amplifier is connected to the first reference voltage; the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, so that the voltage of the drain electrode of the first MOS tube is kept at the first reference voltage through the control of the first MOS tube.
5. The power supply circuit with adjustable channel switch impedance of claim 4, wherein the first holding unit further comprises a second current source and a reference resistor, the second current source and the reference resistor are connected in series and then connected between the execution-side power supply and ground, and the second input terminal of the first operational amplifier is connected between the second current source and the reference resistor, so as to collect a voltage of a potential between the second current source and the reference resistor as the first reference voltage.
6. The power supply circuit with adjustable channel switch impedance of claim 2, wherein the control module, when adjusting the current between the source and the drain of the first MOS transistor, is specifically configured to: adjusting the first reference voltage.
7. The power supply circuit with adjustable channel switch impedance of any one of claims 1 to 6, wherein the main channel MOS transistor and the first MOS transistor are both PMOS transistors, the execution side power supply is the first power supply, a drain electrode of the first MOS transistor is directly or indirectly grounded, a first end of the main channel MOS transistor is a source electrode of the main channel MOS transistor, and a second end of the main channel MOS transistor is a drain electrode of the main channel MOS transistor.
8. The power supply circuit with the adjustable channel switch impedance of any one of claims 1 to 6, wherein the main channel MOS transistor and the first MOS transistor are both NMOS, a first end of the main channel MOS transistor is a drain electrode of the main channel MOS transistor, a second end of the main channel MOS transistor is a source electrode of the main channel MOS transistor, the drain electrode of the first MOS transistor is connected to the execution side power supply, and the source electrode of the first MOS transistor is directly or indirectly connected to ground.
9. The channel switch impedance adjustable power supply circuit according to any one of claims 1 to 6, wherein the execution module further comprises a gate-source voltage replication unit;
the two ends of the first side of the grid-source voltage copying unit are respectively connected with the source electrode and the grid electrode of the first MOS tube, and the voltage of the two ends of the second side of the grid-source voltage copying unit is consistent with the grid-source voltage of the main channel MOS tube;
the grid-source voltage copying unit is configured to enable the voltage across the first side and the voltage across the second side to be consistent, so that the grid-source voltage of the first MOS tube and the grid-source voltage of the main channel MOS tube are consistent.
10. The channel switch impedance adjustable power supply circuit according to any one of claims 1 to 6, wherein the detection module further comprises a second holding unit;
the second holding unit is used for controlling the second end of the second MOS tube to be consistent with the voltage of the second end of the main channel MOS tube.
11. The power circuit of claim 10, wherein the second holding unit comprises a second operational amplifier and a third MOS transistor;
the third MOS tube is connected in series between the second end of the second MOS tube and the detection resistor or between the detection resistor and the ground, and two input ends of the second operational amplifier are respectively connected with the second end of the second MOS tube and the second end of the main channel MOS tube; the output end of the second operational amplifier is connected with the grid electrode of the third MOS tube, so that the voltage of the second end of the second MOS tube is consistent with that of the second end of the main channel MOS tube through the control of the third MOS tube.
12. The power supply circuit with the adjustable channel switch impedance of any one of claims 1 to 6, wherein the control module is configured to, when adjusting, according to the voltage drop information, a current between a source and a drain of the first MOS transistor to adjust a source-drain voltage of the first MOS transistor, so that a gate-source voltage of the main channel MOS transistor changes correspondingly, and an impedance formed by the N main channel MOS transistors is adjusted accordingly, specifically:
determining the current of the load according to the voltage drop information;
according to the current range of the current of the load and the corresponding relation between different current ranges and different impedances of the main channel MOS tube, adjusting the current between the source electrode and the drain electrode of the first MOS tube so as to enable the impedance of the main channel MOS tube to be in the impedance corresponding to the current range;
in the correspondence, at least one of the following is satisfied:
the impedance of the main channel MOS tube corresponding to the overcurrent protection current range is the impedance of the main channel MOS tube when the main channel MOS tube is switched off, and the overcurrent protection current range refers to the current range larger than an overcurrent protection point;
for at least part of the current range, the lower limit value of the current range is smaller, and the impedance of the corresponding main channel MOS tube is larger;
for at least part of the current range, the smaller the upper limit value of the current range is, the larger the impedance of the corresponding main channel MOS tube is.
13. An electronic device comprising the channel switch impedance adjustable power supply circuit of any one of claims 1 to 12.
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