CN111446759A - New energy battery management system and electric automobile - Google Patents

New energy battery management system and electric automobile Download PDF

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Publication number
CN111446759A
CN111446759A CN202010272276.0A CN202010272276A CN111446759A CN 111446759 A CN111446759 A CN 111446759A CN 202010272276 A CN202010272276 A CN 202010272276A CN 111446759 A CN111446759 A CN 111446759A
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CN
China
Prior art keywords
resistor
port
battery
capacitor
isolation
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Withdrawn
Application number
CN202010272276.0A
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Chinese (zh)
Inventor
江丽
赵红霞
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Shenzhen Jing Fang Ying Technology Co ltd
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Shenzhen Jing Fang Ying Technology Co ltd
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Priority to CN202010272276.0A priority Critical patent/CN111446759A/en
Publication of CN111446759A publication Critical patent/CN111446759A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L58/00—Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles
    • B60L58/10—Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries
    • B60L58/12—Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries responding to state of charge [SoC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M2010/4278—Systems for data transfer from batteries, e.g. transfer of battery parameters to a controller, data transferred between battery controller and main controller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries

Abstract

The invention provides a battery management system and an electric automobile. The battery management system includes: the system comprises a central processing unit, a battery controller and a network transceiver module, wherein the network transceiver module is arranged between the central processing unit and the battery controller, the central processing unit comprises a processing chip MPC560xB, an MPC5746R or an MPC5744P, and the reliability of the battery management system is effectively improved.

Description

New energy battery management system and electric automobile
Technical Field
The application relates to the technical field of electric automobiles, in particular to a battery management system and an electric automobile.
Background
With the development of electric vehicles, the driving range is increasing, which leads to the continuous increase of the number of the storage batteries installed in the vehicle, and in order to manage the storage batteries well, a battery management system is usually installed to monitor and regulate the storage batteries. The battery management system is a core component of the electric automobile and is an important index for ensuring the performance of the electric automobile.
The existing battery management system has poor reliability, even devices are damaged, the transmission of control signals is seriously influenced, and inconvenience and even danger are brought to the driving safety of the electric automobile. Therefore, a battery management system and an electric vehicle are needed to solve the above technical problems in the prior art.
Disclosure of Invention
The application provides a battery management system and an electric automobile, and the reliability of the battery management system is effectively improved.
The technical scheme adopted by the application is as follows: a battery management system, comprising: the system comprises a central processing unit, a battery controller and a network transceiver module, wherein the network transceiver module is arranged between the central processing unit and the battery controller, and the central processing unit comprises a processing chip MPC560xB, MPC5746R or MPC 5744P.
Preferably, the central processing unit further includes a charge and discharge management module, and the processing chip is connected to the battery controller through the charge and discharge management module.
Preferably, the charge and discharge management module includes a charge management unit, and the charge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode (D6) and a resistor (R33) after being connected in parallel is connected to the input end of the driving chip (J4), the anode of the diode (D6) is close to the driving chip (J4), one end of 2 triodes (Q13, Q16) after being connected in parallel is connected in series with the resistor (R36) and then connected to two output ends of the driving chip (J4), the bases of the 2 triodes (Q13, Q16) are close to the driving chip (J4), the collector of an NPN type triode (Q13) is connected to the power interface of the driving chip (J4), capacitors (C24, C126) are respectively connected between the collector of the NPN type triode (Q13) and the power interface of the driving chip (J4) and then grounded, one end of the diode (D3) and the resistor (R29) after being connected in parallel is connected between the emitter of the NPN type triode (Q13) and the emitter of the PNP type triode (Q16), the other end of the diode (D3) connected with the resistor (R29) in parallel is connected to the G pole of the MOS transistor (Q4), and the other end of the diode (D3) connected with the resistor (R29) in parallel is connected with the resistor (R30) in series and then is grounded.
Preferably, the discharge management module includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode (D7) and a resistor (R34) after being connected in parallel is connected to the input end of the driving chip (J5), the anode of the diode (D7) is close to the driving chip (J5), one end of 2 triodes (Q14, Q17) after being connected in parallel is connected in series with the resistor (R36) and then connected to two output ends of the driving chip (J5), the bases of the 2 triodes (Q14, Q17) are close to the driving chip (J5), the collector of an NPN type triode (Q14) is connected to the power interface of the driving chip (J5), capacitors (C25, C125) are respectively connected between the collector of the NPN type triode (Q14) and the power interface of the driving chip (J5) and then grounded, one end of the diode (D4) and the resistor (R31) after being connected in parallel is connected between the emitter of the NPN type triode (Q14) and the emitter of the PNP type triode (Q17), the other end of the diode (D4) connected with the resistor (R31) in parallel is connected to the G pole of the MOS transistor (Q5), and the other end of the diode (D4) connected with the resistor (R31) in parallel is connected with the resistor (R32) in series and then is grounded.
Preferably, said battery controller comprises an integrated circuit MC33771B and a first interference rejection module, said first interference rejection module comprising: 1 MOS pipe, 2 resistances, 1 electric capacity, wherein: one end of a resistor (R128) connected with a capacitor (C117) in series is grounded, the other end of the resistor (R128) connected with the capacitor (C117) in series is connected with the negative electrode of a storage battery (BA 14), one end of a resistor (R123) is connected with the positive electrode of the storage battery (BA 14), the resistor (R123) is connected with the CT-1 port of the integrated circuit MC33771B, the G electrode of the MOS tube (Q32) is connected between the resistor (R128) and the capacitor (C117) and connected with the CB-1 port of the integrated circuit MC33771B, the S electrode of the MOS tube (Q32) is connected between the resistor (R128) and the negative electrode of the power supply (BA 14), and the D electrode of the MOS tube (Q32) is connected between the resistor (R123) and the positive electrode of the storage battery (BA 14).
Preferably, the number of the first interference rejection modules is multiple, the first interference rejection modules are sequentially connected between CT-1 to CT-14 on the same side of the integrated circuit MC33771B, wherein isolation circuits are arranged between the first interference rejection modules, one of the isolation circuits comprises 1 resistor, and the resistors (R122) are respectively connected between the CB-2.1-C port of the integrated circuit MC33771B and the storage battery.
Preferably, the battery controller further comprises a current detection circuit comprising 1 resistor and 2 capacitors, one end of the capacitor (C32) and the resistor (R73) connected in series with the capacitor (C91) is connected to the VANA port of the integrated circuit MC33771B, the AGND port and the ISENSE-port of the integrated circuit MC33771B are respectively connected between the capacitor (C32) and the resistor (R73), the ISENSE-port of the integrated circuit MC33771B is connected to ground, and the ISENSE + port of the integrated circuit MC33771B is connected to the resistor (R73) and the capacitor (C91).
Preferably, the network transceiver module includes an isolation transceiver MC33664 and an isolation circuit, and the isolation circuit includes: 1 transformer, 2 capacitors and 3 resistors, wherein the resistor (R69) is connected in parallel with a primary coil of the transformer (C142) and then respectively connected to a port RDTX + and a port RDTX-of the isolation transceiver MC 33664; the two ends of the resistor (R71), the secondary coil of the transformer (C142) and the resistor (R72) which are sequentially connected in series are connected to the integrated circuit MC33771B, one end of the capacitor (C89) which is grounded is connected between the resistor (R72) and the integrated circuit MC33771B, and one end of the capacitor (C90) is connected between the resistor (R71) and the integrated circuit MC33771B which is grounded.
Preferably, the network transceiver module further comprises a second anti-interference module, wherein the second anti-interference module comprises 11 resistors and 9 capacitors, wherein the resistor (R) is connected to an INTB port of the isolation transceiver MC33664 and the processing chip MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (C) is connected to the INTB port of the isolation transceiver MC33664 after being grounded and the other end thereof is connected to the INTB port of the isolation transceiver MC33664, the resistor (R) is connected to a DATA-RX port of the isolation transceiver MC33664 and the processing chip MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (81) is connected to the DATA-RX port of the isolation transceiver MC33664 after being grounded and the other end thereof is connected to the DATA-RX port of the isolation transceiver MC33664, the resistor (R) is connected to the CSB-RX port of the isolation transceiver MC33664 and the processing chip MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (80) is connected to the MPC 57664 after being grounded and the other end of the MPC 335777 and the resistor (R) is connected to the ground, the resistor (R) of the isolation transceiver MC33664, the isolation transceiver MC 33R) is connected to the ground, the resistor (R) of the isolation transceiver MC33664, the resistor (R) is connected to the resistor (R) and the MPC 57664, the isolation transceiver MC 33r) and the other end of the isolation transceiver MC 33r) are connected to the isolation transceiver MC 33r 33664, the resistor (R) in parallel, the isolation transceiver MC 33r) and the other end of the resistor (R) is connected to the isolation transceiver MC 3357664, the resistor (R) is connected to the resistor (R) and the isolation transceiver MC 33r) in parallel, the resistor (R) and the other end of the isolation transceiver MC 3357664, the isolation transceiver MC 33r) is connected to the isolation transceiver MC 33r) and the isolation transceiver after being connected to the resistor (R) in parallel, the isolation transceiver, the resistor (R) and the other end of the resistor (R) and the resistor (R) is connected to the isolation transceiver after being connected to the resistor (R) in parallel, the other end of the isolation transceiver after being connected to the isolation transceiver MC33664, the resistor (SC 33664, the resistor (R.
The present application also provides an electric vehicle characterized in that it comprises a battery management system according to the above.
By adopting the technical scheme, the application at least has the following technical effects:
the battery management system and electric automobile that this application provided, processing chip MPC560xB, MPC5746R or MPC5744P have higher fail-safe protection function, have effectively improved battery management system's reliability.
Drawings
Fig. 1 provides a block diagram of a battery management system according to a first embodiment of the present application;
FIG. 2 is a block diagram of a battery management system according to a second embodiment of the present application;
FIG. 3 is a block diagram of a battery management system according to three embodiments of the present application;
FIG. 4 is a block diagram of a battery management system according to four embodiments of the present application;
fig. 5 is a block diagram of a battery management system according to five embodiments provided herein;
fig. 6 is a block diagram of a battery management system according to six embodiments provided herein;
FIG. 7 is a block diagram of a battery management system according to a ninth embodiment of the present application;
fig. 8 is a block diagram of a battery management system according to a tenth embodiment of the present application;
fig. 9 is a block diagram of a battery management system according to an eleventh embodiment provided herein;
fig. 10 is a block diagram of a battery management system according to a thirteenth embodiment of the present application.
10-a battery management system; 100-a central processing unit; 110-a network transceiver module; 120-a battery controller; 130-a voltage stabilizing module; 140-voltage isolation transceiver; 20-battery.
Detailed Description
To further clarify the technical measures and effects taken by the present application to achieve the intended purpose, the present application will be described in detail below with reference to the accompanying drawings and preferred embodiments.
The battery management system and the electric automobile provided by the application effectively improve the reliability of the battery management system. The battery management system of the present application and its various parts will be described in detail below.
Example one
As shown in fig. 1, the battery management system 10 provided in the present embodiment includes: the system comprises a central processing unit 100, a battery controller 120 and a network transceiver module 110, wherein the network transceiver module 110 is arranged between the central processing unit 100 and the battery controller 120, and the central processing unit comprises a processing chip MPC560xB, an MPC5746R or an MPC 5744P.
The central processor is responsible for information processing of the battery management system and coordinates cooperation among the modules. The central processor 100 realizes the transmission of information with the battery controller 120 through the network transceiver module 110. The operation of the battery by the battery controller 120 requires the central processor 100 to transmit a corresponding instruction through the network transceiver module 110 to start.
The processing chip MPC560xB, MPC5746R or MPC5744P has a higher fail-safe function as IN the case of the 64 MHz, 32 bit CPU core complex of the memory of the processing chip MPC560xB, MPC5746R or MPC5744P, an additional 64 (4 ×) KB on-chip data flash with ECC up to 20KB for EEPROM emulation with SRAM with ECC fail-safe protection, up to 3 DSPI channels with automatic chip selection generation (up to 8/4/4 chip selection) highly flexible preconditioners allowing both topologies, when not used as a safety port, a second CAN, a highly flexible SMPS preconditioner allowing both topologies, non-inverting buck and standard buck, multiple wake-up sources CAN, L IN and IOS IN low power mode, controlling the charge and discharge of the TC battery 44201 through the ports of the processing chip MPC 63560, MPC5746 IN and MPC 57P, but requiring the processing chip MPC 3, MPC5746 or MPC5744 to send and receive and charge the batteries via the ports of the processing chip MPC 57560, MPC5746, 68542 or MPC5746 to the power transmission module 120 or the next specific examples of the power transmission and power transmission module 5742.
Example two
Based on the first embodiment, the central processing unit 100 of the present embodiment further includes a charge and discharge management module, and the processing chip MPC560xB, MPC5746R, or MPC5744P is connected to the battery controller through the charge and discharge management module. The charge and discharge management module comprises a charge management unit and a discharge management unit, the processing chips MPC560xB, MPC5746R or MPC5744P realize the charge of the battery through the charge management unit, and realize the discharge of the battery through the discharge management unit, but all of the processing chips MPC560xB, MPC5746R or MPC5744P are required to send corresponding commands to the battery controller 120 through the network transceiver module 110. The following description will use the processing chip MPC560xB as the processing chip MPC 5602.
As shown in fig. 2, the charge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D6 and a resistor R33 after being connected in parallel is connected to an input end of a driving chip J4, the anode of the diode D6 is close to a driving chip J4, 2 transistors Q13, one end of a Q16 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J4, 2 transistors Q13, the base of a Q16 is close to the driving chip J4, the collector of an NPN transistor Q13 is connected to a power interface of the driving chip J4, capacitors C24 and C126 are respectively connected between the collector of an NPN transistor Q13 and the power interface of the driving chip J4 and then grounded, one end of a diode D3 after being connected in parallel with a resistor R29 is connected between the emitter of the NPN transistor Q29 and the emitter of the PNP transistor Q29, the other end of the diode D29 after being connected in parallel with the resistor R29 is connected in series with the resistor R29 and then connected to the G pole of the MOS transistor.
As shown in fig. 2, the discharge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D7 and a resistor R34 after being connected in parallel is connected to an input end of a driving chip J5, the anode of the diode D7 is close to a driving chip J5, 2 transistors Q14, one end of a Q17 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J5, 2 transistors Q14, the base of a Q17 is close to the driving chip J5, the collector of an NPN transistor Q14 is connected to a power interface of the driving chip J5, capacitors C25 and C125 are respectively connected between the collector of an NPN transistor Q14 and the power interface of the driving chip J5 and then grounded, one end of a diode D4 after being connected in parallel with a resistor R31 is connected between the emitter of the NPN transistor Q31 and the emitter of the PNP transistor Q31, the other end of the diode D31 after being connected in parallel with the resistor R31 is connected in series with the resistor R31 and then connected to the G pole of the MOS transistor.
The driving chip TC44201, the triodes Q17 and Q14 form a driving circuit to drive the MOS tube APPW34N120, the charging chip TC44201, the triodes Q16 and Q13 form a driving circuit to drive the MOS tube APPW34N120 to discharge, the charging and discharging currents can be adjusted during charging and discharging, once a battery fails, a power supply can be turned off at any time, a discharging path can be turned off at any time when the motor fails, and the safety coefficient is increased.
When the battery is charged, a pin D12 of the processing chip MPC5602 outputs a control signal to the driving chip J4, the driving chip J4 conducts the MOS transistor Q4, the battery is discharged, when the motor works, a pin D14 of the processing chip MPC5602 outputs a control signal to the driving chip J5, and the driving chip J5 conducts the MOS transistor Q5. The charging management unit and the discharging management unit which are designed separately can charge at constant current during charging, so that the service life of the battery is ensured; when the battery is discharged, the electromechanical operation can ensure that the battery can not be over-discharged, so that the situation that the battery is damaged due to over-charging can not occur when the battery is charged for the second time.
EXAMPLE III
As shown in fig. 3, on the basis of the above embodiment, the present embodiment provides that the battery controller in the battery management system includes an integrated circuit MC33771B and a first tamper-resistant module, where the first tamper-resistant module includes: 1 MOS pipe, 2 resistances, 1 electric capacity, wherein: one end of a resistor R128 connected with the capacitor C117 in series is grounded, the other end of the resistor R128 connected with the capacitor C117 in series is connected with the cathode of the battery BA14, one end of a resistor R123 is connected with the anode of the battery BA14, the resistor R123 is connected with the CT-1 port of the integrated circuit MC33771B, the G pole of the MOS tube Q32 is connected between the resistor R128 and the capacitor C117 and connected with the CB-1 port of the integrated circuit MC33771B, the S pole of the MOS tube Q32 is connected between the resistor R128 and the cathode of the power supply BA14, and the D pole of the MOS tube Q32 is connected between the resistor R123 and the anode of the battery BA 14.
The integrated circuit MC33771B is a smart mos lithium ion battery controller IC that performs ADC conversion of differential battery voltage and current, as well as battery coulomb counting and battery temperature measurement, digital transmission of communication information through Serial Peripheral Interface (SPI) or transformer isolation (TP L), automatic over/under voltage and temperature detection routable to fault pins, integrated sleep mode over/under voltage and temperature monitoring, on-board 300mA passive battery balancing and diagnostics, hot-plug capability to detect internal and external faults such as open, short, and leakage, etc., and design support ISO26262, highest ASI L D safety capability.
As shown in fig. 3, the number of the first antijam modules is multiple, the first antijam modules are sequentially connected between CT-1 to CT-14 on the same side of the integrated circuit MC33771B, wherein isolation circuits are arranged between the first antijam modules, one of the isolation circuits includes 1 resistor, and the resistors R122 are respectively connected between the CB-2.1-C port of the integrated circuit MC33771B and the storage battery.
Furthermore, the battery controller also comprises a current detection circuit which comprises 1 resistor and 2 capacitors, one end of each capacitor C32 and one end of each resistor R73 which are connected with the capacitor C91 in series are connected with the VANA port of the integrated circuit MC33771B after being grounded, the AGND port and the ISENSE-port of the integrated circuit MC33771B are respectively connected between the capacitor C32 and the resistor R73, the ISENSE-port of the integrated circuit MC33771B is grounded, and the ISENSE + port of the integrated circuit MC33771B is connected with the resistor R73 and the capacitor C91.
The resistor R73 is used for current detection of battery charging and discharging, the capacitor C91, the capacitor C36, the resistor R43 and the resistor R39 are used for resisting interference, and the MOS tube Q19 is used for balancing voltage in the charging process of the storage battery.
When the integrated circuit MC33771B is conducted through the resistor in the first anti-interference module and the MOS tube, the charging voltage of each battery is ensured to be the same, the charging current of all batteries is the same, and the service life of the batteries is prolonged.
Example four
As shown in fig. 4, on the basis of the foregoing embodiments, this embodiment provides that the network transceiver module in the battery management system includes an isolation transceiver MC33664 and an isolation circuit, where the isolation circuit includes: 1 transformer, 2 capacitors and 3 resistors, wherein the resistor R69 is connected in parallel with the primary coil of the transformer C142 and then respectively connected to a port RDTX + and a port RDTX-of the isolation transceiver MC 33664; two ends of the resistor R71, the secondary coil of the transformer C142 and the resistor R72 which are sequentially connected in series are respectively connected to the integrated circuit MC33771B, one end of the capacitor C89 which is grounded is connected between the resistor R72 and the integrated circuit MC33771B, and one end of the capacitor C90 is connected between the resistor R71 and the integrated circuit MC33771B and then grounded.
For example, the processing chip MPC5602 sends a battery charging command to the isolation transceiver MC33664, and the isolation transceiver MC33664 sends the battery charging command to the battery controller through the port RDTX + and the port RDTX-via the transformer C142, so that the integrated circuit MC33771B performs charging management on the battery.
Isolation transceiver MC33664 may enable isolation of the central processor from the high speed communication network interface, with isolation transceiver MC33664 being converted and sent back to the central processor as an SPI bit stream. The isolated transceiver MC33664 integrates current measurement channels and coulomb counting, which reduces product cost in 48V battery management applications (only one AFE is needed); the synchronous measurement of current and voltage channels can be realized, the impedance of each battery can be given by one-time acquisition, and the accuracy of SoC/SoH estimation is further improved; high speed isolated daisy chain communication or SPI communication, applicable to various topologies (centralized, distributed daisy chain and distributed CAN); high speed (2Mbps) isolated daisy chain differential communication CAN reduce the cost of the product for transferring from CAN to daisy chain without reducing the communication speed; the rapid data acquisition and communication can obtain the battery impedance within 65 microseconds through synchronous voltage and current measurement; the excellent hot plug and random battery connection protection can not damage the battery in advance; the excellent and reliable ESD/EMC performance can save peripheral components, reduce the product cost and save the space of the board card; the SafeaAssure function of the ISO26262 level of the chip has the functions of verification and diagnosis, and can independently configure a bottom-layer drive code, thereby simplifying the development cost of a product.
As shown in fig. 4, the network transceiver module in this embodiment further includes a second anti-interference module including 11 resistors and 9 capacitors, wherein the resistor R is connected to the INTB port of the isolation transceiver MC33664 and the processing chip MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor C is connected to the INTB port of the isolation transceiver MC33664 after being grounded, the resistor R is connected to the DATA-RX port of the isolation transceiver MC33664 and the processing chip MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor 81 is connected to the DATA-RX port of the isolation transceiver MC33664 after being grounded, the resistor R is connected to the CSB-RX port of the isolation transceiver MC33664 and the processing chip MPC 57560, MPC5746 or MPC5744 respectively, one end of the capacitor 80 is connected to the DATA-RX port of the isolation transceiver MC33664 after being grounded, the other end of the resistor R is connected to the SC-RX port of the isolation transceiver MC33664 and the processing chip MPC 57560, the MPC5746 or MPC5744 respectively, one end of the MPC 5779 is connected to the resistor TX port of the isolation transceiver MC 33r, the isolation transceiver MC33664, the resistor R is connected to the ground, the other end of the isolation transceiver MC 33r 33664, the resistor R33r 3357664, the other end of the resistor R33r 33664 is connected to the resistor R33r 335777, the isolation transceiver MC 33r 33664, the isolation transceiver MC 3357664, the isolation transceiver MC 33r 335777, the isolation transceiver MC 3357664, the other end of the isolation transceiver MC 33r 335777, the other end of the isolation transceiver MC 33r 3357664 is connected to the isolation transceiver MC 33r 3357664, the isolation transceiver MC 33r 335777, the isolation transceiver MC 33r 3357664 is connected to the isolation transceiver MC 33r 3357664, the isolation transceiver.
Capacitors C75, C76, C77, C78, C79, C80, C81 and C82 are ceramic capacitors for isolating the MC33664 of the transceiver for resisting interference, resistors R67 and R68 are pull-up resistors, and a transformer C142 is provided with a physical layer transformer driver, so that a processing chip can be conveniently interfaced with a high-speed isolated communication network. The serial peripheral interface SPI of processing chip directly converts data bit information into pulse bit information, transmits to CAN bus network, and resistance R71, R72, R69 CAN improve signal transmission's precision, prevent that error data from arousing misjudgement.
EXAMPLE five
As shown in fig. 5, the battery management system 10 provided in the present embodiment includes: the battery management system comprises a central processing unit 100, a battery controller 120 and a voltage stabilizing module 130, wherein the voltage stabilizing module 130 and the battery controller 120 are respectively connected to the central processing unit 100, the voltage stabilizing module 130 provides stable power supply voltage for the battery management system and provides power supply data of each component, and the voltage stabilizing module 130 comprises a voltage regulator MC 33907.
The central processor 100 is responsible for the information processing of the entire battery management system and coordinates the cooperation between the various modules, regulator MC33907 provides stable supply voltage for the chip, its local area network (HSCAN) and L IN transceivers CAN provide accurate power for new energy electric vehicles, regulator MC33907 has multi-switch and linear voltage regulators, including low power mode 32uA, and has Vallous wake-up capability, adopts advanced power management concepts to maintain high efficiency over wide input voltage low level V L, has battery voltage sensing & MUX output pins, flexible pre-regulator allowing two topologies, non-inverting buck and standard buck, switching power to the single chip core power from 1.2V to 3.3V, multiple wake-up sources IN low power mode CAN, L IN and IOS.
EXAMPLE six
As shown in fig. 6, based on the fifth embodiment, this embodiment provides that the voltage stabilizing module in the battery management system further includes a voltage converting circuit, where the voltage converting circuit includes 1 inductor, 1 diode, 2 resistors, and 3 capacitors, where the anode of the diode D19 is grounded, and then the other end of the diode D19 is connected in series with the resistor R10, the diode D5, and the resistor R9 in turn and then connected to the VSENSE port of the voltage regulator MC33907, the other ends of the parallel capacitor C17 and the capacitor C18 are connected to the VSUP3 port of the voltage regulator MC33907 and between the resistor R10 and the diode D5, one end of the inductor L3 is connected between the resistor R10 and the diode D5, and then the other end of the parallel capacitor C3838 is connected to the VSUP1 port and the VSUP2 port of the voltage regulator MC33907, and the other end of the capacitor C15 is connected to the VSUP1 port of the voltage regulator 33.
With this circuit a leakage loop is created artificially, whereby the voltage on the VSUP port does not exceed the upper limit value.
As shown, the voltage regulator module further includes a standard voltage-reducing circuit, which includes 1 inductor, 5 resistors, and 6 capacitors, wherein, the other end of the resistor R3 is connected to the VCORE-SWS port of the voltage regulator MC33907 after being connected in series with the capacitor C6 and the inductor L, one end of the capacitor C7 is connected to the boost-CORE port of the voltage regulator MC33907 after being connected to ground, the other end of the capacitor C7 is connected between the capacitor C6 and the inductor L, the SW-CORE port of the voltage regulator 33907 is connected between the capacitor C6 and the inductor L, the end of the resistor R6 after being connected in series with the capacitor C10 and the resistor R5 in parallel is connected between the VCORE-SWS port of the voltage regulator MC33907 and the inductor L, the other end of the resistor R6 after being connected in series with the capacitor C10 and the resistor 5 in parallel is connected to the FB-CORE port of the MC33907, the other end of the capacitor C8 is connected to the FB-VCORE-SWS port of the voltage regulator 33907 after being connected to ground, the other end of the resistor R L and the resistor R465 after being connected to ground, the resistor C33907 after being connected in series with the resistor R33907 after being connected to ground, the other end of the resistor C33907 after being connected to ground, the resistor C33907 being connected to ground.
As shown in fig. 6, the regulator module further includes a voltage regulation circuit and an information transceiving port, the voltage regulation circuit includes 1 inductor, 1 MOS transistor, 2 resistors, 2 diodes, 2 transistors, and 5 capacitors, wherein the other end of the resistor R1 is connected to ground and then connected in series with the capacitor C1, the inductor L, and the diode D2 in order to the VPRE port of the regulator MC33907, the other end of the diode D9 is connected between the inductor L1 and the capacitor C1, the SW-PRE1 port and the SW-PRE2 port of the regulator MC33907 are connected between the capacitor C1 and the diode D1, the BOOF-RRE port of the regulator MC33907 is connected between the capacitor C1 and the diode D1 through the capacitor C2, the GATE of the regulator MC33907 is connected to the G port of the MOS transistor Q1 through the resistor R1, the S port of the MOS transistor MC 33ux 1 is connected to ground, the D port of the MOS transistor MC 33ux 72 is connected between the inductor R1 and the inductor C3372, the emitter of the diode D33ux 72, the transistor 33mc 33ux 72 is connected between the emitter of the transistor MC 33ux 72 and the transistor vce 72, the emitter of the transistor 33ux 72, the transistor 33ux 72 is connected between the transistor MC 33ux 72, the emitter of the transistor 33mc 33ux 72 and the transistor 72, the transistor 3372 are connected between the transistor 33mc 33ux 72, the transistor 33ux is connected between the transistor 3372, the transistor 3372 and the emitter of the transistor 33mc 33ux is connected between the transistor 3372, the transistor 72, the transistor 3372 of the transistor 3372, the transistor 3372 is connected to the transistor 33ux 72.
The information receiving and transmitting port comprises 1 CAN communication interface and 1 resistor, wherein the CAN communication interface J1 is connected in parallel with the resistor R11 and then is respectively connected with a CANH port of the voltage stabilizer MC33907 and a CAN L port.
For example, pins 25, 26, 27, 28 of the voltage regulator MC33907 transmit the detection signal to the MPC5602, so that the processing chip MPC5602 detects the stability of the power output voltage, thereby ensuring the stability of the power output voltage and ensuring the better operation of the battery management system.
EXAMPLE seven
As shown in fig. 3, on the basis of the fifth embodiment and the sixth embodiment, the present embodiment provides that the battery controller in the battery management system includes an integrated circuit MC33771B and a first tamper-resistant module, and the first tamper-resistant module includes: 1 MOS pipe, 1 power, 2 resistances, 1 electric capacity, wherein: one end of a resistor R128 connected with the capacitor C117 in series is grounded, the other end of the resistor R128 connected with the capacitor C117 in series is connected with the cathode of the battery BA14, one end of a resistor R123 is connected with the anode of the battery BA14, the resistor R123 is connected with the CT-1 port of the integrated circuit MC33771B, the G pole of the MOS tube Q32 is connected between the resistor R128 and the capacitor C117 and connected with the CB-1 port of the integrated circuit MC33771B, the S pole of the MOS tube Q32 is connected between the resistor R128 and the cathode of the battery BA14, and the D pole of the MOS tube Q32 is connected between the resistor R123 and the anode of the battery BA 14.
As shown in fig. 3, the number of the first antijam modules is multiple, the first antijam modules are sequentially connected between CT-1 to CT-14 on the same side of the integrated circuit MC33771B, wherein isolation circuits are arranged between the first antijam modules, one of the isolation circuits includes 1 resistor, and the resistors R122 are respectively connected between the CB-2.1-C port of the integrated circuit MC33771B and the storage battery.
The integrated circuit MC33771B is a smart mos lithium ion battery controller IC that performs ADC conversion of differential battery voltage and current, as well as battery coulomb counting and battery temperature measurement, digital transmission of communication information through Serial Peripheral Interface (SPI) or transformer isolation (TP L), automatic over/under voltage and temperature detection routable to fault pins, integrated sleep mode over/under voltage and temperature monitoring, on-board 300mA passive battery balancing and diagnostics, hot-plug capability to detect internal and external faults such as open, short, and leakage, etc., and design support ISO26262, highest ASI L D safety capability.
When the integrated circuit MC33771B is conducted through the resistor in the first anti-interference module and the MOS tube, the charging voltage of each battery is ensured to be the same, the charging current of all batteries is the same, and the service life of the batteries is prolonged.
Example eight
As shown in fig. 2, on the basis of the fifth embodiment to the seventh embodiment, the central processing unit in the battery management system provided in this embodiment further includes a charging and discharging management module, and the processing chip is connected to the battery controller through the charging and discharging management module. The charge and discharge management module comprises a charge management unit and a discharge management unit, the processing chips MPC560xB, MPC5746R or MPC5744P realize the charge of the battery through the charge management unit, and realize the discharge of the battery through the discharge management unit, but all of the processing chips MPC560xB, MPC5746R or MPC5744P need to send corresponding instructions through the network transceiver module 110.
As shown in fig. 2, the cpu includes a processor MPC560xB, MPC5746R, or MPC5744P, and the charge and discharge management module includes a charge management unit, and the charge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D6 and a resistor R33 after being connected in parallel is connected to an input end of a driving chip J4, the anode of the diode D6 is close to a driving chip J4, 2 transistors Q13, one end of a Q16 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J4, 2 transistors Q13, the base of a Q16 is close to the driving chip J4, the collector of an NPN transistor Q13 is connected to a power interface of the driving chip J4, capacitors C24 and C126 are respectively connected between the collector of an NPN transistor Q13 and the power interface of the driving chip J4 and then grounded, one end of a diode D3 after being connected in parallel with a resistor R29 is connected between the emitter of the NPN transistor Q29 and the emitter of the PNP transistor Q29, the other end of the diode D29 after being connected in parallel with the resistor R29 is connected in series with the resistor R29 and then connected to the G pole of the MOS transistor.
As shown in fig. 2, the charge and discharge management module further includes a discharge management unit, and the discharge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D7 and a resistor R34 after being connected in parallel is connected to an input end of a driving chip J5, the anode of the diode D7 is close to a driving chip J5, 2 transistors Q14, one end of a Q17 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J5, 2 transistors Q14, the base of a Q17 is close to the driving chip J5, the collector of an NPN transistor Q14 is connected to a power interface of the driving chip J5, capacitors C25 and C125 are respectively connected between the collector of an NPN transistor Q14 and the power interface of the driving chip J5 and then grounded, one end of a diode D4 after being connected in parallel with a resistor R31 is connected between the emitter of the NPN transistor Q31 and the emitter of the PNP transistor Q31, the other end of the diode D31 after being connected in parallel with the resistor R31 is connected in series with the resistor R31 and then connected to the G pole of the MOS transistor.
The driving chip TC44201, the triodes Q17 and Q14 form a driving circuit to drive the MOS tube APPW34N120, the charging chip TC44201, the triodes Q16 and Q13 form a driving circuit to drive the MOS tube APPW34N120 to discharge, the charging and discharging currents can be adjusted during charging and discharging, once a battery fails, a power supply can be turned off at any time, a discharging path can be turned off at any time when the motor fails, and the safety coefficient is increased.
Example nine
As shown in fig. 7, on the basis of the fifth to eighth embodiments, the present embodiment provides a battery management system, further including a communication module and a fourth anti-interference module, where the communication module includes 1 chip IS 25L Q040B, 1 display screen physical interface, 6 resistors, and 7 capacitors, where one end of the resistor R18 and the capacitor C26 connected in parallel IS connected to an SCK port of the chip IS 25L Q040B, one end of the resistor R20 and the capacitor C27 connected in parallel IS connected to a CE #1 port of the chip IS 25L Q040B, one end of the capacitor C30 connected to a VCC port of the chip IS 25L Q040B and grounded, one end of the resistor R17 and the capacitor C35 connected in parallel IS connected to a HO L D port of the physical interface R151, one end of the resistor R19 and the capacitor C34 connected in parallel IS connected to a WP # port of the display screen physical interface R151, one end of the resistor R21 and the capacitor C33 connected to an S0 port of the display screen physical interface R151, and one end of the capacitor R22 connected in parallel IS connected to a SI port of the display screen physical interface SI 31.
The resistors R18 and R20 are connected with two chips for interference prevention, C26, C27 and C30 are used for filtering, the resistors R17, R19, R21 and R22 are used for transmitting the content in the chip IS 25L Q040B to the L CD display screen R151, and instant display of the display IS facilitated, and the resistors C31, C33, C34 and C35 play a role in filtering.
The fourth anti-jamming module comprises 1 chip AT24C512, 2 capacitors and 2 diodes, wherein one end of the capacitor C28 connected with the diode D8 in parallel is connected to an A1 port of the chip AT24C512, one end of the capacitor C29 connected with the diode D9 in parallel is connected to an AO port of the chip AT24C512, and the other end of the capacitor C28 and the other end of the capacitor C29 are grounded.
The diodes D9 and D8 are used for connecting the integrated circuit MC33771B and playing a role in interference prevention, and the capacitors C28 and C29 are used for filtering.
Example ten
As shown in fig. 8, the battery management system 10 provided in the present embodiment includes: the voltage isolation transceiver 140 is connected to the central processing unit 100, and the voltage isolation transceiver 140 includes a chip TJA 1052I. Preferably, the number of the voltage isolation transceivers 140 is 3, and the voltage isolation transceivers 140 are connected in parallel. The central processor is responsible for information processing of the battery management system and coordinates cooperation among the modules. TJA1052I is a high-speed CAN transceiver, a protocol controller that provides differential transmit and receive capabilities for CAN bus transmissions.
The operation condition of the motor, information such as phase angle, voltage, rotation speed and temperature, and information such as charge-discharge current, voltage, open-short protection and overvoltage protection of the battery are transmitted to an external network by the central processing unit through the voltage isolation transceiver 140.
EXAMPLE eleven
As shown in fig. 9, on the basis of the tenth embodiment, the present embodiment provides that the voltage isolation transceiver in the battery management system further includes a third interference rejection module. The third interference rejection module includes: 4 capacitors, 2 resistors, wherein: the resistor R157 is respectively connected with a TXD port of the chip TJA1052I and a B1 port of the processing chip MPC560xB, MPC5746R or MPC5744P, the capacitor C60 is connected between the resistor R157 and the TXD port of the chip TJA1052I and then grounded, and the capacitor C69 is connected between the resistor R157 and a B1 port of the processing chip MPC560xB, MPC5746R or MPC5744P and then grounded; the resistor R161 is respectively connected with the RXD port of the chip TJA1052I and the B0 port of the processing chip MPC560xB, MPC5746R or MPC5744P, the capacitor C109 is connected between the resistor R161 and the TXD port of the chip TJA1052I and then grounded, and the capacitor C112 is connected between the resistor R161 and the B0 port of the processing chip MPC560xB, MPC5746R or MPC5744P and then grounded.
As shown in the figure, the voltage isolation transceiver further comprises a capacitance filtering circuit, the capacitance filtering circuit comprises 2 capacitors, the other ends of the capacitors C55 and C128 which are connected in parallel are connected to the VDD2 port and the VDD1 port of the chip TJA1052I after being grounded, and the GND2 port, the STB port, the CANH port, the CAN L port, the VDD2 port, the GND2 port and the GND2 port of the chip TJA1052I are grounded respectively.
Furthermore, the voltage isolation transceiver also comprises a resistance filter circuit, the resistance filter circuit comprises 1 capacitor, 2 resistors and 2 CAN communication ports, one end of the parallel resistor R159 and one end of the resistor R160 are connected with the capacitor C108 in series and then grounded, the other end of the resistor R159 is respectively connected with the CANH port of the chip TJA1052I and the 2 nd pin of the CAN communication port J7, the other end of the resistor R160 is respectively connected with the CAN L port of the chip TJA1052I and the 2 nd pin of the CAN communication port J9, and the 1 st pin of the CAN communication port J7 and the 1 st pin of the CAN communication port J9 are respectively grounded.
The capacitor C60, the capacitor C69 and the resistor R157 form a pi-type filter, and the capacitor C109, the capacitor C112 and the resistor R161 form a pi-type filter, so that the anti-interference capability is improved. The capacitor C55 and the capacitor C128 are filter capacitors for providing 12VDC voltage for the chip TJA1052, and the resistors R159 and R160 and the capacitor C108 form a low-pass filter.
The TJA1052I can realize high-speed data transmission of the CNA local area network. The TXD port and the RXD port of the TJA1052I receive data sent from the pins 50 and 49 of the MPC5602 processing chip, and send the relevant information of the battery, such as charging current, charging voltage, discharging current and discharging voltage, to the data management base through the CAN communication ports J7 and J9 of the TJA1052I, so as to be used in the subsequent analysis work.
Example twelve
As shown in fig. 2, in the tenth and eleventh embodiments, the central processing unit 100 further includes a charge and discharge management module, the processing chip is connected to the battery controller 120 through the charge and discharge management module, and the central processing unit 100 includes a processor MPC560xB, MPC5746R, or MPC 5744P.
The charge and discharge management module comprises a charge management unit and a discharge management unit, the processing chips MPC560xB, MPC5746R or MPC5744P realize the charge of the battery through the charge management unit, and realize the discharge of the battery through the discharge management unit, but all of the processing chips MPC560xB, MPC5746R or MPC5744P need to send corresponding instructions to the battery controller through the network transceiver module 110.
As shown in the figure, the charging and discharging management module in the battery management system of the embodiment includes a charging management unit, and the charging management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D6 and a resistor R33 after being connected in parallel is connected to an input end of a driving chip J4, the anode of the diode D6 is close to a driving chip J4, 2 transistors Q13, one end of a Q16 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J4, 2 transistors Q13, the base of a Q16 is close to the driving chip J4, the collector of an NPN transistor Q13 is connected to a power interface of the driving chip J4, capacitors C24 and C126 are respectively connected between the collector of an NPN transistor Q13 and the power interface of the driving chip J4 and then grounded, one end of a diode D3 after being connected in parallel with a resistor R29 is connected between the emitter of the NPN transistor Q29 and the emitter of the PNP transistor Q29, the other end of the diode D29 after being connected in parallel with the resistor R29 is connected in series with the resistor R29 and then connected to the G pole of the MOS transistor.
The charge and discharge management module shown in fig. 2 further includes a discharge management unit, and the discharge management unit includes: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode D7 and a resistor R34 after being connected in parallel is connected to an input end of a driving chip J5, the anode of the diode D7 is close to a driving chip J5, 2 transistors Q14, one end of a Q17 after being connected in parallel is connected in series with a resistor R36 and then connected to two output ends of the driving chip J5, 2 transistors Q14, the base of a Q17 is close to the driving chip J5, the collector of an NPN transistor Q14 is connected to a power interface of the driving chip J5, capacitors C25 and C125 are respectively connected between the collector of an NPN transistor Q14 and the power interface of the driving chip J5 and then grounded, one end of a diode D4 after being connected in parallel with a resistor R31 is connected between the emitter of the NPN transistor Q31 and the emitter of the PNP transistor Q31, the other end of the diode D31 after being connected in parallel with the resistor R31 is connected in series with the resistor R31 and then connected to the G pole of the MOS transistor.
When the battery is charged, a pin D12 of the processing chip MPC5602 outputs a control signal to the driving chip J4, the driving chip J4 conducts the MOS transistor Q4, the battery is discharged, when the motor works, a pin D14 of the processing chip MPC5602 outputs a control signal to the driving chip J5, and the driving chip J5 conducts the MOS transistor Q5. The charging management unit and the discharging management unit which are designed separately can charge at constant current during charging, so that the service life of the battery is ensured; when the battery is discharged, the electromechanical operation can ensure that the battery can not be over-discharged, so that the situation that the battery is damaged due to over-charging can not occur when the battery is charged for the second time.
EXAMPLE thirteen
As shown in fig. 10, based on the tenth to twelfth embodiments, the cpu in the battery management system further includes a voltage regulation circuit, wherein the voltage regulation circuit includes 1 chip MC3373, 1 transistor, 1 MOS transistor, 1 diode, 2 inductors, 9 resistors, 21 capacitors, wherein the capacitor C and the capacitor C are respectively connected to the post-S electrode ground of the MOS transistor Q, the G electrode of the MOS transistor Q is connected to the PFD port of the chip MC3373U, the D electrode of the MOS transistor Q is connected in series with the inductor 4 to the VBAT port of the chip MC3373U, the capacitor C124 and the capacitor C are respectively connected to the ground to the VBAT port of the inductor 4 and the chip MC3373U, the capacitor C is connected to the ground to the MOS transistor and the inductor 4, the resistor R and the resistor R are respectively connected to the RAT port, the RST port, the HRT port and the 1N-0N port of the chip MC3373U, the resistor R, the resistor R, the resistor R, the resistor.
The voltage regulating circuit provided by the embodiment provides stable and reliable working voltage for the battery management system and provides a standby power supply for the battery management system. MOS pipe Q6 is the switch tube, C13, C124, C126, C54 are the filter capacitance, resistance R52, R51, R48 play the anti-interference effect, R50, C58 and C57, R49 realize the function of integrating network respectively, R54 is the current-limiting resistance.
Example fourteen
On the basis of the above embodiments, the present embodiment further provides an electric vehicle including the battery management system according to the above.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments, as illustrated in the accompanying drawings.

Claims (10)

1. A battery management system, comprising: the system comprises a central processing unit, a battery controller and a network transceiver module, wherein the network transceiver module is arranged between the central processing unit and the battery controller, and the central processing unit comprises a processing chip MPC560xB, MPC5746R or MPC 5744P.
2. The battery management system of claim 1, wherein the central processor further comprises a charge and discharge management module, and the processing chip is connected to the battery controller through the charge and discharge management module.
3. The battery management system of claim 2, wherein the charge and discharge management module comprises a charge management unit comprising: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode (D6) and a resistor (R33) after being connected in parallel is connected to the input end of the driving chip (J4), the anode of the diode (D6) is close to the driving chip (J4), one end of 2 triodes (Q13, Q16) after being connected in parallel is connected in series with the resistor (R36) and then connected to two output ends of the driving chip (J4), the bases of the 2 triodes (Q13, Q16) are close to the driving chip (J4), the collector of an NPN type triode (Q13) is connected to the power interface of the driving chip (J4), capacitors (C24, C126) are respectively connected between the collector of the NPN type triode (Q13) and the power interface of the driving chip (J4) and then grounded, one end of the diode (D3) and the resistor (R29) after being connected in parallel is connected between the emitter of the NPN type triode (Q13) and the emitter of the PNP type triode (Q16), the other end of the diode (D3) connected with the resistor (R29) in parallel is connected to the G pole of the MOS transistor (Q4), and the other end of the diode (D3) connected with the resistor (R29) in parallel is connected with the resistor (R30) in series and then is grounded.
4. The battery management system according to claim 2 or 3, wherein the discharge management module comprises: 1 MOS pipe, 1 driver chip, 1 NPN type triode, 1 PNP type triode, 2 diodes, 2 electric capacity, 4 resistances, wherein: one end of a diode (D7) and a resistor (R34) after being connected in parallel is connected to the input end of the driving chip (J5), the anode of the diode (D7) is close to the driving chip (J5), one end of 2 triodes (Q14, Q17) after being connected in parallel is connected in series with the resistor (R36) and then connected to two output ends of the driving chip (J5), the bases of the 2 triodes (Q14, Q17) are close to the driving chip (J5), the collector of an NPN type triode (Q14) is connected to the power interface of the driving chip (J5), capacitors (C25, C125) are respectively connected between the collector of the NPN type triode (Q14) and the power interface of the driving chip (J5) and then grounded, one end of the diode (D4) and the resistor (R31) after being connected in parallel is connected between the emitter of the NPN type triode (Q14) and the emitter of the PNP type triode (Q17), the other end of the diode (D4) connected with the resistor (R31) in parallel is connected to the G pole of the MOS transistor (Q5), and the other end of the diode (D4) connected with the resistor (R31) in parallel is connected with the resistor (R32) in series and then is grounded.
5. The battery management system of any of claims 1-4, wherein the battery controller comprises an integrated circuit MC33771B and a first tamper resistant module, the first tamper resistant module comprising: 1 MOS pipe, 2 resistances, 1 electric capacity, wherein: one end of a resistor (R128) connected with a capacitor (C117) in series is grounded, the other end of the resistor (R128) connected with the capacitor (C117) in series is connected with the negative electrode of a storage battery (BA 14), one end of a resistor (R123) is connected with the positive electrode of the storage battery (BA 14), the resistor (R123) is connected with the CT-1 port of the integrated circuit MC33771B, the G electrode of the MOS tube (Q32) is connected between the resistor (R128) and the capacitor (C117) and connected with the CB-1 port of the integrated circuit MC33771B, the S electrode of the MOS tube (Q32) is connected between the resistor (R128) and the negative electrode of the power supply (BA 14), and the D electrode of the MOS tube (Q32) is connected between the resistor (R123) and the positive electrode of the storage battery (BA 14).
6. The battery management system according to claim 5, wherein the number of said first interference rejection modules is plural, said first interference rejection modules are connected in sequence between CT-1 to CT-14 on the same side of said integrated circuit MC33771B, wherein an isolation circuit is arranged between said first interference rejection modules, one isolation circuit comprises 1 resistor, and said resistors (R122) are connected between CB-2.1-C port of said integrated circuit MC33771B and said battery respectively.
7. The battery management system according to claim 5 or 6, wherein the battery controller further comprises a current detection circuit comprising 1 resistor and 2 capacitors, one end of the capacitor (C32) and the resistor (R73) connected in series with the capacitor (C91) is connected to the VANA port of the integrated circuit MC33771B, the AGND port and the ISENSE-port of the integrated circuit MC33771B are connected between the capacitor (C32) and the resistor (R73), respectively, the ISENSE-port of the integrated circuit MC33771B is connected to ground, and the ISENSE + port of the integrated circuit MC33771B is connected to the resistor (R73) and the capacitor (C91).
8. The battery management system of any of claims 1-7, wherein the network transceiver module comprises an isolation transceiver MC33664 and an isolation circuit, the isolation circuit comprising: 1 transformer, 2 capacitors and 3 resistors, wherein the resistor (R69) is connected in parallel with a primary coil of the transformer (C142) and then respectively connected to a port RDTX + and a port RDTX-of the isolation transceiver MC 33664; the two ends of the resistor (R71), the secondary coil of the transformer (C142) and the resistor (R72) which are sequentially connected in series are connected to the integrated circuit MC33771B, one end of the capacitor (C89) which is grounded is connected between the resistor (R72) and the integrated circuit MC33771B, and one end of the capacitor (C90) is connected between the resistor (R71) and the integrated circuit MC33771B which is grounded.
9. The battery management system of claim 8, wherein the network transceiver module further comprises a second anti-interference module comprising 11 resistors and 9 capacitors, wherein the resistor (R) is connected to the INTB port of the isolation transceiver MC33664 and the MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (C) is connected to the INTB port of the isolation transceiver MC33664 after being grounded and the other end thereof is connected to the INTB port of the isolation transceiver MC33664, the resistor (R) is connected to the DATA-RX port of the isolation transceiver MC33664 and the MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (81) is connected to the DATA-RX port of the isolation transceiver MC33664 after being grounded and the other end thereof is connected to the DATA-RX port of the isolation transceiver MC33664, the resistor (R) is connected to the MPC 57664 and the MPC560, MPC5746 or MPC5744 respectively, one end of the capacitor (R) is connected to the MPC 3357664 after being grounded and the MPC 33K-RX port of the isolation transceiver MC33664, one end of the isolation transceiver is connected to the MPC 3357664, one end of the resistor (R) and the MPC 33R) is connected to the ground, the MPC 33R 3357664, the resistor (R) is connected to the MPC 33K-RX port of the isolation transceiver, the ground, the MPC 57664, the resistor (R) is connected to the ground, the resistor (R) is connected to the MPC 33R) port of the MPC 33577, the isolation transceiver, the resistor (R) is connected to the ground, the MPC 3357664, the resistor (R) is connected to the resistor (R) and the ground, the isolation transceiver, the resistor (R) port of the ground, the MPC 3357664, the resistor (R) port of the isolation transceiver after being connected to the resistor (R) and the ground, the resistor (R) and the other end of the resistor (R) port of the isolation transceiver, the other end of the resistor (R) is connected to the ground, the isolation transceiver after being connected to the ground, the resistor (R) and the ground, the resistor (R) of the MPC 3357664, the resistor (R) of the ground, the resistor (R) and the other end of the isolation transceiver after being connected to the ground, the isolation transceiver.
10. An electric vehicle characterized by comprising the battery management system according to any one of claims 1 to 9.
CN202010272276.0A 2020-04-09 2020-04-09 New energy battery management system and electric automobile Withdrawn CN111446759A (en)

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