CN111446291A - Semiconductor device structure and manufacturing method thereof - Google Patents

Semiconductor device structure and manufacturing method thereof Download PDF

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Publication number
CN111446291A
CN111446291A CN201910039644.4A CN201910039644A CN111446291A CN 111446291 A CN111446291 A CN 111446291A CN 201910039644 A CN201910039644 A CN 201910039644A CN 111446291 A CN111446291 A CN 111446291A
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semiconductor channel
type
type semiconductor
channel
layer
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肖德元
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Abstract

The invention provides a semiconductor device structure and a manufacturing method thereof, wherein the semiconductor device structure comprises: a substrate; a first N-type semiconductor channel; the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are respectively determined by the lateral widths of the second N-type semiconductor channel and the first N-type semiconductor channel in the semiconductor layer, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable; a first gate dielectric layer; a first gate electrode layer; a first N-type source and a first N-type drain; a second gate dielectric layer; a second gate electrode layer; a second N-type source and a second N-type drain. The invention can continuously adjust the width of the second N-type semiconductor channel and the width of the first N-type semiconductor channel, thereby greatly improving the flexibility of the design of the semiconductor memory device and the integration level and the performance of the device.

Description

Semiconductor device structure and manufacturing method thereof
Technical Field
The invention belongs to the technical field of integrated circuit design and manufacture, and particularly relates to a semiconductor device structure and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, the size of semiconductor devices is continuously reduced, the performance such as driving current is continuously improved, the power consumption is continuously reduced, and meanwhile, the semiconductor devices also face more and more serious short channel effects, more and more complex semiconductor manufacturing processes and higher production cost.
A Fin-Field-Effect Transistor (FinFET) is a new type of cmos Transistor. The FinFET has the shape similar to that of a fin, and the design can improve circuit control, reduce leakage current and shorten the gate length of a transistor.
A FinFET is an innovative design derived from a conventional standard Transistor-Field Effect Transistor (FET). In the conventional transistor structure, the gate can only control the on and off of the current on one surface of the channel region, and belongs to a planar structure. In the FinFET structure, the gate is designed as a fin-shaped 3D structure, and the on/off of the circuit can be controlled on three sides of the fin-shaped gate. This design can greatly improve circuit control and reduce leakage current (leakage), and also can greatly shorten the channel length of the transistor.
FinFET devices are typically fabricated based on a fin-shaped semiconductor layer on a substrate, however, typically all fin-shaped semiconductor layers on the substrate have the same height, and for this reason, the channel width of a FinFET device is limited by this height, and can only vary discretely, but not continuously, greatly reducing the flexibility of circuit design. In addition, compared to a planar gate device (the channel width of the planar gate device can be continuously adjusted), the FinFET device may cause a certain layout loss due to design constraints (the channel width cannot be continuously adjusted), thereby reducing the circuit integration level.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor device structure and a method for fabricating the same, which are used to solve the problem that the channel width of the semiconductor memory device of the FinFET structure in the prior art can only be discretely adjusted, thereby limiting the flexibility of device design.
To achieve the above and other related objects, the present invention provides a semiconductor device structure comprising:
a substrate;
a first N-type semiconductor channel suspended above the substrate;
the second N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are positioned on the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are respectively determined by the transverse width of the second N-type semiconductor channel and the transverse width of the first N-type semiconductor channel in the semiconductor layer, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable;
the first gate dielectric layer is coated on the outer surface of the first N-type semiconductor channel;
the first gate electrode layer is coated on the outer surface of the first gate dielectric layer;
the first N-type source electrode and the first N-type drain electrode are respectively connected to two ends of the first N-type semiconductor channel;
the second gate dielectric layer is coated on the outer surface of the second N-type semiconductor channel;
the second gate electrode layer is coated on the outer surface of the second gate dielectric layer;
the second N-type source electrode and the second N-type drain electrode are respectively connected to two ends of the second N-type semiconductor channel; wherein the content of the first and second substances,
the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor.
Optionally, a channel width of the first N-type semiconductor channel is greater than a channel width of the second N-type semiconductor channel.
Optionally, a channel width of the first N-type semiconductor channel is 1.2 times to 2 times a channel width of the second N-type semiconductor channel.
Optionally, the thickness of the first N-type semiconductor channel is the same as the thickness of the second N-type semiconductor channel.
Optionally, the cross-sectional shape of the first N-type semiconductor channel includes a rounded rectangle or a racetrack shape, and the cross-sectional shape of the second N-type semiconductor channel includes a rounded rectangle or a racetrack shape.
Optionally, the first N-type semiconductor channel is doped with deuterium ions, and the deuterium ions combine with silicon on the surface of the first N-type semiconductor channel to form a silicon-deuterium passivation layer; the second N-type semiconductor channel is doped with deuterium ions that combine with silicon on the surface of the second N-type semiconductor channel to form a silicon-to-passivation layer.
Optionally, the material of the first N-type semiconductor channel and the material of the second N-type semiconductor channel both include N-type ion doped silicon, the material of the first N-type source and the first N-type drain includes N-type doped silicon carbide or N-type doped silicon phosphide, and the material of the second N-type source and the second N-type drain includes N-type doped silicon carbide or N-type doped silicon phosphide.
Optionally, the cross-sectional areas of the first N-type source and the first N-type drain are larger than the cross-sectional area of the first N-type semiconductor channel, and the first N-type source and the first N-type drain are respectively wrapped at two ends of the first N-type semiconductor channel; the cross-sectional areas of the second N-type source electrode and the second N-type drain electrode are larger than that of the second N-type semiconductor channel, and the second N-type source electrode and the second N-type drain electrode are respectively coated at two ends of the second N-type semiconductor channel.
Optionally, the semiconductor device structure includes at least two pull-down transistors stacked upward from the substrate and at least two gating transistors stacked upward from the substrate, and a space is provided between two pull-down transistors adjacent to each other above and below and a space is provided between two gating transistors adjacent to each other above and below; the pull-down transistors are connected via a first common electrode and the gating transistors are connected via a second common electrode.
Optionally, the semiconductor device structure further includes an isolation layer located on the upper surface of the substrate and located between the substrate and the pull-down transistor and the gate transistor.
The invention also provides a manufacturing method of the semiconductor device structure, which comprises the following steps:
providing a substrate, and forming a first N-type semiconductor channel and a second N-type semiconductor channel on the substrate; the first N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are located in the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are determined by the lateral widths of the second N-type semiconductor channel and the first N-type semiconductor channel in the semiconductor layer respectively, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable;
forming a first gate dielectric layer coated on the outer surface of the first N-type semiconductor channel and a second gate dielectric layer coated on the outer surface of the second N-type semiconductor channel;
forming a first gate electrode layer wrapping the outer surface of the first gate dielectric layer and a second gate electrode layer wrapping the outer surface of the second gate dielectric layer;
forming a first N-type source electrode and a first N-type drain electrode at two ends of the first N-type semiconductor channel respectively;
forming a second N-type source electrode and a second N-type drain electrode at two ends of the second N-type semiconductor channel respectively; wherein the content of the first and second substances,
the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor.
Optionally, a channel width of the first N-type semiconductor channel is greater than a channel width of the second N-type semiconductor channel.
Optionally, the cross-sectional shape of the first N-type semiconductor channel includes a rounded rectangle or a racetrack shape, and the cross-sectional shape of the second N-type semiconductor channel includes a rounded rectangle or a racetrack shape.
Optionally, the cross-sectional areas of the first N-type source and the first N-type drain formed are larger than the cross-sectional area of the first N-type semiconductor channel, and the first N-type source and the first N-type drain are respectively wrapped at two ends of the first N-type semiconductor channel; the cross-sectional areas of the second N-type source electrode and the second N-type drain electrode are larger than that of the second N-type semiconductor channel, and the second N-type source electrode and the second N-type drain electrode are respectively coated at two ends of the second N-type semiconductor channel.
Optionally, providing a substrate, and forming a first N-type semiconductor channel and a second N-type semiconductor channel on the substrate includes the following steps:
providing the substrate;
forming a sacrificial layer and a channel material layer which are alternately overlapped from bottom to top on the substrate, wherein the number of the sacrificial layer and the channel material layer at least comprises two layers;
etching the channel material layer and the sacrificial layer to form a first fin-shaped structure and a second fin-shaped structure; the first fin-shaped structure comprises a first sacrificial unit and a first channel unit which are alternately overlapped from bottom to top, and the second fin-shaped structure comprises a second sacrificial unit and a second channel unit which are alternately overlapped from bottom to top;
selectively removing the first sacrificial unit and the second sacrificial unit to obtain a suspended first semiconductor channel and a suspended second semiconductor channel;
and N-type ion doping is carried out on the first semiconductor channel to form the first N-type semiconductor channel, and N-type ion doping is carried out on the second semiconductor channel to form the second N-type semiconductor channel.
Optionally, selectively removing the first sacrificial unit and the second sacrificial unit to obtain the floating first semiconductor channel and the floating second semiconductor channel includes the following steps:
selectively removing the first sacrificial unit and the second sacrificial unit;
performing a heat treatment under a mixed gas of deuterium and hydrogen to obtain the first semiconductor channel or the second semiconductor channel having a cross-sectional shape including a rounded rectangle or a racetrack shape; after the heat treatment, deuterium ions are doped in the first semiconductor channel and the second semiconductor channel;
and when the first gate dielectric layer and the second gate dielectric layer are formed, the deuterium ions are respectively diffused to the surface of the first N-type semiconductor channel and the surface of the second N-type semiconductor channel and are respectively combined with silicon on the surface of the first N-type semiconductor channel and silicon on the surface of the second N-type semiconductor channel to form a silicon-deuterium passivation layer.
Optionally, in the mixed gas of the deuterium gas and the hydrogen gas, the volume percentage of the deuterium gas is not less than 10%, the temperature range of the heat treatment is between 800 ℃ and 1200 ℃, and the time range of the heat treatment is between 5 minutes and 8 hours.
Optionally, after forming the first gate electrode layer and the second gate electrode layer and before forming the first N-type source and the first N-type drain, the method further includes: forming a first common electrode and a second common electrode; wherein the pull-down transistors are connected via the first common electrode and the gate transistors are connected via the second common electrode.
Optionally, while forming the first gate dielectric layer and the second gate dielectric layer, forming an isolation layer on the upper surface of the substrate; the isolation layer is located between the substrate and the pull-down transistor and the gating transistor.
As described above, the semiconductor device structure and the manufacturing method thereof of the present invention have the following advantages:
the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are determined by the transverse width of the second N-type semiconductor channel and the transverse width of the first N-type semiconductor channel in the semiconductor layer, so that the width of the second N-type semiconductor channel and the width of the first N-type semiconductor channel can be continuously adjusted, the flexibility of the design of a semiconductor memory device can be greatly improved, and the integration level and the performance of the device can be improved;
tritium ions are doped in the first N-type semiconductor channel and the second N-type semiconductor channel, and a silicon-tritium passivation layer is formed on the surface of the first N-type semiconductor channel and the surface of the second N-type semiconductor channel through the first N-type semiconductor channel and the second N-type semiconductor channel, so that generation of silicon dangling bonds is avoided, interface traps are reduced, and reliability of a device is greatly improved.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a semiconductor device structure according to a first embodiment of the present invention.
Fig. 2 to 12 are schematic cross-sectional structures of structures presented in steps of a method for manufacturing a semiconductor device structure according to a first embodiment of the present invention.
FIG. 13 is an equivalent circuit diagram of a memory cell consisting of two pull-down transistors and two gate transistors and two pull-up transistors in a semiconductor device according to the present invention.
Description of the element reference numerals
10 substrate
11 sacrificial layer
111 first sacrificial unit
112 second victim unit
12, 12' pull-down transistor
121 first N-type semiconductor channel
1211 channel material layer
1212 first channel cell
1213 first semiconductor channel
122 first gate dielectric layer
123 first gate electrode layer
124 first N-type source and first N-type drain
13, 13' gating transistor
131 second N-type semiconductor channel
1311 second channel cell
1312 second semiconductor channel
132 second gate dielectric layer
133 second gate electrode layer
134 second N-type source and second N-type drain
14 first common electrode
15 second common electrode
16 isolation layer
17, 17' pull-up transistor
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present invention provides a method for fabricating a semiconductor device structure, which includes the steps of:
1) providing a substrate, and forming a first N-type semiconductor channel and a second N-type semiconductor channel on the substrate; the first N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are located in the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are determined by the lateral widths of the second N-type semiconductor channel and the first N-type semiconductor channel in the semiconductor layer respectively, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable;
2) forming a first gate dielectric layer coated on the outer surface of the first N-type semiconductor channel and a second gate dielectric layer coated on the outer surface of the second N-type semiconductor channel;
3) forming a first gate electrode layer wrapping the outer surface of the first gate dielectric layer and a second gate electrode layer wrapping the outer surface of the second gate dielectric layer;
4) forming a first N-type source electrode and a first N-type drain electrode at two ends of the first N-type semiconductor channel respectively;
5) forming a second N-type source electrode and a second N-type drain electrode at two ends of the second N-type semiconductor channel respectively; the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor.
In step 1), referring to step S1 in fig. 1 and fig. 2 to 8, a substrate 10 is provided, and a first N-type semiconductor channel 121 and a second N-type semiconductor channel 131 are formed on the substrate 10; the first N-type semiconductor channel 121 is suspended on the substrate 10, the second N-type semiconductor channel 131 and the first N-type semiconductor channel 121 are located in the same semiconductor layer, and the channel width of the second N-type semiconductor channel 131 and the channel width of the first N-type semiconductor channel 121 are determined by the lateral widths of the second N-type semiconductor channel 131 and the first N-type semiconductor channel 121 in the semiconductor layer, respectively, so that the channel width of the second N-type semiconductor channel 131 and the channel width of the first N-type semiconductor channel 121 are continuously adjustable.
As an example, step 1) may include the steps of:
1-1) providing the substrate 10, as shown in fig. 2;
1-2) forming a sacrificial layer 11 and a channel material layer 1211 on the substrate 10, the sacrificial layer 11 and the channel material layer 1211 being alternately stacked in sequence from bottom to top, the number of layers of the sacrificial layer 11 and the channel material layer 1211 both including at least two layers, as shown in fig. 3, wherein the number of layers of the sacrificial layer 11 and the channel material layer 1211 is two as an example in fig. 3;
1-3) etching the channel material layer 1211 and the sacrificial layer 11 to form a first fin-shaped structure and a second fin-shaped structure; the first fin-shaped structure includes a first sacrificial unit 111 and a first channel unit 1212 which are alternately stacked in sequence from bottom to top, and the second fin-shaped structure includes a second sacrificial unit 112 and a second channel unit 1311 which are alternately stacked in sequence from bottom to top, as shown in fig. 4;
1-4) selectively removing the first and second sacrificial cells 111, 112 to obtain floating first and second semiconductor channels 1213, 1312, as shown in fig. 5 and 6;
1-5) N-type ion doping the first semiconductor channel 1213 to form the first N-type semiconductor channel 121, as shown in fig. 7, and N-type ion doping the second semiconductor channel 1312 to form the second N-type semiconductor channel 131, as shown in fig. 8.
By way of example, the substrate 10 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, or a silicon germanium substrate. Preferably, in this embodiment, the substrate 10 is a silicon substrate.
As an example, the sacrificial layer 11 and the channel material layer 1211 may be repeatedly formed on the substrate 10 by using a chemical vapor deposition process, the material of the sacrificial layer 11 may include silicon dioxide, and the material of the channel material layer 1211 may include silicon, such as silicon-on-insulator (SOI).
As an example, the thickness of the sacrificial layer 11 may range from 10 nm to 200 nm, such as 50 nm, 100 nm, 150 nm, etc.; the thickness of the channel material 1211 may include 10 nm to 100 nm, such as 25 nm, 50 nm, or 75 nm, and so on.
As an example, the channel material 1211 and the sacrificial layer 11 may be etched by a photolithography process to obtain the first fin structure and the second fin structure, where a width D1 of the first fin structure is greater than a width D2 of the second fin structure. Since the first channel unit 1212 and the second channel unit 1311 are formed by etching the channel material layer 1211, and the first sacrificial unit 111 and the second sacrificial unit 112 are formed by etching the sacrificial layer 11, widths of the first channel unit 1212 and the second channel unit 1311 may be continuously adjustable, which may greatly improve flexibility of semiconductor memory device design, and improve device integration and device performance.
As an example, the steps 1-4) include the steps of:
1-4-1) selectively removing the first sacrificial unit 111 and the second sacrificial unit 112, as shown in fig. 5;
1-4-2) in deuterium gas (D)2) And hydrogen, so that the surfaces of the first semiconductor channel 1213 and the second semiconductor channel 1312 are smoothed, and corners of the first semiconductor channel 1213 and the second semiconductor channel 1312 are rounded to have a rounded rectangular or racetrack cross-sectional shape, i.e., so as to obtain the first semiconductor channel 1213 or the second semiconductor channel 1312 having a cross-sectional shape including a rounded rectangular or racetrack; after the thermal treatment, the first semiconductor channel 1213 and the second semiconductor channel 1312 are doped with deuterium ions therein, as shown in fig. 6.
As an example, in the mixed gas of the deuterium gas and the hydrogen gas, the volume percentage of the deuterium gas may be not less than 10%, the temperature range of the heat treatment may be between 800 ℃ and 1200 ℃, and the time range of the heat treatment may be between 5 minutes and 8 hours.
As an example, the first N-type semiconductor channel 121 may be formed by N-type ion doping of the first semiconductor channel 1213 using an ion implantation process or an ion diffusion process, and the N-type ions may include arsenic or phosphorus, or the like.
As an example, the second semiconductor channel 1312 may be N-type ion-doped using an ion implantation process or an ion diffusion process to form the second N-type semiconductor channel 131, and the N-type ions may include arsenic or phosphorus, or the like. The first N-type semiconductor channel 121 is used to form the pull-down transistor and the second N-type semiconductor channel 131 is used to form the gate transistor.
As an example, the channel width of the first N-type semiconductor channel 121 is greater than the channel width of the second N-type semiconductor channel 131, and preferably, in this embodiment, the channel width of the first N-type semiconductor channel 121 may be 1.2 times to 2 times the channel width of the second N-type semiconductor channel 131.
As an example, the thickness of the first N-type semiconductor channel 121 and the thickness of the second N-type semiconductor channel 131 may be the same.
As an example, the cross-sectional shape of the first N-type semiconductor channel 121 may include a rounded rectangle or a racetrack shape, and the cross-sectional shape of the second N-type semiconductor channel 131 may include a rounded rectangle or a racetrack shape.
Note that the first N-type semiconductor channel 121 and the second N-type semiconductor channel 131 may be formed by simultaneously doping N-type ions into the first semiconductor channel 1213 and the second semiconductor channel 1312.
In step 2), referring to step S2 of fig. 1 and fig. 9, a first gate dielectric layer 122 is formed to cover the outer surface of the first N-type semiconductor channel 121 and a second gate dielectric layer 132 is formed to cover the outer surface of the second N-type semiconductor channel 131.
By way of example, the first gate dielectric layer 122 and the second gate dielectric layer 132 may be formed by a Chemical Vapor Deposition (CVD) process or an atomic layer deposition (a L D) process, the material of the first gate dielectric layer 122 may include a high-k dielectric layer, specifically, the material of the first gate dielectric layer 122 may include any one of high-k dielectric materials such as silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, or hafnium silicon oxide, and the material of the second gate dielectric layer 132 may also include a high-k dielectric layer, specifically, the material of the second gate dielectric layer 132 may include any one of high-k dielectric materials such as silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, or hafnium silicon oxide.
As an example, the method further includes forming an isolation layer 16 on the upper surface of the substrate 10 while forming the first gate dielectric layer 122 and the second gate dielectric layer 132; the isolation layer 16 is located between the substrate 10 and the pull-down transistors and the gate transistors. The isolation layer 16 is used to isolate the substrate 10 from the pull-down transistor, the gate transistor, the first common electrode formed subsequently, and the second common electrode formed subsequently, so as to improve the performance of the device structure. The material of the isolation layer 16 may be the same as the material of the first gate dielectric layer 122 and the second gate dielectric layer 132.
In the process of forming the first gate dielectric layer 122 and the second gate dielectric layer 132, the deuterium ions doped in the first N-type semiconductor channel 121 diffuse to the surface of the first N-type semiconductor channel 121 to form a silicon-deuterium passivation layer (not shown) in combination with silicon on the surface of the first N-type semiconductor channel 121, and simultaneously, the deuterium ions doped in the second N-type semiconductor channel 131 diffuse to the surface of the second N-type semiconductor channel 131 to form a silicon-deuterium passivation layer (not shown) in combination with silicon on the surface of the second N-type semiconductor channel 131. The silicon-deuterium has higher bonding bond strength, and the existence of the silicon-deuterium passivation layer can avoid the generation of silicon dangling bonds and reduce interface traps, thereby greatly improving the reliability of the device.
In step 3), please refer to step S3 in fig. 1 and fig. 10, a first gate electrode layer 123 covering the outer surface of the first gate dielectric layer 122 and a second gate electrode layer 133 covering the outer surface of the second gate dielectric layer 132 are formed.
For example, the first gate electrode layer 123 covering the outer surface of the first gate dielectric layer 122 and the second gate electrode layer 133 covering the periphery of the second gate dielectric layer 132 may be deposited by a chemical vapor deposition process or an atomic layer deposition process. The material of the first gate electrode layer 123 may include any one of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), or titanium (Ti); the material of the second gate electrode layer 133 may include any one of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), or titanium (Ti).
As an example, the steps after forming the first gate electrode layer 123 and the second gate electrode layer 133 further include: forming a first common electrode 14 and a second common electrode 15, as shown in fig. 11; wherein the first gate electrode layer 123 in the pull-down transistor is connected via the first common electrode 14, and the second gate electrode layer 133 in the gate transistor is connected via the second common electrode 15.
As an example, the first common electrode 14 and the second common electrode 15 may be formed using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the material of the first common electrode 14 may include any one of aluminum (Al), tungsten (W), or copper (Cu); the material of the second common electrode 15 may include any one of aluminum (Al), tungsten (W), or copper (Cu).
In step 4), referring to step S4 in fig. 1 and fig. 12, a first N-type source and a first N-type drain 124 are formed at two ends of the first N-type semiconductor channel 121, respectively, to form a junction-less pull-down transistor.
As an example, the first N-type source and the first N-type drain 124 may be formed by using an epitaxial growth process, and the material of the first N-type source and the first N-type drain 124 may include N-type doped silicon carbide (SiC) or N-type doped silicon phosphide (SiP); the cross-sectional areas of the first N-type source and the first N-type drain 124 are larger than the cross-sectional area of the first N-type semiconductor channel 121, and the first N-type source and the first N-type drain 124 are respectively wrapped at two ends of the first N-type semiconductor channel 121.
The first N-type source and the first N-type drain 124 are formed by an epitaxial growth process, and silicon carbide is used as a base material of the first N-type source and the first N-type drain 124, so that the electron mobility of the first N-type source and the first N-type drain 124 can be effectively improved; compared with the N-type doped silicon carbide, the N-type doped silicon phosphide is adopted as the material of the first N-type source and the first N-type drain 124, so that the stress of the first N-type source and the first drain 124 is greater, and the carrier mobility of the first N-type semiconductor channel 121 is higher.
In step 5), referring to step S5 of fig. 1 and fig. 12, a second N-type source and a second N-type drain 134 are formed at two ends of the second N-type semiconductor channel 131, respectively.
As an example, the second N-type source and the second N-type drain 134 may be formed by an epitaxial growth process, and the material of the second N-type source and the second N-type drain 134 may include N-type doped silicon carbide or N-type doped silicon phosphide; (ii) a The cross-sectional areas of the second N-type source and the second N-type drain 134 are larger than the cross-sectional area of the second N-type semiconductor channel 131, and the second N-type source and the second N-type drain 134 are respectively wrapped at two ends of the second N-type semiconductor channel 131.
The second N-type source and the second N-type drain 134 are formed by an epitaxial growth process, and silicon carbide is used as a base material of the second N-type source and the second N-type drain 134, so that the electron mobility of the second N-type source and the second N-type drain 134 can be effectively improved; compared with N-type doped silicon carbide, the N-type doped silicon phosphide is used as the material of the second N-type source and the second N-type drain 134, so that the stress of the second N-type source and the second N-type drain 134 is greater, and the carrier mobility of the second N-type semiconductor channel 131 is higher.
It should be noted that the sequence of step 4) and step 5) may be interchanged, that is, the second N-type source and the second N-type drain 134 may be formed first, and then the first N-type source and the first N-type drain 124 may be formed.
According to the invention, two pull-down transistors 12 and 12 ' and two gating transistors 13 and 13 ' and two pull-up transistors 17 and 17 ' form a memory unit together, an equivalent circuit diagram of the memory unit is shown in FIG. 13, the drain of the gating transistor 13 ' is connected with a bit line B L, the gate of the gating transistor 13 ' is connected with a word line W L, the drain of the gating transistor 13 is connected with a bit line B L B, the gate of the gating transistor 13 is connected with the word line W L, the gate of the pull-up transistor 17 is connected with the gate of the pull-down transistor 12 and then connected with the drain of the pull-up transistor 17 ', the drain of the pull-down transistor 12 ' and the source of the gating transistor 13 ', the source of the pull-up transistor 17 is connected with a power supply voltage Vcc, the gate of the pull-up transistor 17 ' is connected with the gate of the pull-down transistor 12 ' and then connected with the drain of the pull-up transistor 17, the drain of the pull-down transistor 12 and the source of the pull-down transistor 12 ' are connected with the ground voltage Vcc, and the source of the pull-down transistor 12 ' are connected with the pull-down transistor 12 and the pull-down transistor 12 ' respectively.
Example two
With continuing reference to fig. 12 with reference to fig. 2 to 11, the present invention further provides a semiconductor device structure, including: a substrate 10; a first N-type semiconductor channel 121, the first semiconductor channel 121 being suspended above the substrate 10; a second N-type semiconductor channel 131, the second N-type semiconductor channel 131 being suspended above the substrate 10, the second N-type semiconductor channel 131 and the first N-type semiconductor channel 121 being located in the same semiconductor layer, a channel width of the second N-type semiconductor channel 131 and a channel width of the first N-type semiconductor channel 121 being respectively determined by their lateral widths in the semiconductor layer, so that the channel width of the second N-type semiconductor channel 131 and the channel width of the first N-type semiconductor channel 121 are continuously adjustable; the first gate dielectric layer 122, the first gate dielectric layer 122 wraps the outer surface of the first N-type semiconductor channel 121; the first gate electrode layer 123, wherein the first gate electrode layer 123 covers the outer surface of the first gate dielectric layer 122; a first N-type source and a first N-type drain 124, wherein the first N-type source and the first N-type drain 124 are respectively connected to two ends of the first N-type semiconductor channel 121; the second gate dielectric layer 132, wherein the second gate dielectric layer 132 covers the outer surface of the second N-type semiconductor channel 131; the second gate electrode layer 133, wherein the second gate electrode layer 133 covers the outer surface of the second gate dielectric layer; a second N-type source and a second N-type drain 134 respectively connected to two ends of the second N-type semiconductor channel 131; the first N-type semiconductor channel 121, the first gate dielectric layer 122, the first gate electrode layer 123, the first N-type source electrode, and the first N-type drain electrode 124 together form a pull-down transistor; the second N-type semiconductor channel 131, the second gate dielectric layer 132, the second gate electrode layer 133, the second N-type source, and the second N-type drain 134 together form a gating transistor.
By way of example, the substrate 10 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, or a silicon germanium substrate. Preferably, in this embodiment, the substrate 10 is a silicon substrate.
As an example, the channel width of the first N-type semiconductor channel 121 is greater than the channel width of the second N-type semiconductor channel 131, and preferably, in this embodiment, the channel width of the first N-type semiconductor channel 121 may be 1.2 times to 2 times the channel width of the second N-type semiconductor channel 131.
As an example, the thickness of the first N-type semiconductor channel 121 and the thickness of the second N-type semiconductor channel 131 may be the same.
As an example, the cross-sectional shape of the first N-type semiconductor channel 121 may include a rounded rectangle or a racetrack shape, and the cross-sectional shape of the second N-type semiconductor channel 131 may include a rounded rectangle or a racetrack shape.
As an example, the first N-type semiconductor channel 121 is doped with deuterium ions, which combine with silicon on the surface of the first N-type semiconductor channel 121 to form a silicon-deuterium passivation layer (not shown); the second N-type semiconductor channel 131 is doped with deuterium ions that combine with the silicon on the surface of the second N-type semiconductor channel to form a silicon-to-passivation layer.
As an example, the material of the first N-type semiconductor channel 121 and the material of the second N-type semiconductor channel 131 may each include N-type ion-doped silicon.
As an example, the material of the first gate dielectric layer 122 may include a high-k dielectric layer, and specifically, the material of the first gate dielectric layer 122 may include any one of high dielectric constant materials such as silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, or hafnium silicide; similarly, the material of the second gate dielectric layer 132 may include a high-k dielectric layer, and specifically, the material of the second gate dielectric layer 132 may include any one of high-dielectric-constant materials such as silicon dioxide, aluminum oxide, silicon oxynitride, silicon oxycarbide, or hafnium silicon oxide
As an example, the material of the first gate electrode layer 123 may include any one of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), or titanium (Ti); the material of the second gate electrode layer 133 may include any one of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), or titanium (Ti).
The material of the first N-type source and the first N-type drain 124 may include N-type doped silicon carbide (SiC) or N-type doped silicon phosphide (SiP); the cross-sectional areas of the first N-type source and the first N-type drain 124 are larger than the cross-sectional area of the first N-type semiconductor channel 121, and the first N-type source and the first N-type drain 124 are respectively wrapped at two ends of the first N-type semiconductor channel 121.
The material of the second N-type source and the second N-type drain 134 may include N-type doped silicon carbide or N-type doped silicon phosphide; the cross-sectional areas of the second N-type source and the second N-type drain 134 are larger than the cross-sectional area of the second N-type semiconductor channel 131, and the second N-type source and the second N-type drain 134 are respectively wrapped at two ends of the second N-type semiconductor channel 131.
As an example, the semiconductor device structure includes at least two pull-down transistors stacked upward from the substrate and at least two gate transistors stacked upward from the substrate, and a space is provided between two pull-down transistors adjacent to each other above and below and a space is provided between two gate transistors adjacent to each other above and below; the pull-down transistors are connected via a first common electrode 14, the gate transistors are connected via a second common electrode 15; specifically, the first gate electrode layer 123 of the pull-down transistor is connected via the first common electrode 14, and the second gate electrode layer 133 of the gate transistor is connected via the second common electrode 15.
As an example, the semiconductor device structure further includes an isolation layer 16, the isolation layer 16 being located between the substrate 10 and the pull-down transistor and the gate transistor. The isolation layer 16 is used to isolate the substrate 10 from the pull-down transistor, the gate transistor, the first common electrode formed subsequently, and the second common electrode formed subsequently, so as to improve the performance of the device structure. The material of the isolation layer 16 may be the same as the material of the first gate dielectric layer 122 and the second gate dielectric layer 132.
According to the invention, two pull-down transistors 12 and 12 ' and two gating transistors 13 and 13 ' and two pull-up transistors 17 and 17 ' form a memory unit together, an equivalent circuit diagram of the memory unit is shown in FIG. 13, the drain of the gating transistor 13 ' is connected with a bit line B L, the gate of the gating transistor 13 ' is connected with a word line W L, the drain of the gating transistor 13 is connected with a bit line B L B, the gate of the gating transistor 13 is connected with the word line W L, the gate of the pull-up transistor 17 is connected with the gate of the pull-down transistor 12 and then connected with the drain of the pull-up transistor 17 ', the drain of the pull-down transistor 12 ' and the source of the gating transistor 13 ', the source of the pull-up transistor 17 is connected with a power supply voltage Vcc, the gate of the pull-up transistor 17 ' is connected with the gate of the pull-down transistor 12 ' and then connected with the drain of the pull-up transistor 17, the drain of the pull-down transistor 12 and the source of the pull-down transistor 12 ' are connected with the ground voltage Vcc, and the source of the pull-down transistor 12 ' are connected with the pull-down transistor 12 and the pull-down transistor 12 ' respectively.
As described above, the semiconductor device structure and the method of manufacturing the same of the present invention includes: a substrate; a first N-type semiconductor channel suspended above the substrate; the second N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are positioned on the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are respectively determined by the transverse width of the second N-type semiconductor channel and the transverse width of the first N-type semiconductor channel in the semiconductor layer, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable; the first gate dielectric layer is coated on the outer surface of the first N-type semiconductor channel; the first gate electrode layer is coated on the outer surface of the first gate dielectric layer; the first N-type source electrode and the first N-type drain electrode are respectively connected to two ends of the first N-type semiconductor channel; the second gate dielectric layer is coated on the outer surface of the second N-type semiconductor channel; the second gate electrode layer is coated on the outer surface of the second gate dielectric layer; the second N-type source electrode and the second N-type drain electrode are respectively connected to two ends of the second N-type semiconductor channel; the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor. The channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are determined by the transverse width of the second N-type semiconductor channel and the transverse width of the first N-type semiconductor channel in the semiconductor layer, so that the width of the second N-type semiconductor channel and the width of the first N-type semiconductor channel can be continuously adjusted, the flexibility of the design of a semiconductor memory device can be greatly improved, and the integration level and the performance of the device can be improved; tritium ions are doped in the first N-type semiconductor channel and the second N-type semiconductor channel, and a silicon-tritium passivation layer is formed on the surface of the first N-type semiconductor channel and the surface of the second N-type semiconductor channel through the first N-type semiconductor channel and the second N-type semiconductor channel, so that generation of silicon dangling bonds is avoided, interface traps are reduced, and reliability of a device is greatly improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (19)

1. A semiconductor device structure, comprising:
a substrate;
a first N-type semiconductor channel suspended above the substrate;
the second N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are positioned on the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are respectively determined by the transverse width of the second N-type semiconductor channel and the transverse width of the first N-type semiconductor channel in the semiconductor layer, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable;
the first gate dielectric layer is coated on the outer surface of the first N-type semiconductor channel;
the first gate electrode layer is coated on the outer surface of the first gate dielectric layer;
the first N-type source electrode and the first N-type drain electrode are respectively connected to two ends of the first N-type semiconductor channel;
the second gate dielectric layer is coated on the outer surface of the second N-type semiconductor channel;
the second gate electrode layer is coated on the outer surface of the second gate dielectric layer;
the second N-type source electrode and the second N-type drain electrode are respectively connected to two ends of the second N-type semiconductor channel; wherein the content of the first and second substances,
the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor.
2. The semiconductor device structure of claim 1, wherein: the channel width of the first N-type semiconductor channel is larger than the channel width of the second N-type semiconductor channel.
3. The semiconductor device structure of claim 2, wherein: the channel width of the first N-type semiconductor channel is 1.2-2 times of the channel width of the second N-type semiconductor channel.
4. The semiconductor device structure of claim 1, wherein: the thickness of the first N-type semiconductor channel is the same as the thickness of the second N-type semiconductor channel.
5. The semiconductor device structure of claim 1, wherein: the cross-sectional shape of the first N-type semiconductor channel comprises a rounded rectangle or a racetrack shape, and the cross-sectional shape of the second N-type semiconductor channel comprises a rounded rectangle or a racetrack shape.
6. The semiconductor device structure of claim 1, wherein: deuterium ions are doped in the first N-type semiconductor channel and combined with silicon on the surface of the first N-type semiconductor channel to form a silicon-deuterium passivation layer; the second N-type semiconductor channel is doped with deuterium ions that combine with silicon on the surface of the second N-type semiconductor channel to form a silicon-to-passivation layer.
7. The semiconductor device structure of claim 1, wherein: the material of the first N-type semiconductor channel and the material of the second N-type semiconductor channel both comprise N-type ion doped silicon, the material of the first N-type source electrode and the first N-type drain electrode comprise N-type doped silicon carbide or N-type doped silicon phosphide, and the material of the second N-type source electrode and the second N-type drain electrode comprise N-type doped silicon carbide or N-type doped silicon phosphide.
8. The semiconductor device structure of claim 1, wherein: the cross-sectional areas of the first N-type source electrode and the first N-type drain electrode are larger than that of the first N-type semiconductor channel, and the first N-type source electrode and the first N-type drain electrode are respectively coated at two ends of the first N-type semiconductor channel; the cross-sectional areas of the second N-type source electrode and the second N-type drain electrode are larger than that of the second N-type semiconductor channel, and the second N-type source electrode and the second N-type drain electrode are respectively coated at two ends of the second N-type semiconductor channel.
9. The semiconductor device structure of any one of claims 1 to 8, wherein: the semiconductor device structure comprises at least two pull-down transistors stacked upwards from the substrate and at least two gating transistors stacked upwards from the substrate, wherein a space is formed between every two adjacent pull-down transistors, and a space is formed between every two adjacent gating transistors; the pull-down transistors are connected via a first common electrode and the gating transistors are connected via a second common electrode.
10. The semiconductor device structure of claim 9, wherein: the semiconductor device structure further comprises an isolation layer located on the upper surface of the substrate and located between the substrate and the pull-down transistor and the gating transistor.
11. A method for manufacturing a semiconductor device structure is characterized by comprising the following steps:
providing a substrate, and forming a first N-type semiconductor channel and a second N-type semiconductor channel on the substrate; the first N-type semiconductor channel is suspended above the substrate, the second N-type semiconductor channel and the first N-type semiconductor channel are located in the same semiconductor layer, and the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are determined by the lateral widths of the second N-type semiconductor channel and the first N-type semiconductor channel in the semiconductor layer respectively, so that the channel width of the second N-type semiconductor channel and the channel width of the first N-type semiconductor channel are continuously adjustable;
forming a first gate dielectric layer coated on the outer surface of the first N-type semiconductor channel and a second gate dielectric layer coated on the outer surface of the second N-type semiconductor channel;
forming a first gate electrode layer wrapping the outer surface of the first gate dielectric layer and a second gate electrode layer wrapping the outer surface of the second gate dielectric layer;
forming a first N-type source electrode and a first N-type drain electrode at two ends of the first N-type semiconductor channel respectively;
forming a second N-type source electrode and a second N-type drain electrode at two ends of the second N-type semiconductor channel respectively; wherein the content of the first and second substances,
the first N-type semiconductor channel, the first gate dielectric layer, the first gate electrode layer, the first N-type source electrode and the first N-type drain electrode form a pull-down transistor together; the second N-type semiconductor channel, the second gate dielectric layer, the second gate electrode layer, the second N-type source electrode and the second N-type drain electrode jointly form a gating transistor.
12. The method of claim 11, wherein a channel width of the first N-type semiconductor channel is greater than a channel width of the second N-type semiconductor channel.
13. The method of claim 11, wherein a cross-sectional shape of the first N-type semiconductor channel comprises a rounded rectangle or a racetrack shape, and wherein a cross-sectional shape of the second N-type semiconductor channel comprises a rounded rectangle or a racetrack shape.
14. The method as claimed in claim 11, wherein cross-sectional areas of the first N-type source and the first N-type drain are larger than a cross-sectional area of the first N-type semiconductor channel, and the first N-type source and the first N-type drain are respectively wrapped around two ends of the first N-type semiconductor channel; the cross-sectional areas of the second N-type source electrode and the second N-type drain electrode are larger than that of the second N-type semiconductor channel, and the second N-type source electrode and the second N-type drain electrode are respectively coated at two ends of the second N-type semiconductor channel.
15. A method of fabricating a semiconductor device structure according to any of claims 11 to 14, wherein: providing a substrate, and forming a first N-type semiconductor channel and a second N-type semiconductor channel on the substrate comprises the following steps:
providing the substrate;
forming a sacrificial layer and a channel material layer which are alternately overlapped from bottom to top on the substrate, wherein the number of the sacrificial layer and the channel material layer at least comprises two layers;
etching the channel material layer and the sacrificial layer to form a first fin-shaped structure and a second fin-shaped structure; the first fin-shaped structure comprises a first sacrificial unit and a first channel unit which are alternately overlapped from bottom to top, and the second fin-shaped structure comprises a second sacrificial unit and a second channel unit which are alternately overlapped from bottom to top;
selectively removing the first sacrificial unit and the second sacrificial unit to obtain a suspended first semiconductor channel and a suspended second semiconductor channel;
and N-type ion doping is carried out on the first semiconductor channel to form the first N-type semiconductor channel, and N-type ion doping is carried out on the second semiconductor channel to form the second N-type semiconductor channel.
16. A method of fabricating a semiconductor device structure according to claim 15, wherein:
selectively removing the first sacrificial unit and the second sacrificial unit to obtain a suspended first semiconductor channel and a suspended second semiconductor channel comprises the following steps:
selectively removing the first sacrificial unit and the second sacrificial unit;
performing a heat treatment under a mixed gas of deuterium and hydrogen to obtain the first semiconductor channel or the second semiconductor channel having a cross-sectional shape including a rounded rectangle or a racetrack shape; after the heat treatment, deuterium ions are doped in the first semiconductor channel and the second semiconductor channel;
and when the first gate dielectric layer and the second gate dielectric layer are formed, the deuterium ions are respectively diffused to the surface of the first N-type semiconductor channel and the surface of the second N-type semiconductor channel and are respectively combined with silicon on the surface of the first N-type semiconductor channel and silicon on the surface of the second N-type semiconductor channel to form a silicon-deuterium passivation layer.
17. A method of fabricating a semiconductor device structure according to claim 16, wherein: in the mixed gas of the deuterium gas and the hydrogen gas, the volume percentage of the deuterium gas is not less than 10%, the temperature range of the heat treatment is between 800 and 1200 ℃, and the time range of the heat treatment is between 5 minutes and 8 hours.
18. A method of fabricating a semiconductor device structure according to claim 15, wherein: after the first gate electrode layer and the second gate electrode layer are formed and before the first N-type source and the first N-type drain are formed, the method further comprises the following steps: forming a first common electrode and a second common electrode; wherein the pull-down transistors are connected via the first common electrode and the gate transistors are connected via the second common electrode.
19. A method of fabricating a semiconductor device structure according to claim 15, wherein: forming an isolation layer on the upper surface of the substrate while forming the first gate dielectric layer and the second gate dielectric layer; the isolation layer is located between the substrate and the pull-down transistor and the gating transistor.
CN201910039644.4A 2019-01-16 2019-01-16 Semiconductor device structure and manufacturing method thereof Withdrawn CN111446291A (en)

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Application publication date: 20200724