CN111445883A - Control circuit, driving method thereof and display device - Google Patents
Control circuit, driving method thereof and display device Download PDFInfo
- Publication number
- CN111445883A CN111445883A CN202010386625.1A CN202010386625A CN111445883A CN 111445883 A CN111445883 A CN 111445883A CN 202010386625 A CN202010386625 A CN 202010386625A CN 111445883 A CN111445883 A CN 111445883A
- Authority
- CN
- China
- Prior art keywords
- delay module
- module
- transistor
- signal
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a control circuit, a driving method thereof and a display device, and relates to the technical field of display. When the display panel is shut down, the path between the current source module and the delay module is controlled to be conducted, each switch unit is started under the action of a high-level voltage signal so as to charge the storage unit through the current source module, when the storage voltage of the storage unit of the Nth delay module is the high-level voltage, the high-level voltage is output to the (N + 1) th delay module so that the switch unit of the (N + 1) th delay module is started, and when the switch unit of the Nth delay module or the (N + 1) th delay module is started, the signal output end of the Nth delay module outputs the high-level voltage. When the display panel is shut down, under the action of the storage unit in each delay module, the time interval of the signal output end of each delay module outputting the high level voltage is a certain duration, and the current drawn from the high level signal end every time is reduced, so that the shutdown noise is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a control circuit, a driving method thereof and a display device.
Background
L CD (L liquid Crystal Display) Display panel has the advantages of light weight, thin thickness and low power consumption, and is widely applied to electronic products such as televisions, mobile phones and displays.
Therefore, an XON (Output All-On Control) module is provided in the display panel, and when the display panel is turned off, the XON module sets All signals Output by the signal Output terminal C L KOUT to a high level at the same time, so that All driving transistors in the display panel are turned On at the same time to release charges remaining On the liquid crystal.
However, when the display panel is turned off, in order to simultaneously pull up all signals output by the signal output terminal C L KOUT to simultaneously turn on all driving transistors in the display panel, a large current needs to be drawn from the high-level signal terminal VGH, which may cause mechanical vibration of the patch capacitor at the high-level signal terminal VGH, thereby causing shutdown noise.
Disclosure of Invention
The invention provides a control circuit, a driving method thereof and a display device, which are used for solving the problem that shutdown noise is caused due to mechanical vibration of a chip capacitor at a high-level signal end VGH caused by the fact that a large current needs to be absorbed from the high-level signal end VGH when an existing display panel is shut down.
In order to solve the above problem, the present invention discloses a control circuit, comprising: the circuit comprises a current source module, a control module and a plurality of delay modules, wherein each delay module comprises a switch unit and a storage unit;
the control module is respectively connected with the current source module, the first control signal end and each delay module, and is configured to control the conduction of a channel between the current source module and the delay module according to a control signal input by the first control signal end when the display panel is turned off;
each switch unit is respectively connected with the corresponding second control signal end, the control module and the storage unit and is configured to be turned on under the action of a high-level voltage signal input by the second control signal end when the display panel is turned off so as to charge the storage unit through the current source module;
the memory unit of the nth delay module is connected with the second control signal end of the (N + 1) th delay module, and is configured to output a high-level voltage to the second control signal end of the (N + 1) th delay module when the memory voltage of the memory unit of the nth delay module is the high-level voltage, so that the switch unit of the (N + 1) th delay module is turned on; n is a positive integer greater than 0;
when the switch unit of the nth delay module or the switch unit of the (N + 1) th delay module is turned on, the signal output end of the nth delay module outputs the high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module is turned on.
Optionally, the storage unit of the nth delay module is further connected to the signal output end of the nth delay module;
or the second control signal end of the first delay module is connected with the signal output end of the first delay module, and the storage units of other delay modules except the first delay module are connected with the corresponding signal output ends.
Optionally, the switching unit includes a first transistor;
the grid electrode of the first transistor is connected with the second control signal end, the first pole of the first transistor is connected with the control module, and the second pole of the first transistor is connected with the storage unit.
Optionally, the storage unit includes a first capacitor, a first end of the first capacitor is connected to the switch unit, and a second end of the first capacitor is connected to a ground terminal.
Optionally, the current source module includes a current generation unit and a mirror unit;
the current generation unit is connected with an external signal terminal and is configured to generate a target current signal according to a target signal input by the external signal terminal;
the mirror image unit is connected with the current generation unit and the control module, and is configured to copy the target current signal to obtain a mirror image current signal and output the mirror image current signal to the control module.
Optionally, the current generating unit includes a digital-to-analog converter, an operational amplifier, a second transistor, and a first resistor;
the digital-to-analog converter is respectively connected with the external signal end and the non-inverting input end of the operational amplifier;
the output end of the operational amplifier is connected with the grid electrode of the second transistor;
the first pole of the second transistor is connected with the mirror image unit, and the second pole of the second transistor is connected with the first end of the first resistor;
the first end of the first resistor is further connected with the inverting input end of the operational amplifier, and the second end of the first resistor is connected with the ground terminal.
Optionally, the mirroring unit includes a third transistor and a fourth transistor;
a gate of the third transistor is connected to the current generating unit, a first pole of the third transistor is connected to a high-level signal terminal, and a second pole of the third transistor is connected to the current generating unit;
the grid electrode of the fourth transistor is connected with the current generation unit, the first pole of the fourth transistor is connected with the high-level signal end, and the second pole of the fourth transistor is connected with the control module.
Optionally, the control module includes a fifth transistor;
the grid electrode of the fifth transistor is connected with the first control signal end, the first pole of the fifth transistor is connected with the current source module, and the second pole of the fifth transistor is connected with the switch unit of each delay module.
In order to solve the above problem, the present invention further discloses a driving method of a control circuit, which is applied to driving the control circuit, and the driving method includes:
when the display panel is shut down, the control module is started according to a control signal input by the first control signal end so as to control the conduction of a path between the current source module and the delay module;
under the action of a high-level voltage signal input by a second control signal end of the Nth time delay module, a switch unit of the Nth time delay module is started, and a storage unit of the Nth time delay module is charged through the current source module;
when the storage unit of the Nth delay module is a high level voltage, outputting the high level voltage to a second control signal end of an (N + 1) th delay module so as to start a switch unit of the (N + 1) th delay module; n is a positive integer greater than 0;
when the switch unit of the nth delay module or the switch unit of the (N + 1) th delay module is turned on, the signal output end of the nth delay module outputs the high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module is turned on.
In order to solve the above problem, the present invention further discloses a display device including the above control circuit.
Compared with the prior art, the invention has the following advantages:
in the embodiment of the invention, when the display panel is powered off, the control module controls the conduction of the path between the current source module and the delay module according to the control signal input by the first control signal terminal, each switch unit is turned on under the action of the high-level voltage signal input by the second control signal terminal to charge the storage unit through the current source module, when the storage voltage of the storage unit of the Nth delay module is a high level voltage, the high level voltage is output to the second control signal end of the (N + 1) th delay module so as to open the switch unit of the (N + 1) th delay module, when the switch unit of the nth delay module or the switch unit of the (N + 1) th delay module is turned on, and the signal output end of the Nth time delay module outputs high level voltage so as to start the driving transistor corresponding to the signal output end of the Nth time delay module. When the display panel is shut down, under the action of the storage unit in each delay module, the turn-on time interval of the switch units of any two adjacent delay modules is a certain time, and the time for the signal output end of each delay module to output the high level voltage is related to the turn-on time of the corresponding switch unit, so that the time for the signal output end of each delay module to output the high level voltage is a certain time interval, the current drawn by the delay module from the high level signal end VGH every time is reduced, the mechanical vibration of the patch capacitor at the high level signal end VGH is also reduced, and the shutdown noise is reduced.
Drawings
FIG. 1 shows a schematic diagram of a control circuit of an embodiment of the present invention;
FIG. 2 shows a schematic diagram of another control circuit of an embodiment of the present invention;
FIG. 3 shows a detailed circuit diagram of the control circuit shown in FIG. 1;
FIG. 4 shows a detailed circuit diagram of the control circuit depicted in FIG. 2;
fig. 5 is a flowchart illustrating a driving method of a control circuit according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
Referring to fig. 1, a schematic diagram of a control circuit according to an embodiment of the present invention is shown, and fig. 2 is a schematic diagram of another control circuit according to an embodiment of the present invention.
The embodiment of the invention provides a control circuit, which comprises a current source module 11, a control module 12 and a plurality of delay modules 13, wherein each delay module 13 comprises a switch unit 131 and a storage unit 132.
And the control module 12 is connected to the current source module 11, the first control signal terminal XON, and each delay module 13, and configured to control a path between the current source module 11 and the delay module 13 to be conducted according to a control signal input by the first control signal terminal XON when the display panel is turned off.
Each switch unit 131 is connected to the corresponding second control signal end Ctr, the control module 12 and the storage unit 132, and is configured to be turned on under the action of a high-level voltage signal input by the second control signal end Ctr when the display panel is turned off, so as to charge the storage unit 132 through the current source module 11.
The storage unit 132 of the nth delay module 13 is connected to the second control signal terminal Ctr of the (N + 1) th delay module 13, and configured to output a high level voltage to the second control signal terminal Ctr of the (N + 1) th delay module 13 when the storage voltage of the storage unit 132 of the nth delay module 13 is the high level voltage, so as to turn on the switch unit 131 of the (N + 1) th delay module 13; n is a positive integer greater than 0.
When the switch unit 131 of the nth delay module 13 or the switch unit 131 of the (N + 1) th delay module 13 is turned on, the signal output end of the nth delay module 13 outputs a high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module 13 is turned on.
In the embodiment of the present invention, when the display panel normally works, the control module 12 is turned off, so as to control the path between the current source module 11 and the delay module 13 to be disconnected, and the delay module 13 does not work; when the display panel is turned off, the control module 12 is turned on under the action of the control signal input by the first control signal terminal XON, so as to control the conduction of the path between the current source module 11 and the delay module 13, and at this time, the delay module 13 starts to work.
As shown in fig. 1 and 2, the control circuit is provided with 4 delay modules 13, each delay module 13 includes a switch unit 131 and a storage unit 132, for example, a first delay module 13 includes a switch unit 1 and a storage unit 1, a second delay module 13 includes a switch unit 2 and a storage unit 2, a third delay module 13 includes a switch unit 3 and a storage unit 3, and a fourth delay module 13 includes a switch unit 4 and a storage unit 4, and each delay module 13 corresponds to a signal output terminal, for example, the signal output terminal corresponding to the first delay module 13 is a signal output terminal C L K1OUT, the signal output terminal corresponding to the second delay module 13 is a signal output terminal C L K2OUT, the signal output terminal corresponding to the third delay module 13 is a signal output terminal C L K3OUT, and the signal output terminal corresponding to the fourth delay module 12 is a signal output terminal C L K4 OUT.
It should be noted that the number of the delay modules 13 arranged in the control circuit is determined according to the number of the clock signals C L K required by the Gate driving circuit corresponding to the display panel, the Gate driving circuit may be a Gate Driver on array (GOA) circuit, when the number of the clock signals C L K required by the Gate driving circuit corresponding to the display panel is M, the number of the delay modules 13 arranged in the control circuit is M, and M is a positive integer greater than 1, therefore, the number of the delay modules 13 in the control circuit according to the embodiment of the present invention is not limited to 4, and the signal output terminal corresponding to each delay module 13 is used to provide the clock signal C L K to the Gate driving circuit, so as to pull up the signal of the Gate line connected to the output terminal of the Gate driving circuit, so that the driving transistor connected to the Gate line is turned on, thereby releasing the charge remaining on the liquid crystal corresponding to the driving transistor.
Taking the control circuit shown in fig. 1 and fig. 2 as an example, the working process of each delay module 13 is described:
when the display panel is turned off, a high-level voltage signal is input to the second control signal end Ctr connected to the switch unit 1 in the first delay module 13, so that the switch unit 1 in the first delay module 13 is turned on, the current source module 11 charges the storage unit 1 through the switch unit 1, and when the storage voltage of the storage unit 1 in the first delay module 13 is a high-level voltage, a high-level voltage is output to the second control signal end Ctr of the second delay module 13; the switch unit 2 in the second delay module 13 is turned on under the action of a high-level voltage signal input by the second control signal terminal Ctr of the second delay module 13, and then the current source module 11 charges the storage unit 2 through the switch unit 2, and outputs a high-level voltage to the second control signal terminal Ctr of the third delay module 13 when the storage voltage of the storage unit 2 in the second delay module 13 is the high-level voltage; the switch unit 3 in the third delay module 13 is turned on under the action of a high-level voltage signal input by the second control signal terminal Ctr of the third delay module 13, and then the current source module 11 charges the storage unit 3 through the switch unit 3, and outputs a high-level voltage to the second control signal terminal Ctr of the fourth delay module 13 when the storage voltage of the storage unit 3 in the third delay module 13 is the high-level voltage; the switch unit 4 in the fourth delay module 13 is turned on under the action of the high-level voltage signal input from the second control signal end Ctr of the fourth delay module 13, and then the current source module 11 charges the storage unit 4 through the switch unit 4.
When the charging current of the current source module 11 is Iref and the storage capacitors of the memory cells 132 are all C, the time t required for charging the storage voltage of each memory cell 132 to the high level voltage Vgh is C × Vgh/Iref, so the duration of the on-time interval of the switch cells 131 in two adjacent delay modules 13 is t.
It should be noted that, in order to simplify the drawing of the circuit, the storage unit 132 of the nth delay module 13 is directly connected to the switch unit 131 of the (N + 1) th delay module 13, actually, the storage unit 132 of the nth delay module 13 is connected to the second control signal terminal Ctr of the (N + 1) th delay module 13, and the second control signal terminal Ctr of the (N + 1) th delay module 13 is further connected to the switch unit 131 of the (N + 1) th delay module 13; in addition, the storage capacitors of the storage units 132 may be set differently, and the durations of the on-time intervals of the switch units 131 in any two adjacent delay modules 13 are different.
In an alternative embodiment of the present invention, as shown in fig. 1, the second control signal terminal Ctr of the first delay module 13 is connected to the signal output terminal C L K1OUT of the first delay module 13, and the memory units 132 of the other delay modules 13 except the first delay module 13 are connected to the corresponding signal output terminals.
That is, in fig. 1, the memory cell 2 in the second delay module 13 is connected to the signal output terminal C L K2OUT corresponding to the second delay module 13, the memory cell 3 in the third delay module 13 is connected to the signal output terminal C L K3OUT corresponding to the third delay module 13, and the memory cell 4 in the fourth delay module 13 is connected to the signal output terminal C L K4OUT corresponding to the fourth delay module 13.
Therefore, when the switch unit 1 in the first delay module 13 is turned on, the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage to turn on the driving transistor corresponding to the signal output terminal C L K1OUT of the first delay module 13, when the switch unit 3 in the third delay module 13 is turned on (i.e., when the storage voltage of the memory unit 2 in the second delay module 13 is a high level voltage), the signal output terminal C L K2OUT of the second delay module 13 outputs a high level voltage to turn on the driving transistor corresponding to the signal output terminal C L K2OUT of the second delay module 13, and when the switch unit 4 in the fourth delay module 13 is turned on (i.e., when the storage voltage of the memory unit 3 in the third delay module 13 is a high level voltage), the signal output terminal C L K3OUT of the third delay module 13 outputs a high level voltage to turn on the driving transistor corresponding to the signal output terminal C L K3OUT of the third delay module 13.
Since only 4 delay modules 13 are provided in the control circuit of fig. 1, when the switch unit 4 in the fourth delay module 13 is turned on, the current source module 11 charges the storage unit 4 through the switch unit 4, and when the storage voltage of the storage unit 4 in the fourth delay module 13 is a high level voltage, the signal output terminal C L K4OUT of the fourth delay module 13 outputs the high level voltage, so that the driving transistor corresponding to the signal output terminal C L K4OUT of the fourth delay module 13 is turned on.
In summary, when the charging current of the current source module 11 is Iref and the storage capacitors of the storage units 132 are all C, the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K2OUT of the second delay module 13 outputs a high level voltage after the interval duration of 2t, correspondingly, the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K3OUT of the third delay module 13 outputs a high level voltage after the interval duration of 3t, and then the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K4OUT of the fourth delay module 13 outputs a high level voltage after the interval duration of 4 t.
In another alternative embodiment of the present invention, as shown in fig. 2, the storage unit 132 of the nth delay module 13 is further connected to the signal output terminal of the nth delay module.
That is, in fig. 2, the memory cell 1 of the first delay module 13 is connected to the signal output terminal C L K1OUT of the first delay module 13, the memory cell 2 of the second delay module 13 is connected to the signal output terminal C L K2OUT of the second delay module 13, the memory cell 3 of the third delay module 13 is connected to the signal output terminal C L K3OUT of the third delay module 13, and the memory cell 4 of the fourth delay module 13 is connected to the signal output terminal C L K4OUT of the fourth delay module 13.
Therefore, when the switch unit 2 in the second delay block 13 is turned on (i.e., when the storage voltage of the memory unit 1 in the first delay block 13 is a high level voltage), the signal output terminal C L K1OUT of the first delay block 13 outputs a high level voltage to turn on the driving transistor corresponding to the signal output terminal C L K1OUT of the first delay block 13, when the switch unit 3 in the third delay block 13 is turned on (i.e., when the storage voltage of the memory unit 2 in the second delay block 13 is a high level voltage), the signal output terminal C L K2OUT of the second delay block 13 outputs a high level voltage to turn on the driving transistor corresponding to the signal output terminal C L K2OUT of the second delay block 13, and when the switch unit 4 in the fourth delay block 13 is turned on (i.e., when the storage voltage of the memory unit 3 in the third delay block 13 is a high level voltage), the signal output terminal C L K3OUT of the third delay block 13 outputs a high level voltage to turn on the driving transistor L K3OUT corresponding to the third delay block 13.
Since only 4 delay modules 13 are provided in the control circuit of fig. 2, when the switch unit 4 in the fourth delay module 13 is turned on, the current source module 11 charges the storage unit 4 through the switch unit 4, and when the storage voltage of the storage unit 4 in the fourth delay module 13 is a high level voltage, the signal output terminal C L K4OUT of the fourth delay module 13 outputs the high level voltage, so that the driving transistor corresponding to the signal output terminal C L K4OUT of the fourth delay module 13 is turned on.
In summary, when the charging current of the current source module 11 is Iref and the storage capacitors of the storage units 132 are all C, the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K2OUT of the second delay module 13 outputs a high level voltage after the interval duration t, correspondingly, the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K3OUT of the third delay module 13 outputs a high level voltage after the interval duration 2t, and then the signal output terminal C L K1OUT of the first delay module 13 outputs a high level voltage, and then the signal output terminal C L K4OUT of the fourth delay module 13 outputs a high level voltage after the interval duration 3 t.
It can be seen that, when the display panel is turned off, under the action of the storage unit 132 in each delay module 13, the on-time intervals of the switch units 131 of any two adjacent delay modules 13 are a certain duration, for example, the interval duration is t, and when the switch unit 131 of the nth delay module 13 or the switch unit 131 of the (N + 1) th delay module 13 is turned on, the signal output end of the nth delay module 13 outputs a high-level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module 13 is turned on, that is, the time for the signal output end of each delay module 13 to output the high-level voltage is related to the on-time of the corresponding switch unit 131, therefore, the time for the signal output end of each delay module 13 to output the high-level voltage is also a certain duration, and the current drawn by the delay module 13 from the high-level signal end VGH each time is reduced, the mechanical vibration of the patch capacitor at the high level signal terminal VGH is also reduced, thereby reducing the shutdown noise.
As shown in fig. 3 and 4, the switching unit 131 includes a first transistor M1; the gate of the first transistor M1 is connected to the second control signal terminal Ctr, the first pole of the first transistor M1 is connected to the control module 12, and the second pole of the first transistor M1 is connected to the memory cell 132. The memory cell 132 includes a first capacitor C1, a first terminal of the first capacitor C1 is connected to the switch unit 131, and a second terminal of the first capacitor C1 is connected to the ground GND.
As shown in fig. 3, the second control signal terminal Ctr (not shown for the sake of simplicity of circuit drawing) of the first delay module 13 is connected to the signal output terminal C L K1OUT of the first delay module 13, and the gate of the first transistor M1 in the first delay module 13 is also connected to the second control signal terminal Ctr of the first delay module 13, so that the gate of the first transistor M1 in the first delay module 13 is also connected to the signal output terminal C L K1OUT of the first delay module 13, the gates of the first transistors M1 in the other delay modules 13 except the first delay module 13 are connected to the first terminal of the first capacitor C1 in the last delay module 13, that is, the gate of the first transistor M1 in the second delay module 13 is connected to the first terminal of the first capacitor C1 in the first delay module 13, and the gate of the first transistor M5 in the third delay module 13 is connected to the first terminal of the first capacitor C1 in the second delay module 13, and the gate of the first transistor M466 in the first delay module 13 is connected to the fourth delay module 5813.
As shown in fig. 3, the first end of the first capacitor C1 in the other delay modules 13 except the first delay module 13 is further connected to the corresponding signal output terminal, that is, the first end of the first capacitor C1 in the second delay module 13 is connected to the signal output terminal C L K2OUT corresponding to the second delay module 13, the first end of the first capacitor C1 in the third delay module 13 is connected to the signal output terminal C L K3OUT corresponding to the third delay module 13, and the first end of the first capacitor C1 in the fourth delay module 13 is connected to the signal output terminal C L K3OUT corresponding to the fourth delay module 13.
As shown in fig. 4, the first end of the first capacitor C1 in each delay module 13 is connected to the corresponding signal output end, that is, the first end of the first capacitor C1 in the nth delay module 13 is connected to the signal output end of the nth delay module; the first terminal of the first capacitor C1 in the nth delay module 13 is further connected to the gate of the first transistor M1 in the (N + 1) th delay module 13.
In the embodiment of the present invention, as shown in fig. 3 and 4, the current source module 11 includes a current generating unit 111 and a mirroring unit 112; a current generating unit 111 connected to the external signal terminal Input and configured to generate a target current signal according to a target signal Input by the external signal terminal Input; and the mirror unit 112, connected to the current generating unit 111 and the control module 12, configured to copy the target current signal, obtain a mirror current signal, and output the mirror current signal to the control module 12.
The current generation unit 111 includes a digital-to-analog converter, an operational amplifier OP, a second transistor M2, and a first resistor R1; the digital-to-analog converter is respectively connected with an external signal end Input and the non-inverting Input end of the operational amplifier OP; the output end of the operational amplifier OP is connected to the gate of the second transistor M2; a first pole of the second transistor M2 is connected to the mirror cell 112, and a second pole of the second transistor M2 is connected to a first terminal of the first resistor R1; the first end of the first resistor R1 is further connected to the inverting input terminal of the operational amplifier OP, and the second end of the first resistor R1 is connected to the ground GND.
The mirroring unit 112 includes a third transistor M3 and a fourth transistor M4; a gate of the third transistor M3 is connected to the current generating unit 111, a first pole of the third transistor M3 is connected to the high level signal terminal VGH, and a second pole of the third transistor M3 is connected to the current generating unit 111; the gate of the fourth transistor M4 is connected to the current generating unit 111, the first pole of the fourth transistor M4 is connected to the high level signal terminal VGH, and the second pole of the fourth transistor M4 is connected to the control module 12.
Specifically, the gate of the third transistor M3 and the second pole of the third transistor M3 are connected to the first pole of the second transistor M2 in the current generating unit 111, and the gate of the third transistor M4 is connected to the first pole of the second transistor M2 in the current generating unit 111.
The digital-to-analog converter receives a target signal Input by an external signal end Input, the target signal is a digital signal, the digital-to-analog converter converts the digital target signal into an analog target signal and inputs the analog target signal to a non-inverting Input end of an operational amplifier OP, and the voltage value of the analog target signal is V1; and the operational amplifier OP, the second transistor M2 and the first resistor R1 form a negative feedback loop so that the voltage at the inverting input terminal of the operational amplifier OP is equal to the voltage at the non-inverting input terminal of the operational amplifier OP, and therefore, the current flowing through the first resistor R1 is made to be V1/R1, i.e., the current of the target current signal generated by the current generating unit 111 is made to be V1/R1.
The third transistor M3 and the fourth transistor M4 form a current mirror, the current flowing through the first resistor R1 is mirrored to the fourth transistor M4, that is, the mirror unit 112 copies the target current signal generated by the current generation unit 111 to obtain a mirror current signal, the mirror unit 112 outputs the mirror current signal to the control module 12 as a current source of the delay module 13, and the current of the mirror current signal is also V1/R1, so that, when the display panel is turned off, the charging current Iref when the current source module 11 charges the storage unit 132 in the delay module 13 is V1/R1.
It should be noted that the current source module 11 of the embodiment of the present invention is not limited to the current source module 11 shown in fig. 3 and fig. 4, and the current source module 11 may also be replaced by a current source chip, if the current source chip is adopted, the charging current provided to the storage unit 132 in the delay module 13 is usually a fixed value, and by adopting the current source module 11 shown in fig. 3 and fig. 4, the charging current provided to the storage unit 132 in the delay module 13 may be made different by adjusting the voltage value of the target signal Input by the external signal terminal Input, so as to change the interval duration of outputting the high level voltage by the signal output terminal of each delay module 13, so that the control current of the embodiment of the present invention may be applied to different display panels.
As shown in fig. 3 and 4, the control module 12 includes a fifth transistor M5; a gate of the fifth transistor M5 is connected to the first control signal terminal XON, a first pole of the fifth transistor M5 is connected to the current source module 11, and a second pole of the fifth transistor M5 is connected to the switching unit 131 of each delay module 13.
Specifically, a first pole of the fifth transistor M5 is connected to a second pole of the fourth transistor M4, and a second pole of the fifth transistor M5 is connected to a first pole of the first transistor M1.
When the display panel normally works, the control signal input by the first control signal terminal XON is at a high level, so that the fifth transistor M5 is turned off, and the path between the control current source module 11 and the delay module 13 is disconnected; when the shutdown of the display panel is detected, the control signal input by the first control signal terminal XON is at a low level, so that the fifth transistor M5 is turned on, and the path between the current source module 11 and the delay module 13 is controlled to be turned on.
The first transistor M1 is an N-type transistor, the second transistor M2 is an N-type transistor, the third transistor M3 and the fourth transistor M4 are P-type transistors, and the fifth transistor M5 is a P-type transistor. In order to distinguish two poles of a transistor except for a gate, a source thereof is referred to as a first pole, and a drain thereof is referred to as a second pole.
In the embodiment of the present invention, as shown in fig. 3 and 4, the control circuit further includes a level shifter 14 connected to the signal output terminal of each delay module 13, specifically, the signal output terminal of each delay module 13 is connected to the output terminal of the corresponding level shifter 14, and the level shifter 14 is configured to output a high level voltage to the corresponding signal output terminal when the display panel displays normally, so as to provide the required clock signal C L K to the gate driving circuit connected to the signal output terminal.
When the display panel normally operates, the delay module 13 does not operate, and each of the level shifters 14 is in a normal operation mode, that is, the first level shifter 14 pulls up a C L K1 signal output by a TCON (Timer Control Register) chip to a high level voltage Vgh and provides the signal to a signal output terminal C L K1OUT, the second level shifter 14 pulls up a C L K2 signal output by the TCON chip to the high level voltage Vgh and provides the signal to a signal output terminal C L K2OUT, the third level shifter 14 pulls up a C L K3 signal output by the TCON chip to the high level voltage Vgh and provides the signal to a signal output terminal C L K3OUT, and the fourth level shifter 14 pulls up a C L K4 signal output by the TCON chip to the high level voltage Vgh and provides the signal to a signal output terminal C L K4 OUT.
It should be noted that the level shifter 14 is actually connected to the high-level signal terminal VGH, and the high-level signal terminal VGH provides power to pull up the signal output by the TCON chip to the high-level voltage VGH.
As shown in fig. 3, since the second control signal terminal Ctr of the first delay module 13 is connected to the signal output terminal C L K1OUT of the first delay module 13, the level shifter 14 connected to the signal output terminal C L K1OUT of the first delay module 13 is also connected to the second control signal terminal Ctr of the first delay module 13 (not shown for simplifying the drawing of the circuit), and is configured to output a high level voltage to the second control signal terminal Ctr of the first delay module 13 when the display panel is powered off, so as to turn on the first delay module 13.
Specifically, when the display panel is turned off, the level shifter 14 connected to the signal output terminal C L K1OUT of the first delay module 13 receives the C L K1 signal output by the TCON chip, pulls the voltage of the C L K1 signal up to the high level voltage Vgh, and then inputs the high level voltage Vgh to the second control signal terminal Ctr of the first delay module 13 to start the delay module 13, that is, the control circuit in fig. 3 starts the delay module 13 by the high level voltage signal provided by the level shifter 14.
In fig. 3, the other level shifters 14 except the level shifter 14 connected to the first delay module 13 all output signals in a high-impedance state when the display panel is turned off, and the other level shifters 14 except the level shifter 14 connected to the first delay module 13 do not affect the signal output end, that is, the signal output end is only related to the delay module 13.
For the control circuit shown in fig. 4, an additional path of signal is needed to provide a high-level voltage signal for the second control signal terminal Ctr of the first delay module 13, that is, an additional path of high-level voltage signal is needed to start the delay module 13, so that the control circuit shown in fig. 3 reduces a path of signal compared with the control circuit shown in fig. 4. Each of the level shifters 14 in fig. 4 outputs a signal in a high impedance state when the display panel is turned off.
In the embodiment of the present invention, when the display panel is turned off, under the action of the storage unit in each delay module, the on time intervals of the switch units of any two adjacent delay modules are a certain duration, and the time for the signal output end of each delay module to output the high level voltage is related to the on time of the corresponding switch unit, so that the time for the signal output end of each delay module to output the high level voltage is also a certain duration, and the current drawn by the delay module from the VGH at the high level signal end every time is reduced, and the mechanical vibration of the patch capacitor at the VGH at the high level signal end is also reduced, thereby reducing the turn-off noise.
Example two
Referring to fig. 5, a flowchart of a driving method of a control circuit according to an embodiment of the present invention is shown, and the method is applied to driving the control circuit according to the first embodiment, and specifically includes the following steps:
In the embodiment of the present invention, the control circuit includes a current source module 11, a control module 12, and a plurality of delay modules 13, each delay module 13 includes a switch unit 131 and a storage unit 132, and the control module 12 is connected to the current source module 11, the first control signal terminal XON, and each delay module 13, respectively.
When the display panel is turned off, the control module 12 is turned on under the action of the control signal input by the first control signal terminal XON, so as to control the conduction of the path between the current source module 11 and the delay module 13, and at this time, the delay module 13 starts to work.
In the embodiment of the present invention, each switch unit 131 is connected to the corresponding second control signal end Ctr, the control module 12 and the storage unit 132, and when the display panel is turned off, under the action of a high-level voltage signal input from the second control signal end Ctr of the nth delay module, the switch unit 131 of the nth delay module is turned on, so as to charge the storage unit 132 of the nth delay module through the current source module 11.
In the embodiment of the present invention, the storage unit 132 of the nth delay module 13 is connected to the second control signal terminal Ctr of the (N + 1) th delay module 13, and when the storage voltage of the storage unit 132 of the nth delay module 13 is a high level voltage, the storage unit 132 of the nth delay module 13 outputs the high level voltage to the second control signal terminal Ctr of the (N + 1) th delay module 13, so as to turn on the switch unit 131 of the (N + 1) th delay module 13; n is a positive integer greater than 0.
When the switch unit 131 of the nth delay module 13 or the switch unit 131 of the (N + 1) th delay module 13 is turned on, the signal output end of the nth delay module 13 outputs a high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module 13 is turned on.
In the embodiment of the present invention, when the display panel is turned off, under the action of the storage unit in each delay module, the on time intervals of the switch units of any two adjacent delay modules are a certain duration, and the time for the signal output end of each delay module to output the high level voltage is related to the on time of the corresponding switch unit, so that the time for the signal output end of each delay module to output the high level voltage is also a certain duration, and the current drawn by the delay module from the VGH at the high level signal end every time is reduced, and the mechanical vibration of the patch capacitor at the VGH at the high level signal end is also reduced, thereby reducing the turn-off noise.
EXAMPLE III
The embodiment of the invention also provides a display device which comprises the control circuit.
The control circuit of the embodiment of the present invention may be integrated in an L S (L ev Shift, level Shift) chip, and for the specific description of the control circuit, reference may be made to the description of the first embodiment and the second embodiment, which is not described again in the embodiment of the present invention.
In addition, the display device further comprises a display panel, a TCON chip, a driving chip and other devices.
In practical applications, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a display, a notebook computer, a navigator and the like.
In the embodiment of the present invention, when the display panel is turned off, under the action of the storage unit in each delay module, the on time intervals of the switch units of any two adjacent delay modules are a certain duration, and the time for the signal output end of each delay module to output the high level voltage is related to the on time of the corresponding switch unit, so that the time for the signal output end of each delay module to output the high level voltage is also a certain duration, and the current drawn by the delay module from the VGH at the high level signal end every time is reduced, and the mechanical vibration of the patch capacitor at the VGH at the high level signal end is also reduced, thereby reducing the turn-off noise.
For simplicity of explanation, the foregoing method embodiments are described as a series of acts or combinations, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The control circuit, the driving method thereof, and the display device provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A control circuit, comprising: the circuit comprises a current source module, a control module and a plurality of delay modules, wherein each delay module comprises a switch unit and a storage unit;
the control module is respectively connected with the current source module, the first control signal end and each delay module, and is configured to control the conduction of a channel between the current source module and the delay module according to a control signal input by the first control signal end when the display panel is turned off;
each switch unit is respectively connected with the corresponding second control signal end, the control module and the storage unit and is configured to be turned on under the action of a high-level voltage signal input by the second control signal end when the display panel is turned off so as to charge the storage unit through the current source module;
the memory unit of the nth delay module is connected with the second control signal end of the (N + 1) th delay module, and is configured to output a high-level voltage to the second control signal end of the (N + 1) th delay module when the memory voltage of the memory unit of the nth delay module is the high-level voltage, so that the switch unit of the (N + 1) th delay module is turned on; n is a positive integer greater than 0;
when the switch unit of the nth delay module or the switch unit of the (N + 1) th delay module is turned on, the signal output end of the nth delay module outputs the high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module is turned on.
2. The control circuit of claim 1, wherein the storage unit of the nth delay module is further connected to the signal output terminal of the nth delay module;
or the second control signal end of the first delay module is connected with the signal output end of the first delay module, and the storage units of other delay modules except the first delay module are connected with the corresponding signal output ends.
3. The control circuit according to claim 1, wherein the switching unit includes a first transistor;
the grid electrode of the first transistor is connected with the second control signal end, the first pole of the first transistor is connected with the control module, and the second pole of the first transistor is connected with the storage unit.
4. The control circuit of claim 1, wherein the storage unit comprises a first capacitor, a first end of the first capacitor is connected to the switch unit, and a second end of the first capacitor is connected to ground.
5. The control circuit of claim 1, wherein the current source module comprises a current generating unit and a mirroring unit;
the current generation unit is connected with an external signal terminal and is configured to generate a target current signal according to a target signal input by the external signal terminal;
the mirror image unit is connected with the current generation unit and the control module, and is configured to copy the target current signal to obtain a mirror image current signal and output the mirror image current signal to the control module.
6. The control circuit according to claim 5, wherein the current generation unit includes a digital-to-analog converter, an operational amplifier, a second transistor, and a first resistor;
the digital-to-analog converter is respectively connected with the external signal end and the non-inverting input end of the operational amplifier;
the output end of the operational amplifier is connected with the grid electrode of the second transistor;
the first pole of the second transistor is connected with the mirror image unit, and the second pole of the second transistor is connected with the first end of the first resistor;
the first end of the first resistor is further connected with the inverting input end of the operational amplifier, and the second end of the first resistor is connected with the ground terminal.
7. The control circuit according to claim 5, wherein the mirroring unit includes a third transistor and a fourth transistor;
a gate of the third transistor is connected to the current generating unit, a first pole of the third transistor is connected to a high-level signal terminal, and a second pole of the third transistor is connected to the current generating unit;
the grid electrode of the fourth transistor is connected with the current generation unit, the first pole of the fourth transistor is connected with the high-level signal end, and the second pole of the fourth transistor is connected with the control module.
8. The control circuit of claim 1, wherein the control module comprises a fifth transistor;
the grid electrode of the fifth transistor is connected with the first control signal end, the first pole of the fifth transistor is connected with the current source module, and the second pole of the fifth transistor is connected with the switch unit of each delay module.
9. A driving method of a control circuit, applied to driving the control circuit according to any one of claims 1 to 8, the driving method comprising:
when the display panel is shut down, the control module is started according to a control signal input by the first control signal end so as to control the conduction of a path between the current source module and the delay module;
under the action of a high-level voltage signal input by a second control signal end of the Nth time delay module, a switch unit of the Nth time delay module is started, and a storage unit of the Nth time delay module is charged through the current source module;
when the storage unit of the Nth delay module is a high level voltage, outputting the high level voltage to a second control signal end of an (N + 1) th delay module so as to start a switch unit of the (N + 1) th delay module; n is a positive integer greater than 0;
when the switch unit of the nth delay module or the switch unit of the (N + 1) th delay module is turned on, the signal output end of the nth delay module outputs the high level voltage, so that the driving transistor corresponding to the signal output end of the nth delay module is turned on.
10. A display device characterized by comprising the control circuit according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010386625.1A CN111445883B (en) | 2020-05-09 | 2020-05-09 | Control circuit, driving method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010386625.1A CN111445883B (en) | 2020-05-09 | 2020-05-09 | Control circuit, driving method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111445883A true CN111445883A (en) | 2020-07-24 |
| CN111445883B CN111445883B (en) | 2021-10-29 |
Family
ID=71652172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010386625.1A Active CN111445883B (en) | 2020-05-09 | 2020-05-09 | Control circuit, driving method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111445883B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112615354A (en) * | 2020-12-17 | 2021-04-06 | 西安易朴通讯技术有限公司 | Overcurrent protection circuit, Buck circuit and control method |
| WO2023060779A1 (en) * | 2021-10-14 | 2023-04-20 | 惠科股份有限公司 | Current control circuit, display panel driving apparatus and display apparatus |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060244710A1 (en) * | 2005-04-27 | 2006-11-02 | Nec Corporation | Active matrix type display device and driving method thereof |
| CN102103294A (en) * | 2009-12-17 | 2011-06-22 | 联咏科技股份有限公司 | Gate drive circuit and relevant liquid crystal display |
| CN102842292A (en) * | 2011-06-24 | 2012-12-26 | 鸿富锦精密工业（深圳）有限公司 | Power supply management circuit and display device using same |
| CN104732948A (en) * | 2015-04-17 | 2015-06-24 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method of gate drive circuit, display panel and display device |
| CN107564491A (en) * | 2017-10-27 | 2018-01-09 | 北京京东方显示技术有限公司 | One kind shutdown discharge circuit, driving method, drive circuit and display device |
| CN107633832A (en) * | 2017-10-25 | 2018-01-26 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display device and its driving method |
| CN107644609A (en) * | 2017-10-11 | 2018-01-30 | 京东方科技集团股份有限公司 | The circuit and driving method, gate driving circuit of GOA signal end signal amplitudes during lifting shutdown |
| CN107705763A (en) * | 2017-10-12 | 2018-02-16 | 深圳市华星光电技术有限公司 | Level shifting circuit and liquid crystal display device |
| CN107731186A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | A kind of control circuit, control method and display device |
| CN110120201A (en) * | 2018-02-07 | 2019-08-13 | 京东方科技集团股份有限公司 | Eliminate circuit, its control method and the liquid crystal display device of power-off ghost shadow |
-
2020
- 2020-05-09 CN CN202010386625.1A patent/CN111445883B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060244710A1 (en) * | 2005-04-27 | 2006-11-02 | Nec Corporation | Active matrix type display device and driving method thereof |
| CN102103294A (en) * | 2009-12-17 | 2011-06-22 | 联咏科技股份有限公司 | Gate drive circuit and relevant liquid crystal display |
| CN102842292A (en) * | 2011-06-24 | 2012-12-26 | 鸿富锦精密工业（深圳）有限公司 | Power supply management circuit and display device using same |
| CN104732948A (en) * | 2015-04-17 | 2015-06-24 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method of gate drive circuit, display panel and display device |
| CN107644609A (en) * | 2017-10-11 | 2018-01-30 | 京东方科技集团股份有限公司 | The circuit and driving method, gate driving circuit of GOA signal end signal amplitudes during lifting shutdown |
| CN107705763A (en) * | 2017-10-12 | 2018-02-16 | 深圳市华星光电技术有限公司 | Level shifting circuit and liquid crystal display device |
| CN107633832A (en) * | 2017-10-25 | 2018-01-26 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display device and its driving method |
| CN107564491A (en) * | 2017-10-27 | 2018-01-09 | 北京京东方显示技术有限公司 | One kind shutdown discharge circuit, driving method, drive circuit and display device |
| CN107731186A (en) * | 2017-10-31 | 2018-02-23 | 京东方科技集团股份有限公司 | A kind of control circuit, control method and display device |
| CN110120201A (en) * | 2018-02-07 | 2019-08-13 | 京东方科技集团股份有限公司 | Eliminate circuit, its control method and the liquid crystal display device of power-off ghost shadow |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112615354A (en) * | 2020-12-17 | 2021-04-06 | 西安易朴通讯技术有限公司 | Overcurrent protection circuit, Buck circuit and control method |
| CN112615354B (en) * | 2020-12-17 | 2023-04-25 | 西安易朴通讯技术有限公司 | Overcurrent protection circuit, buck circuit and control method |
| WO2023060779A1 (en) * | 2021-10-14 | 2023-04-20 | 惠科股份有限公司 | Current control circuit, display panel driving apparatus and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111445883B (en) | 2021-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108962154B (en) | Shifting register unit, array substrate grid driving circuit, display and grid driving method | |
| CN107845403B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| US7872646B2 (en) | Power supply generating circuit, display apparatus, and portable terminal device | |
| CN106847156B (en) | Gate drive circuit and display device | |
| CN108806584B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| EP3086312A1 (en) | Shift register unit, gate drive circuit and display device | |
| CN103578402B (en) | Display panel | |
| CN109243351B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN111508449B (en) | Voltage supply circuit, display drive circuit, display device, and display drive method | |
| CN110264948B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN111445883B (en) | Control circuit, driving method thereof and display device | |
| CN108766381B (en) | Shift register circuit, array substrate and display device | |
| CN104537997B (en) | A kind of image element circuit and its driving method and display device | |
| CN106991958B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| US10553170B2 (en) | Scan driving circuit and apparatus thereof | |
| CN103632644A (en) | Display devices | |
| US7486267B2 (en) | Output devices and display devices utilizing same | |
| US11410629B2 (en) | Output voltage regulating circuit and liquid crystal display device | |
| CN111613170B (en) | Shift register unit and driving method thereof, grid driving circuit and display device | |
| CN112992097A (en) | Driving method, driving circuit and display device | |
| CN109616042B (en) | Pixel circuit, driving method thereof and display device | |
| CN106710554B (en) | Flashing drift optimization circuit and optimization method, array substrate, display device | |
| CN102779493B (en) | Shift register cell, shift register and liquid crystal indicator | |
| CN110956937B (en) | Control circuit, driving method thereof and display device | |
| CN217588405U (en) | Liquid crystal display device and control circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |