CN111435604A

CN111435604A - Decoding method, memory control circuit unit and memory storage device

Info

Publication number: CN111435604A
Application number: CN201910034821.XA
Authority: CN
Inventors: 梁鸣仁
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-01-15
Filing date: 2019-01-15
Publication date: 2020-07-21
Anticipated expiration: 2039-01-15
Also published as: CN111435604B

Abstract

The invention provides a decoding method, a memory control circuit unit and a memory storage device, wherein the method comprises the following steps: receiving a plurality of instructions; according to a first read command in the commands, reading a first entity programming unit by using a plurality of first read voltage groups in a plurality of read voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first read voltage groups is less than that of the plurality of read voltage groups; and when the failure of executing the first decoding operation on each of the plurality of first data occurs, executing other instructions different from the first reading instruction in the plurality of instructions.

Description

Decoding method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a decoding method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, when data is read from the rewritable nonvolatile memory module by using a read voltage, the memory management circuit can decode the read data to obtain the data to be read. However, when the decoding fails, the memory management circuit performs a re-Read (Retry-Read) mechanism to retrieve another Read voltage, and reads with the another Read voltage to retrieve the Read data and decode the Read data. The memory management circuit performs the decoding operation according to the retrieved verification bits to obtain another decoded data composed of a plurality of decoded bits. The above-mentioned mechanism of retrieving the read voltage and re-reading can be repeatedly executed until the number of times exceeds the preset number of times. When the re-read mechanism is performed more than a preset number of times, the memory management circuitry may, for example, instead perform the decode operation in the manner of other non-re-read mechanisms.

It should be noted that when a decoding operation is repeatedly performed (e.g., a re-fetch mechanism) for data read by a fetch instruction but a decoding failure occurs, subsequent fetch instructions in the fetch instruction are forced to wait and cannot be executed, which may result in inefficient execution of the fetch instruction.

Disclosure of Invention

The invention provides a decoding method, a memory control circuit unit and a memory storage device, which can reduce the time spent by a subsequent read instruction waiting for a previous read instruction to execute a complete decoding operation.

The invention provides a decoding method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the decoding method comprises the following steps: receiving a plurality of instructions; according to a first read command in the commands, reading a first entity programming unit by using a plurality of first read voltage groups in a plurality of read voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first read voltage groups is less than that of the plurality of read voltage groups; and when the failure of executing the first decoding operation on each of the plurality of first data occurs, executing other instructions of the plurality of instructions different from the first read instruction.

In an embodiment of the invention, after the step of executing other instructions of the plurality of instructions different from the first read instruction, the method further includes: according to the first read instruction, reading the first entity programming unit by using a plurality of second read voltage groups in the plurality of read voltage groups to respectively obtain a plurality of second data, and executing the first decoding operation on each second data in the plurality of second data. Wherein a number of the plurality of second read voltage sets is less than a number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the present invention, the method further includes: executing other instructions of the plurality of instructions different from the first read instruction when a failure occurs in executing the first decode operation on each of the plurality of second data; and when the number of other executed instructions in the plurality of instructions different from the first read instruction reaches a threshold value, reading the first entity programming unit by using at least one remaining read voltage group out of the plurality of read voltage groups and the plurality of second read voltage groups according to the first read instruction in the plurality of instructions to obtain at least one third data, and executing the first decoding operation on the third data.

In an embodiment of the present invention, the method further includes: when the first decoding operation on the third data fails, reading the first entity programming unit to obtain fourth data, and performing a second decoding operation on the fourth data, wherein an algorithm used by the first decoding operation is different from an algorithm used by the second decoding operation.

In an embodiment of the invention, the number of the first read voltage sets is greater than or equal to five and the number of the first read voltage sets is less than or equal to ten.

In an embodiment of the invention, the number of the other instructions different from the first read instruction is three.

In an embodiment of the invention, the other instruction different from the first read instruction is a read instruction.

The invention provides a memory control circuit unit, which is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the memory control circuit unit comprises: host interface, memory interface and memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for executing the following operations: receiving a plurality of instructions; according to a first read command in the commands, reading a first entity programming unit by using a plurality of first read voltage groups in a plurality of read voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first read voltage groups is less than that of the plurality of read voltage groups; and when the failure of executing the first decoding operation on each of the plurality of first data occurs, executing other instructions of the plurality of instructions different from the first read instruction.

In an embodiment of the invention, after performing operations of other instructions of the plurality of instructions different from the first read instruction, the memory management circuit is further configured to read the first physical programming unit using a plurality of second read voltage sets of the plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and perform the first decoding operation on each of the plurality of second data. Wherein a number of the plurality of second read voltage sets is less than a number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the invention, when the failure of performing the first decoding operation on each of the plurality of second data occurs, the memory management circuit is further configured to execute other instructions of the plurality of instructions different from the first read instruction. When the number of other instructions of the plurality of instructions that have been executed and are different from the first read instruction reaches a threshold value, the memory management circuit is further configured to read the first physical programming unit using at least one remaining read voltage group of the plurality of read voltage groups other than the first read voltage groups and the second read voltage groups to obtain at least one third data according to the first read instruction of the plurality of read instructions, and perform the first decoding operation on the third data.

In an embodiment of the invention, when the first decoding operation performed on the third data fails, the memory management circuit is further configured to read the first physical program unit to obtain a fourth data, and perform a second decoding operation on the fourth data, wherein an algorithm used in the first decoding operation is different from an algorithm used in the second decoding operation.

The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: receiving a plurality of instructions; according to a first read command in the commands, reading a first entity programming unit by using a plurality of first read voltage groups in a plurality of read voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first read voltage groups is less than that of the plurality of read voltage groups; and when the failure of executing the first decoding operation on each of the plurality of first data occurs, executing other instructions of the plurality of instructions different from the first read instruction.

In an embodiment of the invention, after performing operations of other instructions of the plurality of instructions different from the first read instruction, the memory control circuit unit is further configured to read the first physical programming unit using a plurality of second read voltage sets of the plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and perform the first decoding operation on each of the plurality of second data. Wherein a number of the plurality of second read voltage sets is less than a number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

In an embodiment of the invention, when the failure of performing the first decoding operation on each of the plurality of second data occurs, the memory control circuit unit is further configured to execute other instructions different from the first read instruction. When the number of instructions of the plurality of instructions that have been executed and are different from the first read instruction reaches a threshold value, the memory control circuit unit is further configured to read the first physical programming unit using at least one remaining read voltage group of the plurality of read voltage groups other than the first read voltage groups and the second read voltage groups to obtain at least one third data according to the first read instruction of the plurality of instructions, and perform the first decoding operation on the third data.

In an embodiment of the invention, when the first decoding operation performed on the third data fails, the memory control circuit unit is further configured to read the first physical programming unit to obtain fourth data, and perform a second decoding operation on the fourth data. Wherein the algorithm used by the first decoding operation is different from the algorithm used by the second decoding operation.

Based on the above, the decoding method, the memory control circuit unit and the memory storage device of the present invention can suspend the decoding corresponding to a read instruction when the re-reading mechanism of the data read by the read instruction is partially executed and the re-reading mechanisms of the portions fail, and execute other instructions subsequent to the read instruction first, thereby reducing the time taken by the subsequent instruction to wait for the previous read instruction to execute the complete decoding operation.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment.

FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

FIG. 7 is a graph illustrating a statistical distribution of gate voltages corresponding to write data stored in an array of memory cells, according to an example embodiment.

FIG. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment.

FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

FIG. 10 is a diagram illustrating an example of a physically erased cell according to the present example embodiment.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Fig. 12 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

FIG. 13 is a diagram illustrating a re-read mechanism, according to an example embodiment.

FIG. 14 is a diagram illustrating multiple read voltage sets for a re-read scheme, according to an example embodiment.

FIG. 15 is a flowchart illustrating a decoding method according to an example embodiment.

[ notation ] to show

10: memory storage device

11: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: main machine board

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

2202: memory cell array

2204: word line control circuit

2206: bit line control circuit

2208: row decoder

2210: data input/output buffer

2212: control circuit

502: memory cell

504: bit line

506: word line

508: common source line

512: select gate drain transistor

514: selective gate source transistor

L SB least significant bit

CSB: intermediate significant bit

MSB: most significant bit

VA, VA1, VB, VC, VD, VE, VF, VG, 1440-1444: read voltage

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801(1) -801 (r): position of

820: encoding data

810(0) -810 (E): physical programming unit

1410. 1420: distribution of

1430: region(s)

G1-GX: read voltage set

V1-V1N, V2-V2N, V3-V3N, V4-V4N, V5-V5N, VX-VXN: read voltage

S1501: step of receiving a plurality of instructions

S1503: according to a first read command of the commands, reading the first entity programming unit by using a plurality of first read voltage groups of a plurality of read voltage groups to respectively obtain a plurality of first data, and executing a first decoding operation on each first data of the first data

S1505: judging whether one of the first data is decoded successfully

S1507: executing other instructions of the plurality of instructions other than the first read instruction

S1509: according to the first read command, reading the first physical programming unit by using a plurality of second read voltage groups in the plurality of read voltage groups to respectively obtain a plurality of second data, and executing a first decoding operation on each second data in the plurality of second data

S1511: determining whether one of the plurality of second data is decoded successfully

S1513: executing other instructions of the plurality of instructions other than the first read instruction

S1515: when the number of other executed instructions different from the first read instruction reaches a threshold value, reading the first entity programming unit by using the rest read voltage groups in the read voltage groups according to the first read instruction to obtain third data, and executing a first decoding operation on the third data

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package memory devices (eMCP) 342 to electrically connect the memory module directly to the embedded memory device on the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Multi, Embedded) Multimedia Card (MMC, Multimedia Card (Multimedia Card), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-chip package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 may be a Single level Cell (Single L ev Cell, S L C) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-level Cell (Multi L ev Cell, M L C) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a multiple level Cell (T L ev Cell, T L C) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array is described below as a two-dimensional array. However, it should be noted that the following exemplary embodiment is only an example of the memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

Referring to fig. 5 and fig. 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

In the present exemplary embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of Select Gate Drain (SGD) transistors 512 and a plurality of Select Gate Source (SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (fig. 6) connecting the memory cells. The memory cells 502 are arranged in an array (or stacked) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208 and the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 controls the voltage applied to the word line 506, the bit line control circuit 2206 controls the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data.

The memory cells in the rewritable nonvolatile memory module 406 store multiple bits (bits) with a change in threshold voltage. Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". Each memory cell of the memory cell array 2202 has multiple memory states as the threshold voltage changes. And the reading voltage can judge which storage state the memory cell belongs to, thereby obtaining the bit stored by the memory cell.

Referring to fig. 7, taking M L C NAND flash as an example, each memory cell has 4 memory states with different threshold voltages, and the memory states respectively represent bits such as "11", "10", "00" and "01", in other words, each memory state includes a least Significant Bit (L east Significant Bit, L SB) and a most Significant Bit (mostsignifican Bit, MSB). in the present exemplary embodiment, the 1 st Bit from the left side of the memory states (i.e., "11", "10", "00" and "01") is L SB, and the 2 nd Bit from the left side is MSB.

In an example embodiment where a memory cell may store multiple bits (e.g., M L C or T L C NAND flash memory module), the physical program cells belonging to the same word line may be classified into at least a lower physical program cell and an upper physical program cell, for example, in the M L C NAND flash memory module, the least Significant Bit (L eastsignifican Bit, L SB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (mostsifican Bit, MSB) of the memory cell belongs to the upper physical program cell.

Fig. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment, which is an example of an M L CNAND type flash memory.

Referring to FIG. 8, a read operation of the memory cells of the memory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify data stored in the memory cells by the conductive states of the memory cell channels. A verify bit (VA) is used to indicate whether the memory cell channel is turned on when the read voltage VA is applied; the verification bit (VC) is used for indicating whether the memory cell channel is conducted or not when the reading voltage VC is applied; the Verification Bit (VB) is used to indicate whether the memory cell channel is turned on when the read voltage VB is applied. It is assumed herein that the verify bit is "1" indicating that the corresponding memory cell channel is turned on, and the verify bit is "0" indicating that the corresponding memory cell channel is not turned on. As shown in fig. 8, it is possible to determine which memory state the memory cell is in by verifying the bits (VA) to (VC), and to acquire the stored bit.

Referring to fig. 9, taking a T L C NAND flash memory as an example, each memory state includes a least significant bit L SB of the 1 st bit from the left, a middle significant bit (CSB) of the 2 nd bit from the left, and a most significant bit msb of the 3 rd bit from the left, in this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010", and "011") according to different threshold voltages, and the bits stored by the memory cell can be identified by applying the read voltages VA to VG to the control gates.

It should be noted that the arrangement order of the 8 storage states in fig. 9 can be determined by the design of the manufacturer, but is not limited to the arrangement manner of the present example.

For example, if the rewritable nonvolatile memory module 406 is an M L CNAND flash memory module, the memory cells at the intersections of the same word line and a plurality of bit lines constitute 2 physical program cells, i.e., an upper physical program cell and a lower physical program cell, and an upper physical program cell and a lower physical program cell may be collectively referred to as a physical program cell group, and particularly, if the data to be read is located in a lower physical program cell of a program physical cell group, the value of each bit in the lower physical program cell may be identified using the read voltage VA in fig. 8, and if the data to be read is located in an upper physical program cell of a physical program cell group, the value of each bit in the upper physical program cell may be identified using the read voltage VB and the read voltage VC in fig. 8.

Alternatively, if the rewritable nonvolatile memory module 406 is a T L C NAND flash memory module, the memory cells at the intersections of the same word line and bit lines constitute 3 physical program cells, i.e., an upper physical program cell, a middle physical program cell, and a lower physical program cell, and one upper physical program cell, one middle physical program cell, and one lower physical program cell may be collectively referred to as a physical program cell group.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

Referring to fig. 10, in the present exemplary embodiment, it is assumed that one physically erased cell is composed of a plurality of physically programmed cell groups, wherein each of the physically programmed cell groups includes a lower physically programmed cell, a middle physically programmed cell and an upper physically programmed cell composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and the other physical programming cells are classified into a plurality of physical programming cell groups according to the same manner.

Referring to FIG. 11, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706 and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit element included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.

In the exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be stored in a program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware form. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 706 is electrically connected to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.

In the exemplary embodiment, the error checking and correcting circuit 708 may encode data stored in the same physical programming unit in a single-frame manner, or encode data stored in a plurality of physical programming units in a multi-frame manner, the single-frame encoding and the multi-frame encoding may respectively employ at least one of low-density parity-check code (L DPC), BCH, convolutional code (convolutional code), turbo code, or other encoding algorithms, or, in an exemplary embodiment, the multi-frame encoding may employ Reed-solomon (RS-solomon) algorithms or exclusive or (XOR) algorithms, further, in another exemplary embodiment, more encoding algorithms not listed may be employed, which is not described herein, according to the employed encoding algorithm 708, the error checking and correcting circuit may encode data to generate more error checking codes and/or corresponding error checking codes, which are generally referred to as an error checking code or error checking code, and is generally referred to as an error checking code or error checking code.

Referring to fig. 12, taking the data stored in the encoded entity programming units 810(0) to 810(E) as an example to generate the corresponding encoded data 820, at least a portion of the data stored in each of the entity programming units 810(0) to 810(E) can be regarded as a frame. In multi-frame coding, data in the physical programming units 810(0) to 810(E) is coded according to the position of each bit (or byte). For example,bit b at position 801(1)₁₁、b₂₁、…、b_p1Will be encoded as bit b in the encoded data 820_o1Bit b at position 801(2)₁₂、b₂₂、…、b_p2Will be encoded as bit b in the encoded data 820_o2(ii) a By analogy, bit b at position 801(r)_1r、b_2r、…、b_prWill be encoded as bit b in the encoded data 820_or. Thereafter, the data read from the physical programming units 810(0) -810 (E) can be decoded according to the encoded data 820 to attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 12, the data for generating the encoded data 820 may also include redundant bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the entity programming units 810(0) -810 (E). Take the data stored in the entity programming unit 810(0) as an example, wherein the redundant bits are generated by performing single frame encoding on the data bits stored in the entity programming unit 810(0), for example. In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810(0), the data read from the physical programming unit 810(0) can be decoded by using the redundancy bits (e.g., the single frame coded data) in the physical programming unit 810(0) for error detection and correction. However, when the decoding using the redundancy bits in the physical programming unit 810(0) fails (e.g., the number of bits error of the data stored in the decoded physical programming unit 810(0) is greater than a threshold), a Retry-Read mechanism may be used to attempt to Read the correct data from the physical programming unit 810 (0). Details about the re-reading mechanism will be described later. When the correct data cannot be Read from the physical programming units 810(0) by the Retry-Read mechanism, the encoded data 820 and the data of the physical programming units 810(1) to 810(E) can be Read, and the decoding is performed according to the encoded data 820 and the data of the physical programming units 810(1) to 810(E) to try to correct the errors in the data stored in the physical programming units 810 (0). That is, in the exemplary embodiment, when decoding using the encoded data generated by the single-frame encoding fails and reading using the re-Read (Retry-Read) mechanism fails, the encoded data generated by the multi-frame encoding is decoded instead.

In particular, FIG. 13 is a diagram illustrating a re-read mechanism, according to an example embodiment.

Referring to FIG. 13, for example using the S L C flash memory, distribution 1410 and distribution 1420 are used to indicate the memory states of a plurality of first memory cells, and

distributions

1410 and 1420 represent different memory states, respectively.

In this example embodiment, when the memory cells are to be read, the memory management circuit 702 selects a predetermined read voltage (e.g., the read voltage 1441) to read the memory cells to obtain the verification bits of the memory cells. The error checking and correcting circuit 708 performs a decoding operation according to the verification bits of the memory cells to generate a plurality of decoded bits, and the decoded bits may be combined into a decoded data (also referred to as a codeword).

If the decoding fails, it indicates that the memory cells store uncorrectable error bits. If the decoding fails, in the re-reading mechanism, the memory management circuit 702 re-obtains another read voltage, and reads the first memory cells by using the another read voltage (e.g., the read voltage 1442) to re-obtain the verification bits of the memory cells. The memory management circuit 702 performs the decoding operation according to the retrieved verification bits to obtain another decoded data composed of a plurality of decoded bits. In an exemplary embodiment, the ECC circuit 708 determines whether the decoded data is a valid codeword according to the syndrome corresponding to the decoded data. If the decoded data is not a valid codeword, the memory management circuit 702 determines that the decoding fails. If the number of times of retrieving the read voltage does not exceed the predetermined number of times, the memory management circuit 702 retrieves another read voltage (e.g., the read voltage 1443) again, and reads the memory cell according to the retrieved read voltage 1443 to retrieve the verification bit and perform the first decoding operation.

In other words, when there are uncorrectable error bits, some of the verification bits of the memory cells are changed by retrieving the read voltage, thereby giving an opportunity to change the decoding result of the decoding operation. Logically, the re-fetching of the read voltage is to flip (flip) bits of a codeword and re-decode the new codeword. In some cases, codewords that cannot be decoded before flipping (with uncorrectable erroneous bits), may be decoded after flipping. Also, in an exemplary embodiment, the memory management circuit 702 attempts to decode several times until the number of attempts exceeds a predetermined number. However, the present invention does not limit the number of times to the preset number.

It should be noted that the decoding operation performed on the encoded data generated by the single frame encoding can be divided into hard bit mode (hard bit mode) decoding and soft bit mode (soft bit mode) decoding. In both the hard bit mode decoding and the soft bit mode decoding, decoding is performed according to the "decoding initial value" of the memory cell. In the hard bit pattern decoding process, the decoding initial value of the memory cell is divided into two values (e.g., n and-n) according to a verification bit. For example, if the verification bit is "1", the memory management circuit 702 sets the decoding initial value of the corresponding memory cell to-n; if the verification bit is "0", the decoding initial value is n. Where n is a positive number, the present invention does not limit the value of the positive integer n. That is, iterative decoding performed according to two values is also called hard bit mode (hard bit mode) decoding. However, the step of changing the read voltage can also be applied to soft bit mode (soft bit mode) decoding, in which the decoding initialization value of each memory cell is determined according to a plurality of verification bits. It should be noted that, in either hard bit mode or soft bit mode, the probability value of a bit is calculated in iterative decoding, and thus all the methods belong to the probability decoding algorithm. The detailed implementation of the hard bit pattern decoding and the soft bit pattern decoding can be known from the prior art and will not be described herein.

It is noted that in FIG. 13, the example of the S L C flash memory is illustrated, but the step of retrieving the read voltage can be applied to the M L C or T L C flash memory, as shown in FIG. 8, changing the read voltage VA flips L SB of a memory cell and changing the read voltage VB or VC flips MSB of a memory cell, thus, changing the read voltage VA, VB or VC can change a codeword into another codeword.

It should be noted that, in the embodiment, when a physical programming unit in the rewritable nonvolatile memory module 406 is to be read, the memory management circuit 702 first uses a preset voltage set to read the physical programming unit and performs hard bit pattern decoding according to data read by using the preset voltage set. When decoding fails, the above-described re-reading mechanism is performed to perform hard bit pattern decoding again. When a Read-back (Retry-Read) mechanism fails, the memory management circuitry 702 performs soft-bit mode decoding. When the soft bit mode decoding fails, the memory management circuit 702 decodes the encoded data generated by the multi-frame coding instead.

It should be noted that when a decoding operation is repeatedly performed (e.g., a re-fetch mechanism) for data read by a fetch instruction but a decoding failure occurs, subsequent fetch instructions in the fetch instruction need to wait and cannot be executed, which may result in inefficient execution of the fetch instruction.

Therefore, the present invention provides a decoding method, when a read command (also referred to as a first read command) is used to read data from a physical programming unit (also referred to as a first physical programming unit), if a partial re-reading mechanism executed in the reading process fails, the memory management circuit 702 will first suspend decoding of the data read from the first physical programming unit, and will first execute other commands (e.g., read commands) subsequent to the first read command. After executing other subsequent instructions, the memory management circuit 702 returns to execute another part of the re-reading mechanism for reading according to the first read instruction and executing another part of the data read by the first read instruction.

In more detail, FIG. 14 is a diagram illustrating a plurality of read voltage sets for a re-read scheme according to an example embodiment. Referring to FIG. 14, it is assumed that the memory management circuit 702 receives a plurality of commands from the host system 11. It is assumed that the instructions include a first read instruction, and the instructions other than the first read instruction are read instructions. However, in other embodiments, the other commands besides the first read command may also be other commands (for example, a write command, an erase command, a garbage collection command, or a block wear leveling command, which is not limited in the present invention). Assume that a first read command of the read commands is used to read a first physical program cell. First, the memory management circuit 702 reads the first physical program cell using a predetermined voltage set (not shown) and performs hard bit pattern decoding according to the data read using the predetermined voltage set. When the decoding fails, the memory management circuit 702 performs a re-reading mechanism to select the read voltage group G1 in FIG. 14, and reads the first physical program cells according to the read voltages V1-V1N in the read voltage group G1 to obtain the data read by the read voltages V1-V1N. Thereafter, the memory management circuit 702 performs hard bit pattern decoding again on the data read out using the read voltages V1-V1N.

When the hard bit pattern decoding of the data read by the read voltages V1-V1N fails, the memory management circuit 702 performs a re-read mechanism to select the read voltage group G2 of FIG. 14 and reads the first physical program cells according to the read voltages V2-V2N of the read voltage group G2 to obtain the data read by the read voltages V2-V2N. Thereafter, the memory management circuit 702 performs hard bit pattern decoding again on the data read out using the read voltages V2-V2N.

When the hard bit pattern decoding of the data read by the read voltages V2-V2N fails, the memory management circuit 702 selects the read voltage group G3 shown in FIG. 14, and reads the first physical program cells according to the read voltages V3-V3N of the read voltage group G3 to obtain the data read by the read voltages V3-V3N. Thereafter, the memory management circuit 702 performs hard bit pattern decoding again on the data read out using the read voltages V3-V3N.

When the hard bit pattern decoding of the data read by the read voltages V3-V3N fails, the memory management circuit 702 performs a re-read mechanism to select the read voltage group G4 of FIG. 14 and reads the first physical program cells according to the read voltages V4-V4N of the read voltage group G4 to obtain the data read by the read voltages V4-V4N. Thereafter, the memory management circuit 702 performs hard bit pattern decoding again on the data read out using the read voltages V4-V4N.

When the hard bit pattern decoding of the data read by the read voltages V4-V4N fails, the memory management circuit 702 performs a re-read mechanism to select the read voltage group G5 of FIG. 14 and reads the first physical program cells according to the read voltages V5-V5N of the read voltage group G5 to obtain the data read by the read voltages V5-V5N. Thereafter, the memory management circuit 702 performs hard bit pattern decoding again on the data read out using the read voltages V5-V5N.

When the hard bit pattern decoding of the data read by the read voltages V5-V5N fails, the memory management circuit 702 suspends the execution of the first read command and executes at least one other command (also referred to as a first other command) subsequent to the first read command. In this embodiment, the number of the first other instructions is, for example, three. In this embodiment, it is assumed that the first read instruction is an instruction ordered first among all instructions, and the first other instruction is an instruction ordered second, third, and fourth among all instructions. However, the invention is not intended to be limited to the number of first further instructions.

Here, the read voltage groups G1 to G5 may be collectively referred to as a "first read voltage group". The data read from the first physical program cells using the read voltage groups G1-G5 and used for performing the hard bit pattern decoding can be collectively referred to as "first data". The operation of hard bit pattern decoding may be referred to as a "first decoding operation". It should be noted that the number of the first read voltage sets is five in the embodiment, however, in the preferred embodiment, the number of the first read voltage sets is greater than or equal to five and less than or equal to ten.

Assume that memory management circuit 702 returns to executing the first read instruction after successfully executing the first other instruction. More specifically, the memory management circuit 702, according to the first read command, sequentially performs a re-read mechanism that has not been previously performed to select the read voltage group G6 (not shown) in fig. 14, and reads the first physical program cells according to the read voltages in the read voltage group G6 and performs the hard bit pattern decoding again according to the read data.

When decoding of data read using the read voltage group G6 fails, the memory management circuit 702 performs the re-read mechanism again. Assuming that the hard bit pattern decoding of the data (also referred to as the second data) read by the read voltage groups G7-G10 (not shown) by the memory management circuit 702 fails in the subsequent re-read mechanism, the memory management circuit 702 suspends the execution of the first read command and executes at least one second other command subsequent to the first other command. In the present embodiment, the number of the second other instructions is, for example, three. In this embodiment, it is assumed that the first other instruction refers to the instructions ordered at the second, third and fourth of all the instructions, and therefore the second other instruction refers to the instructions ordered at the fifth, sixth and seventh of all the instructions. In addition, the read voltage groups G6-G10 may be collectively referred to as a "second read voltage group". It should be noted that the first other instruction and the second other instruction may be collectively referred to as "other instructions different from the first read instruction".

Assume that after the second other instruction is successfully executed, the memory management circuit 702 determines whether the number of instructions successfully executed subsequent to the first read instruction (i.e., the number of other instructions executed that are different from the first read instruction) reaches a threshold value, for example. When the number of other executed instructions different from the first read instruction is not greater than the threshold value, if the memory management circuit 702 fails to execute a part of the re-read mechanism again, the memory management circuit 702 may suspend executing the first read instruction again and execute a plurality of instructions ordered after the second other instruction first.

However, when the number of other instructions that have been executed that are different from the first read instruction is greater than the threshold, the memory management circuit 702 returns to execute the first read instruction to complete the decoding process (e.g., decoding the soft bit mode and the remaining unexecuted re-read mechanism). More specifically, the memory management circuit 702, according to the first read command, sequentially executes the above-mentioned re-read mechanism not yet executed to select the read voltage group G11 (not shown) in fig. 14, and reads the first physical program cells according to the read voltages in the read voltage group G11 and performs the hard bit pattern decoding again according to the read data. When decoding of data read using the read voltage group G11 fails, the memory management circuit 702 performs the re-read mechanism again. Assuming that in the subsequent re-reading mechanism, when the memory management circuit 702 fails to decode the hard bit pattern of the data read by using the read voltage groups G12 (not shown) -GX, the memory management circuit 702 does not suspend executing the first read command but executes the soft bit pattern decoding (also referred to as a second decoding operation) according to the first read command. In more detail, the memory management circuit 702 can read the first physical program cell to obtain a data (also referred to as a fourth data) using another read voltage set (not shown), and perform soft bit mode decoding on the fourth data, for example.

Here, the data read by using the read voltage groups G11 to GX may be collectively referred to as "third data".

Referring to fig. 15, in step S1501, the memory management circuit 702 receives a plurality of instructions. In step S1503, the memory management circuit 702 reads the first physical programming unit using a plurality of first read voltage sets of the plurality of read voltage sets according to a first read command of the plurality of commands to obtain a plurality of first data respectively, and performs a first decoding operation on each of the plurality of first data. In step S1505, the memory management circuit 702 determines whether one of the plurality of first data is decoded successfully. When one of the plurality of first data is successfully decoded, the flow of fig. 15 is ended. When a failure occurs in performing the first decoding operation on each of the plurality of first data, in step S1507, the memory management circuit 702 executes another instruction of the plurality of instructions other than the first read instruction. After executing other instructions different from the first read instruction, in step S1509, the memory management circuit 702 reads the first physical program unit using a plurality of second read voltage sets of the plurality of read voltage sets according to the first read instruction to obtain a plurality of second data respectively, and performs a first decoding operation on each of the plurality of second data. In step S1511, the memory management circuit 702 determines whether one of the plurality of second data is decoded successfully. When one of the plurality of second data is successfully decoded, the flow of fig. 14 is ended. When a failure occurs in performing the first decoding operation on each of the plurality of second data, in step S1513, the memory management circuit 702 executes another instruction different from the first read instruction in the plurality of read instructions. Thereafter, in step S1515, when the number of other executed instructions different from the first read instruction reaches a threshold value, the memory management circuit 702 reads the first physical program unit according to the first read instruction by using the remaining read voltage sets of the read voltage sets to obtain third data, and performs a first decoding operation on the third data.

In summary, the decoding method, the memory control circuit unit and the memory storage device of the present invention can suspend the decoding corresponding to a read instruction when the re-reading mechanism of the data read by the read instruction is partially executed and the re-reading mechanisms of the portions fail, and execute other instructions subsequent to the read instruction first, thereby avoiding the time spent by the subsequent instruction waiting for the previous read instruction to execute the complete decoding operation.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A decoding method for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module having a plurality of physically erasable units, each of the plurality of physically erasable units having a plurality of physically programmable units, the decoding method comprising:

receiving a plurality of instructions;

reading a first entity programming unit by using a plurality of first reading voltage groups in a plurality of reading voltage groups according to a first reading instruction in the plurality of instructions to respectively obtain a plurality of first data, and executing a first decoding operation on each first data in the plurality of first data, wherein the number of the plurality of first reading voltage groups is less than that of the plurality of reading voltage groups; and

when the failure of the first decoding operation on each of the plurality of first data occurs, executing other instructions of the plurality of instructions different from the first read instruction.

2. The decoding method of claim 1, wherein after the step of executing other ones of the plurality of instructions other than the first read instruction, the method further comprises:

reading the first entity programming unit by using a plurality of second reading voltage groups in a plurality of reading voltage groups according to the first reading instruction so as to respectively obtain a plurality of second data, and executing the first decoding operation on each second data in the plurality of second data,

wherein a number of the plurality of second read voltage sets is less than a number of the plurality of read voltage sets and the plurality of second read voltage sets is different from the plurality of first read voltage sets.

3. The decoding method of claim 2, the method further comprising:

executing other instructions of the plurality of instructions different from the first read instruction when a failure occurs in executing the first decode operation on each of the plurality of second data; and

when the number of other instructions of the plurality of instructions that have been executed other than the first read instruction reaches a threshold value,

according to the first read command of the plurality of commands, reading the first physical programming unit by using at least one remaining read voltage group except the first read voltage groups and the second read voltage groups of the plurality of read voltage groups to obtain at least one third data, and performing the first decoding operation on the third data.

4. The decoding method of claim 3, the method further comprising:

reading the first physical programming unit to obtain fourth data when the first decoding operation performed on the third data fails, and performing a second decoding operation on the fourth data,

wherein the algorithm used by the first decoding operation is different from the algorithm used by the second decoding operation.

5. The decoding method of claim 1, wherein a number of the plurality of first read voltage groups is greater than or equal to five and a number of the plurality of first read voltage groups is less than or equal to ten.

6. The decoding method according to claim 1, wherein the number of the other instructions different from the first read instruction is three.

7. The decoding method according to claim 1, wherein the other instruction different from the first read instruction is a read instruction.

8. A memory control circuit unit is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, the memory control circuit unit comprises:

a host interface for electrically connecting to a host system;

a memory interface for electrically connecting to the rewritable nonvolatile memory module; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit is to receive a plurality of instructions,

wherein the memory management circuit is further configured to read a first physical programming cell using a plurality of first read voltage sets of a plurality of read voltage sets to obtain a plurality of first data respectively according to a first read command of the plurality of commands, and perform a first decoding operation on each of the plurality of first data, wherein the number of the plurality of first read voltage sets is smaller than the number of the plurality of read voltage sets,

when the failure of performing the first decoding operation on each of the plurality of first data occurs, the memory management circuit is further configured to execute other instructions of the plurality of instructions different from the first read instruction.

9. The memory control circuitry unit of claim 8, wherein after execution of operations of others of the plurality of instructions other than the first read instruction,

the memory management circuit is further configured to read the first physical programming unit using a plurality of second read voltage sets of the plurality of read voltage sets to obtain a plurality of second data respectively according to the first read command, and perform the first decoding operation on each of the plurality of second data,

10. The memory control circuit cell of claim 9,

the memory management circuit is further configured to execute another one of the plurality of instructions different from the first read instruction when the failure to perform the first decode operation on each of the plurality of second data occurs, an

the memory management circuit is further configured to read the first physical programming unit using at least one remaining read voltage group other than the first and second read voltage groups of the read voltage groups according to the first read command of the commands to obtain at least one third data, and perform the first decoding operation on the third data.

11. The memory control circuit cell of claim 10,

when the first decoding operation performed on the third data fails, the memory management circuit is further configured to read the first physical program unit to obtain fourth data, and perform a second decoding operation on the fourth data,

12. The memory control circuit cell of claim 8, wherein a number of the plurality of first read voltage groups is greater than or equal to five and a number of the plurality of first read voltage groups is less than or equal to ten.

13. The memory control circuit unit of claim 8, wherein the number of other instructions than the first read instruction is three.

14. The memory control circuitry unit of claim 8, wherein the other instruction than the first read instruction is a read instruction.

15. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry unit is to receive a plurality of instructions,

wherein the memory control circuit unit is further configured to read the first physical programming unit using a plurality of first read voltage sets of the plurality of read voltage sets to obtain a plurality of first data respectively according to a first read command of the plurality of commands, and perform a first decoding operation on each of the plurality of first data, wherein the number of the plurality of first read voltage sets is smaller than the number of the plurality of read voltage sets,

when the first decoding operation performed on each of the plurality of first data fails, the memory control circuit unit is further configured to execute other instructions of the plurality of instructions different from the first read instruction.

16. The memory storage device of claim 15, wherein subsequent to execution of operations of other of the plurality of instructions other than the first read instruction,

the memory control circuit unit is further configured to read the first physical programming unit using a plurality of second read voltage sets of the plurality of read voltage sets to obtain a plurality of second data respectively according to the first read command, and perform the first decoding operation on each of the plurality of second data,

17. The memory storage device of claim 16,

the memory control circuit unit is further configured to execute another one of the plurality of instructions different from the first read instruction when the failure of the first decoding operation on each of the plurality of second data occurs, an

the memory control circuit unit is further configured to read the first physical programming unit using at least one remaining read voltage group other than the first and second read voltage groups of the read voltage groups according to the first read command of the commands to obtain at least one third data, and perform the first decoding operation on the third data.

18. The memory storage device of claim 17,

the memory control circuit unit is further configured to read the first physical programming unit to obtain fourth data and perform a second decoding operation on the fourth data when the first decoding operation performed on the third data fails,

19. The memory storage device of claim 15, wherein a number of the plurality of first read voltage sets is greater than or equal to five and a number of the plurality of first read voltage sets is less than or equal to ten.

20. The memory storage device of claim 15, wherein the number of other instructions than the first read instruction is three.

21. The memory storage device of claim 15, wherein the other instruction than the first read instruction is a read instruction.