CN111431592B

CN111431592B - Power amplifier protection method, power amplifier protection device and computer storage medium

Info

Publication number: CN111431592B
Application number: CN202010239024.8A
Authority: CN
Inventors: 王天蒙
Original assignee: Comba Network Systems Co Ltd
Current assignee: Comba Network Systems Co Ltd
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2022-05-31
Anticipated expiration: 2040-03-30
Also published as: CN111431592A

Abstract

The application provides a power amplifier protection method, a device and a computer storage medium, wherein the method comprises the following steps: the programmable logic device monitors the running state of the communication equipment; when the operation state is abnormal, the programmable logic device closes the baseband signal and closes the enabling of the pre-pushing stage of the power amplifier in the communication equipment, and the baseband signal is the baseband signal output to the transceiver of the communication equipment. When the operation state is abnormal, the method indicates that the stray phenomenon is likely to occur in the communication equipment, and at the moment, the baseband signal is closed in time through the programmable logic device, and the enabling of the pre-pushing stage of the power amplifier is closed, so that the power input into the power amplifier circuit is stopped, the power amplifier circuit is prevented from being burnt, and the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so that the running state of the communication equipment is monitored very quickly, the output of a baseband signal to the transceiver is closed in time, the enabling of a pre-pushing stage of the power amplifier is closed, and large stray can be avoided quickly so as to effectively protect the power amplifier circuit in time.

Description

Power amplifier protection method, power amplifier protection device and computer storage medium

Technical Field

The present disclosure relates to the field of power amplifier protection technologies, and in particular, to a power amplifier protection method, a power amplifier protection device, and a computer storage medium.

Background

At present, the power amplifier (power amplifier) circuit protection mainly focuses on circuit design and optimization to realize power amplifier protection.

However, the communication device is susceptible to factors such as interface timing, plugging and unplugging of optical fibers, power-up and power-down, temperature change and the like, and large stray can be generated in a very short time. When the spurious signal is not detected and exceeds the bearing range of the power amplifier, the power amplifier can be burnt. Therefore, for the influence of the spurious factors on the power amplifier, how to avoid the spurious factors for the power amplifier becomes one of the problems faced by the protection of the current power amplifier.

Disclosure of Invention

The invention mainly aims to provide a power amplifier protection method, a power amplifier protection device and a computer storage medium.

A power amplifier protection method comprises the following steps:

the programmable logic device monitors the running state of the communication equipment;

and when the running state is abnormal, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of a power amplifier in the communication equipment, wherein the baseband signal is the baseband signal output to a transceiver of the communication equipment.

In one embodiment, after the step of monitoring the operation state of the communication device by the programmable logic device, the method further comprises:

and when the running state is abnormal, the monitoring processor closes the grid voltage of a pushing stage and a final stage of the power amplifier.

In one embodiment, the operational state includes a light port state;

the step of monitoring the operating state of the communication device by the programmable logic device comprises the following steps:

acquiring a plurality of light indication information of the optical signal of the communication equipment;

when any one of the light indication information shows abnormality, judging that the state of the light port is abnormal;

and when the plurality of indication information of the optical signal belong to the normal range, judging that the state of the optical port is normal.

In one embodiment, the operational state comprises a link setup state of a communication link between the programmable logic device and a transceiver;

monitoring a synchronous port state, an effective port state and a ready port state, wherein the ready port state is used for indicating whether the link is ready on information receiving and transmitting;

when the level signals corresponding to the synchronous port state, the effective port state and the ready port state are all in normal level signals, judging that the link establishment state is normal; otherwise, judging that the link establishment state is abnormal.

In one embodiment, the operational state includes a power state;

the step of detecting the operation state of the communication equipment by the programmable logic device comprises the following steps:

and when the signal output by the comparison circuit is monitored to belong to a power supply abnormity warning indication signal, judging that the power supply state is abnormal, wherein the comparison circuit is used for outputting the power supply abnormity warning indication signal when judging that the power supply voltage is not in a preset range.

In one embodiment, before the step of detecting the operating state of the communication device by the programmable logic device, the method further includes:

before the power supply is normally started, continuously monitoring whether the power supply voltage is greater than a preset value in a first time period, and if so, judging that the state of the power supply is normal, wherein the first time period is far greater than the shortest response time of the programmable logic device.

In one embodiment, the first period of time is greater than or equal to 5 seconds.

In one embodiment, the operational state includes an alarm detection state;

the programmable logic device monitors variables of PLL clock locking, optical synchronization and looped network alarm, and receives the information of the synthesized alarm of the transceiver from the monitoring processor;

when any one variable represents abnormity or the information of the synthesized alarm represents abnormity, judging that the alarm detection state is abnormal;

and when the variables all belong to the normal range and the information of the synthesized alarm indicates normal, judging that the alarm detection state is normal.

In one embodiment, the operating state includes a power detection state;

the programmable logic device counts forward mean power according to the first statistical point number and calculates current forward peak power according to the second statistical point number;

when the forward mean power is greater than a first preset threshold or the current forward peak power is greater than a second preset threshold, judging that the power detection state is abnormal; otherwise, judging the power detection state to be normal.

the monitoring processor reads the running state monitored by the programmable logic device;

and the monitoring processor controls the operation state latched by the register in the programmable logic device according to the operation state.

In one embodiment, before the step of monitoring the operation state of the communication device by the programmable logic device, the method further comprises:

and carrying out power-on configuration on the programmable logic device through a monitoring processor.

A power amplifier protection device, comprising:

the monitoring module is used for monitoring the running state of the communication equipment by the programmable logic device;

and the protection module is used for closing the baseband signal output to the transceiver of the communication equipment and closing the enabling of the pre-pushing stage of the power amplifier in the communication equipment by the programmable logic device when the running state is abnormal.

A computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the power amplifier protection method according to any of the above embodiments.

A power amplifier protection method comprises the following steps:

the programmable logic device monitors whether the power state is kept normal in a second time period, wherein the second time period is far longer than the shortest response time of the programmable logic device;

and when the power state is kept normal in the second time period, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

In one embodiment, the second time period is greater than or equal to 5 seconds.

In one embodiment, the power amplifier protection method further includes:

and when the power state is kept normal in the second time period, the monitoring processor clears the operation state latched by the register in the programmable logic device.

In one embodiment, the power amplifier protection method further includes:

and when the power state is abnormal in a second time period, keeping the operating state latched by a register in the programmable logic device, keeping the enabling of a pre-pushing stage of the power amplifier invalid, and keeping the pushing stage and the final stage grid voltage of the power amplifier closed.

In one embodiment, after the power state remains normal for the second period of time, the method further includes:

the programmable logic device monitors whether the optical port state is normal or not and monitors whether the link establishment state is normal or not; the link establishment state is the state of a communication link between the programmable logic device and a transceiver;

when the optical port state and the link establishment state are normal, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

In one embodiment, the step of monitoring whether the optical port state is normal includes:

acquiring a plurality of light indication information of a light signal in communication equipment;

and when the plurality of indication information of the optical signal belong to a normal range, judging that the state of the optical port is normal.

In one embodiment, the step of monitoring whether the link establishment state is normal comprises:

In one embodiment, the step of monitoring whether the power state remains normal for a second period of time includes:

when the comparison circuit detects that the power supply voltage is in a preset range, whether the power supply voltage is in the preset range in a second time period is continuously monitored, if yes, the power supply state is judged to be normal, and the comparison circuit is used for judging whether the power supply voltage is in the preset range.

In one embodiment, before the step of the programmable logic device monitoring whether the power state is normal for the second time period, the method further comprises:

the monitoring processor closes the pushing stage and the final stage grid voltage of the power amplifier;

and the programmable logic device closes the enabling of the pre-driving stage of the power amplifier.

In one embodiment, after the steps of the monitoring processor turning off the push stage and the final stage gate voltage of the power amplifier and the programmable logic device turning off the enabling of the pre-push stage of the power amplifier, the method further includes:

loading a file containing operation configuration by a monitoring processor;

initializing a register of the programmable logic device according to the operating configuration.

In one embodiment, after the optical port state and the link establishment state are normal, the method further includes:

monitoring alarm information of PLL clock locking, optical synchronization and ring network alarm, and synthetic alarm of a transceiver;

and when the alarm information indicates normal, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

A power amplifier protection device, comprising:

the state monitoring module is used for monitoring whether the power supply state is kept normal in a second time period by the programmable logic device, wherein the second time period is far longer than the shortest response time of the programmable logic device;

and the power amplifier starting module is used for starting the pre-pushing stage enabling by the programmable logic device and starting the pushing stage and the final-stage grid voltage by the monitoring processor when the power supply state is kept normal in a second time period so as to start the power amplifier.

According to the power amplifier protection method, the power amplifier protection device and the computer storage medium, when the operation state is abnormal, the stray phenomenon is likely to occur in the communication equipment, and at the moment, the baseband signal is closed through the programmable logic device in time, and the enabling of the pre-pushing stage of the power amplifier is closed, so that the power input into the power amplifier circuit is stopped, the power amplifier circuit is prevented from being burnt, and the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so the running state of the communication equipment is monitored very fast, and therefore the programmable logic device can respond to the large stray generated in a very short time or can prevent the large stray to be generated, the output baseband signal to the transceiver and the enabling of the pre-pushing stage of the power amplifier are closed in time, and the large stray can be quickly avoided so as to effectively protect the power amplifier circuit in time.

The monitoring processor closes the grid voltage of the pushing stage and the final stage of the power amplifier, so that the situation that the signal isolation of the pre-pushing stage is not enough can be prevented, further, the signal is prevented from being radiated to the pushing stage and the final stage of the power amplifier, the power amplifier is completely closed, and the power amplifier can be more completely protected.

Whether the power supply voltage is larger than a preset value in the second time period or not is continuously monitored, if yes, the power supply state is judged to be normal, the power supply can be monitored to be normal in the duration time, the power supply is ensured to be kept stable, the power supply is prevented from being normal, and the power amplifier is prevented from being damaged due to the fact that the power supply faces to be abnormal after the power amplifier is started.

Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice.

Drawings

The foregoing and/or additional aspects and advantages will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is an implementation environment diagram of a power amplifier protection method provided in an embodiment;

FIG. 2 is a flow chart of a power amplifier protection method according to an embodiment;

FIG. 3 is a flow diagram of a power-up configuration process in one embodiment;

FIG. 4 is a schematic illustration of optical port status monitoring in one embodiment;

FIG. 5 is a diagram illustrating monitoring of a link establishment status according to one embodiment;

FIG. 6 is a diagram illustrating alarm detection status monitoring in one embodiment;

FIG. 7 is a schematic illustration of power detection state monitoring in one embodiment;

fig. 8 is a schematic structural diagram of a power amplifier protection device in an embodiment;

fig. 9 is a flowchart of a power amplifier protection method in yet another embodiment;

fig. 10 is a schematic structural diagram of a power amplifier protection device in yet another embodiment.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As shown in fig. 1, fig. 1 is a diagram of an implementation environment of a power amplifier protection method provided in an embodiment, in which the implementation environment includes a programmable logic device 10, a monitoring processor 20, a transceiver 30, and a power amplifier circuit (power amplifier circuit) 40, where the power amplifier circuit includes a pre-driver stage 41, a driver stage 42, and a final stage 43.

Programmable logic device 10 is a general purpose integrated circuit whose logic functions are determined by the programming of the device by a user. For example, the Programmable Logic device 10 may be a field Programmable gate Array fpga (field Programmable gate Array), other Programmable Logic Array devices pla (Programmable Logic Array), Programmable Array Logic pal (Programmable Array Logic), generic Array Logic gal (generic Array Logic), field Programmable gate Array fpga (field Programmable gate Array), Programmable Logic device epld (erase Programmable Logic device), or Programmable large scale integrated device ispLSI.

The supervisory processor 20 may be an ARM processor, but is not so limited. The transceiver 30 is an ADC/DAC (Analog to Digital Converter/Digital to Analog Converter) transceiver, and the power amplifier 40 is a power amplifier. The programmable logic device 10, the monitoring processor 20 and the transceiver 30 are connected in pairs, a communication link is established between the programmable logic device 10 and the transceiver 30, the transceiver 30 is connected with the power amplifier 40, and the programmable logic device 10 and the monitoring processor 20 can control the power amplifier 40 through the transceiver 30.

In an embodiment, as shown in fig. 2, fig. 2 is a flowchart of a power amplifier protection method in an embodiment, where this embodiment proposes a power amplifier protection method, and the power amplifier protection method may be applied in the above implementation environment, and specifically may include the following steps:

step S210: the programmable logic device monitors the operational status of the communication device.

The operating conditions to be monitored may be a source of characterizing factors that may cause spurs to be generated within the communication device. Communication equipment is influenced by factors such as interface time sequence, plugging and unplugging optical fibers, power-on and power-off, temperature change and the like, and a large stray phenomenon of signals can be generated in a very short time. The stray signals are not detected and exceed the bearing range of the power amplifier circuit, and if the power amplifier circuit is not protected in time, the power amplifier circuit can be burnt.

The monitored operating state may include one or more of an optical port state, a link establishment state, a power state, an alarm detection state, and a power detection state.

Step S220: and when the running state is abnormal, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of a power amplifier in the communication equipment, wherein the baseband signal is the baseband signal output to a transceiver of the communication equipment.

The baseband signal is a baseband signal output to a transceiver of the communication device, and when the baseband signal is turned off, the DAC in the transceiver can be turned off to input a signal to the power amplifier circuit.

According to the power amplifier protection method, when the operation state is abnormal, the stray phenomenon is likely to occur in the communication equipment, and at the moment, the baseband signal is closed through the programmable logic device in time, and the enabling of the pre-pushing stage of the power amplifier is closed, so that the power input into the power amplifier circuit is stopped, the power amplifier circuit is prevented from being burnt, and the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so the running state of the communication equipment is monitored very fast, and therefore the programmable logic device can respond to the large stray generated in a very short time or can prevent the large stray to be generated, the output baseband signal to the transceiver and the enabling of the pre-pushing stage of the power amplifier are closed in time, and the large stray can be quickly avoided so as to effectively protect the power amplifier circuit in time.

In one embodiment, after the step of monitoring the operation state of the communication device by the programmable logic device in step S210, the method further includes:

step S230: and when the running state is abnormal, the monitoring processor closes the pushing stage and the final stage grid voltage of the power amplifier.

When the operation state is abnormal, the monitoring processor closes the grid voltage of the pushing stage and the final stage of the power amplifier, so that the situation that the signal isolation of the pre-pushing stage is not enough can be prevented, the signal is prevented from radiating to the pushing stage and the final stage of the power amplifier, and the power amplifier is completely closed.

According to the power amplifier protection method, when the operation state is abnormal, the pushing stage and the final stage grid voltage of the power amplifier can be further closed through the monitoring processor, and the power amplifier can be protected more thoroughly.

In one embodiment, the operational state includes a light port state;

in step S210, the step of monitoring the operating state of the communication device by the programmable logic device includes:

step S211 a: acquiring a plurality of optical indication information of the optical signal of the communication equipment;

step S212 a: when any one of the light indication information shows abnormality, judging that the state of the light port is abnormal;

step S213 a: and when the plurality of indication information of the optical signal belong to the normal range, judging that the state of the optical port is normal.

The power amplifier protection in the optical port state mainly monitors optical indication information such as optical on-site, optical synchronization, optical loss, superframe indication, error code indication and the like, so that the optical indication information can detect abnormality. If any of the optical indication information indicates an abnormality, the programmable logic device turns off the baseband signal and turns off the enabling of the pre-driver stage of the power amplifier in the communication device, and/or the monitoring processor turns off the driver stage and the final gate voltage of the power amplifier.

The power amplifier protection method can judge the abnormal state of the optical port when any optical indication information indicates the abnormality so as to enable the editable logic device to close the baseband signal and close the enabling of the pre-pushing stage of the power amplifier, and can further enable the monitoring processor to close the pushing stage and the final stage grid voltage of the power amplifier so as to protect the power amplifier against large stray which may occur in the abnormal state of the optical port.

Furthermore, a plurality of indication information of the optical signal all belong to a normal range, and can be kept in the second time period without abnormality, so that the state of the optical port is judged to be normal, and the power amplifier pre-pushing stage enabling can be started. For example, the second time period may be 4.36 s.

In one embodiment, the operational state includes a link setup state of a communication link between the programmable logic device and a transceiver.

Taking the connection between the FPGA and the ADC/DAC transceiver as an example, JESD204B can be established between the FPGA and the ADC/DAC transceiver, and JESD204B is a serial digital link between the FPGA and the ADC/DAC transceiver. The link establishment state of the communication link between the programmable logic device and the transceiver may be the link establishment state of JESD204B between the FPGA and the ADC/DAC transceiver.

step S211 b: monitoring a synchronous port state, an effective port state and a ready port state, wherein the ready port state is used for indicating whether the link is ready on information receiving and transmitting.

The programmable logic device may receive a synchronous port state of (RX), receive an active port state of (RX), feedback a synchronous port state of (FB), feedback an active port state of (FB), transmit a synchronous port state of (TX), and (TX) ready port state. Taking the example that the high level represents the normal level signal, the synchronous port state can be a sync port state, and the synchronous port state is pulled up to represent synchronization; the effective port state is a valid port state, and the effective port state is pulled up to represent that the data is effective; the Ready port state is pulled high to represent Ready for information transceiving.

Step S212 b: when the level signals corresponding to the synchronous port state, the effective port state and the ready port state are all in normal level signals, judging that the link establishment state is normal; otherwise, judging that the link establishment state is abnormal.

And when the level signals corresponding to the synchronous port state, the effective port state and the ready port state are all in normal level signals, the link establishment state is normal. And when any one port state of the synchronous port state, the effective port state and the ready port state is in an abnormal level signal, the link establishment state is abnormal.

For example, a high level represents a normal level signal, i.e., a high port state represents a normal level signal. When the synchronous port state is pulled up, the effective port state is pulled up and the Ready port state is pulled up, the link establishment state is normal. When any one port state of the synchronous port state, the effective port state and the ready port state is in a pull-down state, the link establishment state is abnormal, at the moment, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of a power amplifier in the communication equipment, the baseband signal is the baseband signal output to a transceiver of the communication equipment, and further, a monitoring processor can close the pushing stage and the final stage grid voltage of the power amplifier.

In one embodiment, the operational state includes a power state.

In step S210, the step of detecting the operating state of the communication device by the programmable logic device includes:

step S211 c: and when the signal output by the comparison circuit is monitored to belong to a power supply abnormity warning indication signal, judging that the power supply state is abnormal, wherein the comparison circuit is used for outputting the power supply abnormity warning indication signal when judging that the power supply voltage is not in a preset range.

The comparison circuit may output the power supply abnormality warning indication signal when the power supply voltage is lower than a first preset value. And/or, when the power supply voltage is higher than a second preset value, the comparison circuit can also output the power supply abnormal alarm indication signal.

Taking power failure as an example, on one hand, the leakage voltage of the power amplifier tube gradually decreases, and the reliability is reduced under a lower voltage; on the other hand, the power supply is the voltage conversion inside the power supply or on the digital board, and when the voltage is reduced to a certain voltage, the digital chip works abnormally, so that stray power is generated. Therefore, the input signal of the power amplifier can be cut off before the power amplifier voltage is reduced to a tolerable level and the digital board is abnormal, and therefore the protection effect is achieved. For example, when the supply voltage of the drain electrodes of the push stage and the final stage of the normal power amplifier is 28V, and when the supply voltage is lower than 24V, the power supply is abnormal, and a power supply abnormal alarm indication signal is output to the programmable logic device through the comparison circuit.

In one embodiment, before the step of detecting the operation state of the communication device by the programmable logic device at step S210, the method further includes:

step S200: before the power supply is normally started, continuously monitoring whether the power supply voltage is greater than a preset value in a first time period, and if so, judging that the state of the power supply is normal, wherein the first time period is far greater than the shortest response time of the programmable logic device.

According to the power amplifier protection method, the power supply is monitored to be normal within the duration time, the power supply is ensured to be stable, the power supply is prevented from being normal, the power amplifier is prevented from being damaged due to the fact that the power supply is instantly exposed to power supply abnormity after the power amplifier is started, and the power amplifier is prevented from being damaged. For example, if the first period of time is greater than or equal to 5 seconds and the supply voltage is greater than the predetermined value for 5 seconds, it is determined that the power supply state is normal.

In one embodiment, the operational state includes an alarm detection state.

Step S210, the step of monitoring the operating state of the communication device by the programmable logic device includes:

step S211 d: the programmable logic device monitors variables of PLL clock lock, optical synchronization and ring network alarms, and receives information of a composite alarm of the transceiver from the monitoring processor.

The information of the synthesized alarm comprises a link alarm, a local oscillator alarm and a clock chip alarm, wherein the link alarm can be a JESD alarm.

Step S212 d: and when any one variable represents abnormity or the information of the synthesized alarm represents abnormity, judging that the alarm detection state is abnormal.

After the alarm detection state is judged to be abnormal, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of the power amplifier in the communication equipment, wherein the baseband signal is the baseband signal output to a transceiver of the communication equipment, and further, a monitoring processor can close the pushing stage and the final-stage grid voltage of the power amplifier.

Step S213 d: and when the variables all belong to the normal range and the information of the synthesized alarm indicates normal, judging that the alarm detection state is normal.

According to the self characteristics of the power amplifier, the power amplifier is ensured to work stably and normally for a long time, the input and output conditions are within the reasonable working range of the power amplifier, and if the input signal is not suitable to be in the strength of P-3 and above of the power amplifier for a long time. In the aspect of limiting the input power of the input power amplifier, an Automatic Gain Control (AGC) module limits the input power of an analog-to-digital converter (ADC) module to be overlarge; the PLAGC (maximum power output limiting) module limits downlink average power, power protection limits average and peak power.

In one embodiment, the operating state includes a power detection state.

step S211 e: and the programmable logic device counts the forward mean power according to the first statistical point number and calculates the current forward peak power according to the second statistical point number.

For example, the statistical duration T1 of the forward mean power is N1 × 1/fclk, where N1 is the first statistical point number, N1 is 2048(N1 may also be configured in a parameterization manner, and may take values of 5us, 10us, and 20us), and 1/fclk is a clock cycle. The statistical duration T2 of the forward-average power is N2 (1/fclk), where N2 is the second statistical point number, and N2 is 16(N2 may also be parameterized and may take values of 8, 16, and 32).

Step S212 e: when the forward mean power is greater than a first preset threshold or the current forward peak power is greater than a second preset threshold, judging that the power detection state is abnormal; otherwise, judging the power detection state to be normal.

And (4) average power protection: and comparing the counted forward average power with an average threshold, if the average power is greater than the average threshold, closing the baseband signal, otherwise, opening the baseband signal.

Peak power protection: and comparing the forward peak power of the statistics with a peak threshold, and closing the baseband signal if the peak power is greater than the peak threshold. In addition, the forward peak power at time T1 is greater than the peak threshold, and if the peak power is less than the peak threshold all the time after T period (T > -T2), the baseband signal is turned on, otherwise the baseband signal is turned off.

According to the power amplifier protection method, the average power protection can continuously monitor the total power, the power amplifier is prevented from being protected due to overlarge power, the peak power protection can monitor the power at each moment, and the power amplifier is prevented from being protected due to overlarge instantaneous power.

step S241: and the monitoring processor reads the running state monitored by the programmable logic device.

The monitoring processor reads the running state through the programmable logic device so as to close the pushing stage and the final stage grid voltage of the power amplifier according to the running state.

step S242: and the monitoring processor controls the operation state latched by the register in the programmable logic device according to the operation state.

The monitoring processor may set the operational state of register latches in the programmable logic device.

For example, the programmable logic device exception latch state may be cleared by the monitoring processor after the power state, optical port state, and link setup state are all normal.

In one embodiment, before the step of monitoring the operation state of the communication device by the programmable logic device in step S210, the method further includes:

step S201: and carrying out power-on configuration on the programmable logic device through a monitoring processor.

And in the initialized power-on configuration process, the monitoring processor switches off the pre-driving stage enable and the power amplifier gate voltage of each stage. And waiting for the power-on configuration to be finished, and monitoring the power state of the power amplifier read by the processor. And if the power supply of the power amplifier is detected to be abnormal, the power supply of the power amplifier is continuously detected, and if the power supply of the power amplifier is always abnormal or the power supply is continuously detected for 5s after being recovered to be normal, the power amplifier is turned off due to the power supply fault of the power amplifier. If the power supply of the power amplifier is normal, judging whether the link establishment state and the optical port state are normal, if so, clearing the abnormal latch state of the register, enabling the power amplifier pre-pushing stage to be effective, opening the power amplifier grid voltage, starting the power amplifier, and controlling the operating state of the latch of the register in the programmable logic device by the monitoring processor according to the operating state; and if the link establishment state or the optical port state is abnormal, the power amplifier is in a closed state, and the link establishment state and the optical port protection state are continuously inquired.

The basic principle of turning off and turning on the power amplifier is that the power amplifier is turned on quickly and slowly. The 'fast switch-off' means that under the conditions of power supply abnormality, optical port abnormality and chain establishment abnormality, the programmable logic device immediately switches off the power amplifier pre-pushing stage to enable, and the monitoring processor inquires the running state to switch off the grid voltage of the power amplifier pre-pushing stage. The monitoring processor can also inquire the power supply state, the optical port state and the link establishment state, then continuously traverse other system alarm information, and after confirming that all alarm information meets the normal power amplifier starting condition, the programmable logic device clears the power amplifier enabling state, and the programmable logic device opens the power amplifier enabling and the monitoring processor opens the power amplifier grid voltage. The slow turn-on means that after the power amplifier power supply is abnormal, the power discharge source is continuously detected to be normal within 5s, the programmable logic device can start the pre-push stage enabling, and the monitoring processor can start the power amplifier grid voltage.

In one example application, the programmable logic device is powered on and configured by a monitoring processor. Fig. 3 is a flowchart of a power-on configuration process in an embodiment, and the monitoring processor switches on pre-driver stage enable and power amplifier stage gate voltages. And waiting for the power-on configuration to be finished, and monitoring the power state of the power amplifier read by the processor. And if the power supply of the power amplifier is detected to be abnormal, the power supply of the power amplifier is continuously detected, and if the power supply of the power amplifier is always abnormal or the power supply is abnormal within 5s after the power supply is recovered to be normal, the power amplifier is turned off due to the power supply fault of the power amplifier. If the power supply of the power amplifier is normal, judging whether the link establishment state and the optical port state are normal, if so, clearing the abnormal latch state of the register, enabling the power amplifier pre-pushing stage to be effective, opening the grid voltage of the power amplifier, and starting the power amplifier; and if the link establishment state or the optical port state is abnormal, the power amplifier is in a closed state, and the link establishment state and the optical port protection state are continuously inquired.

The programmable logic device monitors the operational status of the communication device. The operating conditions to be monitored may be a source of characterizing factors that may cause spurs to be generated within the communication device. Communication equipment is influenced by factors such as interface time sequence, plugging and unplugging optical fibers, power-on and power-off, temperature change and the like, and a large stray phenomenon of signals can be generated in a very short time. The stray signals are not detected and exceed the bearing range of the power amplifier circuit, and if the power amplifier circuit is not protected in time, the power amplifier circuit can be burnt. The monitored operating state may include one or more of an optical port state, a link establishment state, a power state, an alarm detection state, and a power detection state.

When monitoring the state of an optical port, acquiring a plurality of optical indication information of the optical signal of the communication equipment; when any one of the light indication information shows abnormality, judging that the state of the light port is abnormal; and when the plurality of indication information of the optical signal belong to the normal range, judging that the state of the optical port is normal. As shown in fig. 4, fig. 4 is a schematic diagram of monitoring an optical interface state in an embodiment, and power amplifier protection in the optical interface state mainly monitors optical indication information such as optical on-site, optical synchronization, optical loss, superframe indication, and error indication, so that the optical indication information can detect abnormality.

Monitoring a synchronous port state, an effective port state and a ready port state when monitoring a link establishment state, wherein the ready port state is used for indicating whether the link is ready on information receiving and transmitting; as shown in fig. 5, fig. 5 is a schematic diagram of monitoring a link establishment state in an embodiment, where when level signals corresponding to the synchronous port state, the valid port state, and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, judging that the link establishment state is abnormal. The programmable logic device may compare the received sync port status (RX _ sync), the received valid port status (RX _ valid), the fed back sync port status (FB _ sync), the fed back valid port status (FB _ valid), the transmitted sync port status (TX _ sync), and the transmitted ready port status (TX _ ready). Taking the example that the high level represents the normal level signal, the synchronous port state can be a sync port state, and the synchronous port state is pulled up to represent synchronization; the effective port states are valid port states respectively, and the effective port state is pulled up to represent that the data is effective; the Ready port state is pulled high to represent Ready information transceiving.

When the power supply state is monitored, when the signal output by the comparison circuit is monitored to belong to a power supply abnormity warning indication signal, the power supply state is judged to be abnormal, wherein the comparison circuit is used for outputting the power supply abnormity warning indication signal when the power supply voltage is judged to be lower than a preset value. Before the power supply is normally started, continuously monitoring whether the power supply voltage is greater than a preset value in a first time period, if so, judging that the power supply is in a normal state, wherein the first time period is far greater than the shortest response time of the programmable logic device. For example, if the first period of time is greater than or equal to 5 seconds and the supply voltage is greater than the predetermined value for 5 seconds, it is determined that the power supply state is normal. The power supply is monitored to be normal in the duration time, the power supply is ensured to be stable, the power supply is prevented from being normal, and the power amplifier is prevented from being damaged due to instantaneous power supply abnormity after the power amplifier is started.

When monitoring the alarm detection state, the programmable logic device monitors variables of PLL clock locking, optical synchronization and ring network alarm, and receives the information of the synthesized alarm of the transceiver from the monitoring processor, wherein the information of the synthesized alarm comprises a link alarm, a local oscillator alarm and a clock chip alarm, and the link alarm can be a JESD alarm; as shown in fig. 6, fig. 6 is a schematic diagram of monitoring an alarm detection state in an embodiment, and when any one of the variables indicates an abnormality or the information of the synthesized alarm indicates an abnormality, it is determined that the alarm detection state is abnormal; and when the variables all belong to the normal range and the information of the synthesized alarm indicates normal, judging that the alarm detection state is normal.

When the power detection state is detected, the programmable logic device counts forward mean power according to the first statistical point number and calculates the current forward peak power according to the second statistical point number; as shown in fig. 7, fig. 7 is a schematic diagram of monitoring a power detection state in an embodiment, where when a forward mean power is greater than a first preset threshold or a current forward peak power is greater than a second preset threshold, it is determined that the power detection state is abnormal; otherwise, judging that the power detection state is normal.

And (4) average power protection: and comparing the counted forward average power with an average threshold, if the average power is greater than the average threshold, closing the baseband signal, otherwise, opening the baseband signal. The statistical duration T1 of the forward average power is N1 × 1/fclk, where N1 is the first statistical point number, N1 is 2048(N1 may also be configured in a parameterization manner, and may take values of 5us, 10us, and 20us), and 1/fclk is a clock cycle.

Peak power protection: and comparing the forward peak power of the statistics with a peak threshold, and closing the baseband signal if the peak power is greater than the peak threshold. The statistical duration T2 of the forward peak power is N2 (1/fclk), where N2 is the second statistical point number, and N2 is 16(N2 may also be parameterized and may take values of 8, 16, and 32). In addition, the forward peak power at time T1 is greater than the peak threshold, and if the peak power is less than the peak threshold all the time after T period (T > -T2), the baseband signal is turned on, otherwise the baseband signal is turned off.

And when the running state is abnormal, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of a power amplifier in the communication equipment, wherein the baseband signal is the baseband signal output to a transceiver of the communication equipment. The baseband signal is a baseband signal output to a transceiver of the communication device, and when the baseband signal is turned off, the DAC in the transceiver can be turned off to input a signal to the power amplifier circuit.

And the monitoring processor reads the running state monitored by the programmable logic device. And when the running state is abnormal, the monitoring processor closes the grid voltage of a pushing stage and a final stage of the power amplifier. When the operation state is abnormal, the monitoring processor closes the grid voltage of the pushing stage and the final stage of the power amplifier, so that the situation that the signal isolation of the pre-pushing stage is not enough can be prevented, the signal is prevented from radiating to the pushing stage and the final stage of the power amplifier, and the power amplifier is completely closed.

According to the power amplifier protection method, when the operation state is abnormal, the stray phenomenon is likely to occur in the communication equipment, and at the moment, the baseband signal is closed through the programmable logic device in time, and the enabling of the pre-pushing stage of the power amplifier is closed, so that the power input into the power amplifier circuit is stopped, the power amplifier circuit is prevented from being burnt, and the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so the running state of the communication equipment is monitored very fast, and therefore the programmable logic device can respond to the large stray generated in a very short time or can prevent the large stray to be generated, the output baseband signal to the transceiver and the enabling of the pre-pushing stage of the power amplifier are closed in time, and the large stray can be quickly avoided so as to effectively protect the power amplifier circuit in time. And when the running state is abnormal, the push stage and the final stage grid voltage of the power amplifier can be further closed through the monitoring processor, so that the power amplifier can be protected more thoroughly.

In an embodiment, as shown in fig. 8, fig. 8 is a schematic structural diagram of a power amplifier protection device in an embodiment, and this embodiment provides a power amplifier protection device, which may be applied in the implementation environment described in fig. 1, and specifically may include a monitoring module 310 and a protection module 320, where:

and a monitoring module 310, configured to monitor an operating state of the communication device by using the programmable logic device.

And the protection module 320 is configured to, when the operating state is abnormal, close the baseband signal output to the transceiver of the communication device and close enabling of a pre-driving stage of a power amplifier in the communication device by the programmable logic device.

When the operation state is abnormal, the power amplifier protection device indicates that the stray phenomenon is likely to occur in the communication equipment, and at the moment, the baseband signal is closed through the programmable logic device in time, and the enabling of the pre-pushing stage of the power amplifier is closed, so that the power input into the power amplifier circuit is stopped, the power amplifier circuit is prevented from being burnt, and the effect of protecting the power amplifier circuit is achieved; and the response time of the programmable logic device is short, so the running state of the communication equipment is monitored very fast, and therefore the programmable logic device can respond to the large stray generated in a very short time or can prevent the large stray to be generated, the output baseband signal to the transceiver and the enabling of the pre-pushing stage of the power amplifier are closed in time, and the large stray can be quickly avoided so as to effectively protect the power amplifier circuit in time.

In one embodiment, the protection module is further configured to, when the operating state is abnormal, monitor the processor to turn off the push stage and the last stage gate voltage of the power amplifier.

When the operation state is abnormal, the monitoring processor closes the grid voltage of the pushing stage and the final stage of the power amplifier, so that the situation that the signal isolation of the pre-pushing stage is insufficient can be prevented, further, the signal is prevented from being radiated to the pushing stage and the final stage of the power amplifier, and the power amplifier is completely closed.

When the operation state is abnormal, the power amplifier protection device can further close the pushing stage and the final stage grid voltage of the power amplifier through the monitoring processor, so that the power amplifier can be protected more thoroughly.

For specific limitations of the power amplifier protection device, reference may be made to the above limitations of the power amplifier protection method, which is not described herein again. All modules in the power amplifier protection device can be completely or partially realized through software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements the steps of the power amplifier protection method according to any of the above embodiments.

In an embodiment, as shown in fig. 9, fig. 9 is a flowchart of a power amplifier protection method in another embodiment, where this embodiment proposes a power amplifier protection method, and the power amplifier protection method may be applied in the above implementation environment, and specifically may include the following steps:

step S410: the programmable logic device monitors whether the power state is kept normal in a second time period, wherein the second time period is far longer than the shortest response time of the programmable logic device.

The second time period is much longer than the response time of the monitoring device, so that the monitoring device can perform multiple monitoring within the second time period. And when the second time period is far longer than the shortest response time of the programmable logic device, the programmable logic device continuously monitors for a longer time in the second time period.

Step S420: and when the power state is kept normal in the second time period, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

If the power state remains normal for the second period of time, it can indicate that the power is stable.

According to the power amplifier protection method, the power supply is monitored to be normal within the duration time, the power supply is ensured to be stable, the situation that the power supply is abnormal instantly after the power supply is started after being normal is avoided, the pre-push stage is started to enable through the programmable logic device after the power supply is stable, the push stage and the final stage grid voltage are started through the monitoring processor, and the power amplifier is protected when the power amplifier is started.

For example, the second time period may be greater than or equal to 5 seconds, the supply voltage remains normal for 5 seconds, the programmable logic device turns on the pre-driver enable, and the monitoring processor turns on the driver and final gate voltages, turning on the power amplifier.

In one embodiment, the power amplifier protection method further includes:

step S431: and when the power state is kept normal in the second time period, the monitoring processor clears the operating state latched by the register in the programmable logic device.

The monitoring processor may set the operational state of register latches in the programmable logic device. When the power supply state is normal continuously in the second time period, the monitoring processor can clear the abnormal latch state in the register so as to conveniently start the power amplifier in the subsequent abnormal operation state.

In one embodiment, the power amplifier protection method further includes:

step S432: and when the power state is abnormal in a second time period, keeping the operating state latched by a register in the programmable logic device, keeping the enabling of a pre-pushing stage of the power amplifier invalid, and keeping the pushing stage and the final stage grid voltage of the power amplifier closed.

When the power state is abnormal, the operating state latched in the register is reserved, the enabling of the pre-pushing stage of the power amplifier is kept invalid, the pushing stage and the grid voltage of the final stage of the power amplifier are kept closed, and the power amplifier is enabled to be in a closed state at the moment so as to protect the power amplifier.

The monitoring processor closes the grid voltage of the pushing stage and the grid voltage of the final stage of the power amplifier, so that the situation that the signal isolation of the pre-pushing stage is not enough can be prevented, the signal radiation to the pushing stage and the final stage of the power amplifier is further avoided, and the power amplifier can be thoroughly turned off at the moment.

step S440: the programmable logic device monitors whether the optical port state is normal or not and monitors whether the link establishment state is normal or not; the link establishment state is a state of a communication link between the programmable logic device and a transceiver.

The link establishment state is the state of the communication link between the programmable logic device and the transceiver. Taking the connection between the FPGA and the ADC/DAC transceiver as an example, JESD204B can be established between the FPGA and the ADC/DAC transceiver, and JESD204B is a serial digital link between the FPGA and the ADC/DAC transceiver. The link establishment state of the communication link between the programmable logic device and the transceiver may be the link establishment state of JESD204B between the FPGA and the ADC/DAC transceiver.

Step S450: when the optical port state and the link establishment state are normal, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

Communication equipment is influenced by factors such as interface time sequence, plugging and unplugging optical fibers, power-on and power-off, temperature change and the like, and a large stray phenomenon of signals can be generated in a very short time. The stray signals are not detected and exceed the bearing range of the power amplifier circuit, and if the power amplifier circuit is not protected in time, the power amplifier circuit can be burnt. In this embodiment, after the power state is normal, the power amplifier needs to be opened only after the optical port state and the link establishment state are normal, and a large stray phenomenon of a signal when the power amplifier is opened is avoided to protect the power amplifier.

When the optical port state or the link establishment state is abnormal, the operation state of the communication equipment is abnormal at this time, and in order to prevent the power amplifier from being burnt, the operation state latched by the register in the programmable logic device can be reserved at this time, the enable of the pre-pushing stage of the power amplifier is kept invalid, the pushing stage and the grid voltage of the last stage of the power amplifier are kept closed, and the power amplifier is kept closed, so that the power amplifier is protected.

Specifically, the step of monitoring whether the optical port state is normal in step S440 includes:

step S441: acquiring a plurality of light indication information of a light signal in communication equipment;

step S442: when any one of the light indication information shows abnormality, judging that the state of the light port is abnormal;

step S443: and when the plurality of indication information of the optical signal belong to a normal range, judging that the state of the optical port is normal.

Specifically, the step of monitoring whether the link establishment state is normal in step S440 includes:

step S444: monitoring a synchronous port state, an effective port state and a ready port state, wherein the ready port state is used for indicating whether the link is ready on information receiving and transmitting.

Step S445: when the level signals corresponding to the synchronous port state, the effective port state and the ready port state are all in normal level signals, judging that the link establishment state is normal; otherwise, judging that the link establishment state is abnormal.

For example, a high level represents a normal level signal, i.e., a high port state represents a normal level signal. When the synchronous port state is pulled up, the effective port state is pulled up and the ready port state is pulled up, the link establishment state is normal. And when any one port state of the synchronous port state, the effective port state and the ready port state is pulled down, the link establishment state is abnormal.

In one embodiment, the step of monitoring whether the power state remains normal for the second period of time in step S410 includes:

For example, when the supply voltage is over lower than the second preset value in the second time period, the power state is determined to be abnormal. And/or judging that the power supply state is abnormal when the power supply voltage is higher than a second preset value in a second time period.

In one embodiment, before the step of the programmable logic device monitoring whether the power state remains normal for the second time period in step S410, the method further includes:

step S450: the monitoring processor closes the grid voltage of the pushing stage and the final stage of the power amplifier; and the programmable logic device closes the enabling of the pre-driving stage of the power amplifier.

The power amplifier is burnt out when the signal is abnormal and the abnormality is not recoverable in the power-on process. Before the power amplifier is started when power is on, the pre-push stage enables and grid voltages of all stages of the power amplifier are closed so as to protect the power amplifier.

In one embodiment, after the step of the monitoring processor turning off the push stage and the final stage gate voltage of the power amplifier and the step of the programmable logic device turning off the enabling of the pre-push stage of the power amplifier in step S450, the method further includes:

step S451: loading a file containing operation configuration by a monitoring processor;

step S452: initializing a register of the programmable logic device according to the operating configuration.

After pre-pushing stage enabling and power amplifier grid voltage of each stage are turned off, a monitoring processor loads a file containing operation configuration, and initializes a register of the programmable logic device according to the operation configuration to carry out an initialized power-on configuration process.

And waiting for the power-on configuration to be finished, and reading the power amplifier power supply state by the monitoring processor. And if the power amplifier power supply is detected to be abnormal, the power amplifier power supply is continuously detected, and if the power amplifier power supply is always abnormal or the power supply is continuously detected to be abnormal for 5s after being recovered to be normal, the power amplifier power supply is failed to close the power amplifier. If the power amplifier power supply is normal, judging whether the link establishment state and the optical port state are normal, if the normal register is abnormal, the latch state is cleared, the power amplifier pre-pushing stage is enabled to be effective, and the power amplifier grid voltage is opened so as to start the power amplifier; and if the link establishment state and the optical interface state are abnormal, the power amplifier is in a closed state, and the link establishment state and the optical interface state are continuously inquired.

The power-on configuration mainly comprises file loading, clock configuration, link (JESD) configuration and related test operation. And after the loading of the monitoring processor is finished, a clock chip is configured, the clock chip provides a clock for the programmable logic device, and the monitoring processor judges whether the programmable logic device is loaded successfully or not according to the pin level of the programmable logic device. And resetting the programmable logic device after the loading is successful, and initializing a relevant register of the programmable logic device to ensure the normality of the signal.

step S461: and monitoring alarm information of PLL clock locking, optical synchronization and looped network alarm and synthetic alarm of the transceiver.

Step S462: and when the alarm information indicates normal, the programmable logic device opens the pre-push stage to enable, and the monitoring processor opens the push stage and the last stage grid voltage to start the power amplifier.

When the alarm information shows normal, the alarm detection state is normal, at this time, the programmable logic device can open the pre-push stage to enable, and the monitoring processor can open the push stage and the last stage grid voltage to start the power amplifier.

When any one of the synthesized alarm information shows an abnormality, the alarm detection state is judged to be abnormal, which shows that the operation state of the communication equipment is abnormal at the moment, and in order to prevent the power amplifier from being burnt, the operation state latched by the register in the programmable logic device can be reserved at the moment, the enable of the pre-pushing stage of the power amplifier is kept invalid, the pushing stage and the final stage grid voltage of the power amplifier are kept closed, and the power amplifier is kept closed, so that the power amplifier is protected.

In an application example, this example will protect the power amplifier during the power-on configuration process. As shown in fig. 3, fig. 3 is a flowchart of a power amplifier protection method in a power-on configuration process in an embodiment. Firstly, an initial power-on configuration process is carried out, and the pre-driving stage enabling and the power amplifier gate voltage of each stage are closed. In the power-on configuration, a monitoring processor loads a file containing operation configuration; initializing registers of the programmable logic device according to the operating configuration, and establishing a link between the programmable logic device and the transceiver. And judging whether the link between the programmable logic device and the transceiver is successfully established according to the synchronous port state, the effective port state and the ready port state, and releasing a reference signal for providing a clock for the link after the link is successfully established.

And waiting for the end of power-on configuration, and monitoring the power state by the programmable logic device. If the power supply of the power amplifier is monitored to be abnormal, the power supply of the power amplifier is continuously monitored, if the power supply of the power amplifier is always abnormal or the power supply is abnormal within 5s after being recovered to be normal, the power supply of the power amplifier fails, the running state latched by a register in the programmable logic device is reserved, the enabling of a pre-pushing stage of the power amplifier is kept invalid, and the pushing stage and the final grid voltage of the power amplifier are kept closed so as to close the power amplifier.

If the power state is kept normal in a second time period which is far longer than the shortest response time of the programmable logic device, namely the power of the power amplifier is normal, whether the link establishment state and the optical port state are normal or not is continuously judged, if so, the abnormal latch state of the register is cleared, the enabling of the power amplifier pre-pushing stage is effective, the grid voltage of the power amplifier is opened, and the power amplifier is started; and if the link establishment state or the optical port state is abnormal, the power amplifier is in a closed state, and the link establishment state and the optical port protection state are continuously inquired.

Wherein, the monitoring power supply state can be detected by the comparison circuit. When the comparison circuit detects that the power supply voltage is in a preset range, whether the power supply voltage is in the preset range within 5s is continuously monitored, if yes, the power supply state is judged to be normal, and the comparison circuit is used for judging whether the power supply voltage is in the preset range.

After the power amplifier is started, the programmable logic device can monitor the running state of the communication equipment. The operating conditions to be monitored may be a source of characterizing factors that may cause spurs to be generated within the communication device. Communication equipment is influenced by factors such as interface time sequence, plugging and unplugging optical fibers, power-on and power-off, temperature change and the like, and a large stray phenomenon of signals can be generated in a very short time. The stray signals are not detected and exceed the bearing range of the power amplifier circuit, and if the power amplifier circuit is not protected in time, the power amplifier circuit can be burnt. The monitored operating state may include one or more of an optical port state, a link establishment state, a power state, an alarm detection state, and a power detection state.

When monitoring the state of an optical port, acquiring a plurality of optical indication information of the optical signal of the communication equipment; when any one of the light indication information shows abnormality, judging that the state of the light port is abnormal; and when the plurality of indication information of the optical signal belong to the normal range, judging that the state of the optical port is normal. As shown in fig. 4, fig. 4 is a schematic diagram of monitoring an optical interface state in an embodiment, and power amplifier protection in the optical interface state mainly monitors optical indication information such as optical on-site, optical synchronization, optical loss, superframe indication, and error indication, so that the optical indication information can detect whether an optical interface is abnormal.

Monitoring a synchronous port state, an effective port state and a ready port state when monitoring a link establishment state, wherein the ready port state is used for indicating whether the link is ready on information receiving and transmitting; as shown in fig. 5, fig. 5 is a schematic diagram of monitoring a link establishment state in an embodiment, where when level signals corresponding to the synchronous port state, the valid port state, and the ready port state are all normal level signals, it is determined that the link establishment state is normal; otherwise, judging that the link establishment state is abnormal. The programmable logic device may compare the received sync port status (RX _ sync), the received valid port status (RX _ valid), the fed back sync port status (FB _ sync), the fed back valid port status (FB _ valid), the transmitted sync port status (TX _ sync), and the transmitted ready port status (TX _ ready). Taking the example that the high level represents the normal level signal, the synchronous port state can be a sync port state, and the synchronous port state is pulled up to represent synchronization; the effective port states are valid port states respectively, and the effective port state is pulled up to represent that the data is effective; the Ready port state is pulled high to represent Ready for information transceiving.

The programmable logic device monitors variables of PLL clock locking, optical synchronization and looped network alarm, and receives information of synthetic alarm of the transceiver from the monitoring processor, wherein the information of the synthetic alarm comprises link alarm, local oscillator alarm and clock chip alarm, and the link alarm can be JESD alarm; as shown in fig. 6, fig. 6 is a schematic diagram of monitoring an alarm detection state in an embodiment, and when any one of the variables indicates an abnormality or the information of the synthesized alarm indicates an abnormality, it is determined that the alarm detection state is abnormal; and when the variables all belong to the normal range and the information of the synthesized alarm indicates normal, judging that the alarm detection state is normal.

After the power amplifier is started, if the power supply state, the link establishment state, the optical port state or the alarm detection state are abnormal, the operating state latched by a register in the programmable logic device is reserved, the enabling invalidity of a pre-pushing stage of the power amplifier is kept, and the pushing stage and the final stage grid voltage of the power amplifier are kept closed; if the states are normal, the pre-push stage is turned on to enable through a programmable logic device, and the monitoring processor turns on the push stage and the last stage grid voltage to start the power amplifier.

In an embodiment, as shown in fig. 10, fig. 10 is a schematic structural diagram of a power amplifier protection device in yet another embodiment, and this embodiment provides a power amplifier protection device, which may include a state monitoring module 510 and a power amplifier starting module 520, where:

and the state monitoring module 510 is configured to monitor, by the programmable logic device, whether the power state remains normal in a second time period, where the second time period is far longer than the shortest response time of the programmable logic device.

And a power amplifier starting module 520, configured to, when the power state remains normal in the second time period, turn on the pre-driver stage enable by the programmable logic device, and turn on the driver stage and the last stage gate voltage by the monitoring processor, so as to start the power amplifier.

The power amplifier protection device monitors that the power supply is normal within the duration, ensures that the power supply is stable, avoids the situation that the power supply is abnormal instantly after the power amplifier is started after the power supply is normal, opens the pre-push stage enable through the programmable logic device after the power supply is stable, and opens the push stage and the final stage grid voltage through the monitoring processor, thereby protecting the power amplifier when the power amplifier is started.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A power amplifier protection method is characterized by comprising the following steps:

before the power supply is normally started, when the continuously monitored power supply voltage is larger than a preset value in a first time period, judging that the state of the power supply is normal; wherein the first time period is much greater than the shortest response time of the programmable logic device;

the programmable logic device monitors the running state of the communication equipment; the operating state comprises an optical port state;

when the operation state is abnormal, the programmable logic device closes a baseband signal and closes the enabling of a pre-pushing stage of a power amplifier in the communication equipment, wherein the baseband signal is the baseband signal output to a transceiver of the communication equipment;

the monitoring processor reads the running state monitored by the programmable logic device, and closes the grid voltage of a pushing stage and a final stage of the power amplifier when the running state is abnormal;

wherein, the judgment of the optical port state comprises the following steps: when any one of the optical indication information of the optical signals of the communication equipment shows abnormality, judging that the state of an optical port is abnormal; and when the plurality of optical indication information of the optical signal of the communication equipment belong to a normal range and are kept abnormal in the second time period, judging that the optical port state is normal, and starting the enabling of the pre-pushing stage of the power amplifier.

2. The power amplifier protection method according to claim 1, wherein the operation state comprises a link establishment state of a communication link between the programmable logic device and a transceiver;

3. The power amplifier protection method of claim 1, wherein the operating state comprises a power state;

4. The power amplifier protection method of claim 1, wherein the first time period is greater than or equal to 5 seconds.

5. The power amplifier protection method according to claim 1, wherein the operation state comprises an alarm detection state;

6. The power amplifier protection method according to claim 1, wherein the operating state comprises a power detection state;

when the forward mean power is greater than a first preset threshold or the current forward peak power is greater than a second preset threshold, judging that the power detection state is abnormal; otherwise, judging that the power detection state is normal.

7. The power amplifier protection method according to claim 1, further comprising, after the step of monitoring the operating state of the communication device by the programmable logic device:

8. The power amplifier protection method according to claim 1, before the step of monitoring the operating state of the communication device by the programmable logic device, further comprising:

9. A power amplifier protection device, comprising:

the monitoring module is used for judging that the state of the power supply is normal when the power supply voltage is continuously monitored to be larger than a preset value in a first time period before the power supply is normally started; the programmable logic device monitors the running state of the communication equipment; wherein the first time period is much greater than the shortest response time of the programmable logic device; the operating state comprises an optical port state;

the protection module is used for closing a baseband signal output to a transceiver of the communication equipment and closing the enabling of a pre-pushing stage of a power amplifier in the communication equipment by the programmable logic device when the running state is abnormal; the monitoring processor reads the running state monitored by the programmable logic device, and closes the grid voltage of a pushing stage and a final stage of the power amplifier when the running state is abnormal; wherein, the judgment of the optical port state comprises the following steps: when any one of the optical indication information of the optical signals of the communication equipment shows abnormality, judging that the state of an optical port is abnormal; and when the plurality of optical indication information of the optical signal of the communication equipment belong to a normal range and are kept abnormal in the second time period, judging that the optical port state is normal, and starting the enabling of the pre-pushing stage of the power amplifier.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the power amplifier protection method according to any one of claims 1 to 8.