CN111430379B - Display panel and manufacturing method thereof - Google Patents
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- CN111430379B CN111430379B CN202010289130.7A CN202010289130A CN111430379B CN 111430379 B CN111430379 B CN 111430379B CN 202010289130 A CN202010289130 A CN 202010289130A CN 111430379 B CN111430379 B CN 111430379B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The invention provides a display panel and a manufacturing method thereof, wherein the method comprises the following steps: patterning the photoresist layer by using a fine metal mask plate to form a plurality of flat parts and a plurality of convex parts, wherein the position of the orthographic projection of the flat part on the substrate is not overlapped with the position of the orthographic projection of the grid electrode on the substrate and the position of the orthographic projection of the first metal part on the substrate; etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion; removing the bulge part, manufacturing a second metal layer on the rest metal oxide semiconductor layer, and patterning the second metal layer to form a source electrode and a drain electrode; wherein the source and drain overlie the first subsection; forming a passivation layer on the second metal layer; and manufacturing a pixel electrode on the passivation layer. The display panel and the manufacturing method thereof can improve the aperture opening ratio.
Description
[ technical field ] A
The invention relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
[ background of the invention ]
The metal oxide semiconductor layer has high electron mobility and a small size compared to amorphous silicon (a-si).
The common metal oxide thin film transistor mainly has three structures of a Coplanar Layer (Coplanar), an etching barrier Layer (Island Stop/Etch Stop Layer, IS/ESL) and a Back Channel etching (Back Channel Etch, BCE), but IS limited by the process, so that the metal oxide semiconductor Layer below the existing source electrode and drain electrode protrudes outside the source electrode and drain electrode, and the part IS easily influenced by backlight to generate electrical drift, so that the display panel generates phenomena such as vertical crosstalk and the like, and the display quality IS reduced.
At present, in order to prevent the exposed metal oxide semiconductor layer from being affected by the backlight, the size of the gate electrode is increased to shield the metal oxide semiconductor layer, but the aperture ratio is reduced.
Therefore, it is desirable to provide a display panel and a method for manufacturing the same to solve the problems of the prior art.
[ summary of the invention ]
The invention aims to provide a display panel and a manufacturing method thereof, which can improve the aperture opening ratio.
In order to solve the above technical problem, the present invention provides a method for manufacturing a display panel, including:
manufacturing a first metal layer on a substrate, and patterning the first metal layer to form a grid and a first metal part;
sequentially manufacturing a gate insulating layer, a metal oxide semiconductor layer and a light resistance layer on the first metal layer;
patterning the photoresist layer by using a fine metal mask plate to form a plurality of flat parts and a plurality of convex parts, wherein the orthographic projection position of the flat part on the substrate is not overlapped with the orthographic projection position of the grid electrode on the substrate and the orthographic projection position of the first metal part on the substrate;
etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion;
removing the bulge part, manufacturing a second metal layer on the rest metal oxide semiconductor layer, and patterning the second metal layer to form a source electrode and a drain electrode; wherein the source and drain overlie the first subsection;
forming a passivation layer on the second metal layer;
and manufacturing a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode.
The present invention also provides a display panel including:
a base substrate;
a first metal layer including a gate and a first metal portion;
the gate insulating layer is arranged on the first metal layer;
a metal oxide semiconductor layer disposed on the gate insulating layer, the metal oxide semiconductor layer including a first sub-portion; the position of the first sub-part corresponds to the position of the grid;
the second metal layer is arranged on the metal oxide semiconductor layer and comprises a source electrode and a drain electrode; the source electrode covers one end part of the first sub-part; the drain electrode covers the other end part of the first sub-part;
the passivation layer is arranged on the second metal layer;
and the pixel electrode is arranged on the passivation layer.
The display panel and the manufacturing method thereof comprise the steps of patterning a light resistance layer by using a fine metal mask plate to form a plurality of flat parts and a plurality of convex parts, wherein the orthographic projection position of the flat part on a substrate is not overlapped with the orthographic projection position of a grid electrode on the substrate and the orthographic projection position of a first metal part on the substrate; etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion; removing the bulge part, manufacturing a second metal layer on the rest metal oxide semiconductor layer, and patterning the second metal layer to form a source electrode and a drain electrode; wherein the source and drain overlie the first subsection; the metal oxide semiconductor layer positioned at the outer sides of the source electrode and the drain electrode is etched, so that the metal oxide semiconductor layer is prevented from being exposed outside, the display quality is prevented from being influenced, and in addition, the opening ratio can be improved because the size of the grid electrode does not need to be increased.
[ description of the drawings ]
FIG. 1 is a schematic structural diagram of a conventional display panel;
FIG. 2 is a schematic view of a conventional process for manufacturing a display panel;
FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic view of a process flow for manufacturing a display panel according to the present invention.
[ detailed description ] embodiments
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. In the present invention, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc. refer to directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.
As shown in fig. 1, the conventional display panel includes a substrate 11, and a first metal layer 12, a gate insulating layer 13, a metal oxide semiconductor layer 14, a second metal layer 15, a passivation layer 16, a color film layer 17, a protective layer 18 and a pixel electrode 19 sequentially disposed on the substrate 11. The metal oxide semiconductor layer 14 shown in the dashed line frame of fig. 1 is not covered by the second metal layer and the first metal layer, i.e., is exposed.
With reference to fig. 2 and fig. 1, a conventional method for manufacturing a display panel includes:
s101, a first metal layer 12 is formed on the base substrate 11, and the first metal layer 12 is patterned to form a gate electrode 121 and a first metal portion 122.
And S102, manufacturing a gate insulating layer 13 on the first metal layer 12.
S103, forming the metal oxide semiconductor layer 14 and the photoresist layer 20 on the gate insulating layer 13 in sequence.
S104, the photoresist layer 20 is patterned to form an opening 211.
And S105, etching away the metal oxide semiconductor layer 14 corresponding to the opening 211.
And S106, etching the gate insulating layer 13 corresponding to the etched metal oxide semiconductor layer to form the connecting hole 101.
S107, stripping the remaining photoresist layer, and then performing a second patterning process on the metal oxide semiconductor layer 14 to form the first sub-portion 141, the second sub-portion 142, and the third sub-portion 143;
s108, forming a second metal layer 15 on the connection hole 101 and the metal oxide semiconductor layer 14, and patterning the second metal layer 15 to form a source 151, a drain 152, and a second metal portion 153;
wherein the second metal portion 153 is connected to the first metal portion through the connection hole 101.
S109, forming a passivation layer 16 on the second metal layer 15;
s110, forming a color film layer 17 on the passivation layer 16;
s111, forming a protective layer 18 on the color film layer 17;
and S112, forming a pixel electrode 19 on the protective layer 18, wherein the pixel electrode 19 is connected with the drain electrode 152.
Referring to fig. 3 to 4, fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the invention.
In an embodiment, as shown in fig. 3 and 4, the display panel of the present invention includes a substrate 21, and a first metal layer 22, a gate insulating layer 23, a metal oxide semiconductor layer 24, a second metal layer 25, a passivation layer 26, and a pixel electrode 29 sequentially disposed on the substrate 21, and further includes a color film layer 27 and/or a protective layer 28.
The base substrate 21 may be a glass substrate or a flexible substrate.
The first metal layer 22 includes a gate electrode 221 and a first metal portion 222. The material of the first metal layer 22 includes Mo, Al, Ti, Cu, and the like. The first metal part 222 may be used to form a connection line, and may also be used to form an electrode. Of course, the function of the first metal part 222 is not limited thereto.
The material of the gate insulating layer 23 may be SiNx, SiOx, or the like, and the gate insulating layer 23 may be a single layer film or a double layer film. In one embodiment, a connection hole may be formed on the gate insulating layer 23.
The metal oxide semiconductor layer 24 includes a first sub-portion 241. In one embodiment, the metal oxide semiconductor layer 24 may further include a second sub-portion 242 and a third sub-portion 243; the first sub-portion 241 corresponds to the gate 221, and the second sub-portion 242 corresponds to one end of the first metal portion 222; the third sub-portion 243 corresponds to the other end of the first metal portion 222. Wherein the material of the metal oxide semiconductor layer 24 includes, but is not limited to, IGZO and ITZO.
The second metal layer 25 includes a source 251 and a drain 252, and in addition, in order to simplify the process and improve the production efficiency, the second metal layer 25 may further include a second metal portion 253; the source 251 and the drain 252 are located on the first sub-portion 241, and the second metal portion 253 is located on the second sub-portion 242 and the third sub-portion 243. The material of the second metal layer 25 includes Mo, Al, Ti, Cu, and the like, and the second metal layer 25 may be a single-layer film or a multi-layer film. Wherein the source 251 covers one end of the first sub-portion 241; the drain electrode 252 covers the other end portion of the first sub-portion 241. In one embodiment, in order to further improve the display quality, the second metal portion 253 covers the second sub-portion 242 and the third sub-portion 243. In one embodiment, in order to reduce the impedance, the second metal portion 253 may be connected to the first metal portion 222 through a connection hole.
The material of the passivation layer 26 may include SiO 2 At least one of SiNx and SiON may be, for example, a composite layer of any two of the above materials.
The color film layer 27 includes a plurality of color film resistors 271 to 273 arranged at intervals, for example, a red color film, a green color film, and a blue color film. The positions of the color resists of the color films correspond to the positions of the second metal portions 242.
The material of the protective layer 28 may include SiO 2 At least one of SiNx and SiON may be, for example, a composite layer of any two of the above materials.
The material of the pixel electrode 29 may be ito, and the pixel electrode 29 is connected to the drain electrode 252.
With reference to fig. 4 and fig. 3, in an embodiment, a method for manufacturing a display panel of the present invention includes:
s201, a first metal layer 22 is formed on the base substrate 21, and the first metal layer 22 is patterned to form a gate 221 and a first metal portion 222.
For example, a photoresist layer is coated on the first metal layer, and then the photoresist layer is patterned, including exposing, developing, and then etching the first metal layer 22 using the patterned photoresist layer to form the gate electrode 221 and the first metal portion 222.
S202, sequentially manufacturing a gate insulating layer, a metal oxide semiconductor layer and a light resistance layer on the first metal layer;
for example, a gate insulating layer 23, a metal oxide semiconductor layer 24, and a photoresist layer 30 are sequentially formed on the first metal layer 22.
S203, performing a patterning process on the photoresist layer 30 by using a fine metal mask 40 to form a plurality of flat portions 302 and a plurality of protruding portions 303, wherein the first openings 301 correspond to the first metal portions 222; the position of the orthographic projection of the flat part 302 on the substrate 21, the position of the orthographic projection of the grid electrode on the substrate 21 and the position of the orthographic projection of the first metal part 222 on the substrate 21 are not overlapped;
s204, etching away the metal oxide semiconductor layer corresponding to the flat portion 302 to form a first sub-portion 241; that is, in this embodiment, the metal oxide semiconductor layer does not include the second sub-portion and the third sub-portion.
In an embodiment, the step of etching away the metal oxide semiconductor layer corresponding to the flat portion 302 includes:
s2041, performing ashing treatment on the flat portion 302 to remove the flat portion 302 and form a second opening (not shown);
and S2042, etching away the metal oxide semiconductor layer 24 corresponding to the second opening.
S205, removing the protruding portion 303, forming a second metal layer 25 on the remaining metal oxide semiconductor layer 24, and patterning the second metal layer 25 to form a source electrode 251 and a drain electrode 252; wherein the source 251 and drain 252 overlie the first subsection 241;
s206, forming a passivation layer 26 on the second metal layer 25;
and S207, manufacturing a pixel electrode 29 on the protective layer 28, wherein the pixel electrode 29 is connected with the drain electrode 252.
In another embodiment, a method for manufacturing a display panel of the present invention includes:
s301, a first metal layer 22 is formed on the base substrate 21, and the first metal layer 22 is patterned to form the gate electrode 221 and the first metal portion 222.
With reference to fig. 3 and 4, for example, a photoresist layer is coated on the first metal layer, and then the photoresist layer is patterned, including exposing, developing, and then etching the first metal layer 22 with the patterned photoresist layer to form the gate electrode 221 and the first metal portion 222.
S302, sequentially manufacturing a gate insulating layer, a metal oxide semiconductor layer and a light resistance layer on the first metal layer;
for example, a gate insulating layer 23, a metal oxide semiconductor layer 24, and a photoresist layer 30 are sequentially formed on the first metal layer 22.
S303, performing a patterning process on the photoresist layer 30 by using a fine metal mask 40 to form a first opening 301, a plurality of flat portions 302, and a plurality of protrusions 303, wherein the first opening 301 corresponds to the first metal portion; the position of the orthographic projection of the flat portion 302 on the substrate 21, the position of the orthographic projection of the gate on the substrate 21 and the position of the orthographic projection of the first metal portion 222 on the substrate 21 do not overlap.
S304, etching off the metal oxide semiconductor layer corresponding to the first opening, and etching the gate insulating layer below the first opening to form a connecting hole;
for example, the metal oxide semiconductor layer 24 corresponding to the first opening may be etched, and then the gate insulating layer 23 below may be etched again to form the connection hole 202.
S305, etching away the metal oxide semiconductor layer 24 corresponding to the flat portion 302 to form a first sub-portion 241, a second sub-portion 242 and a third sub-portion 243;
in an embodiment, the step of etching away the metal oxide semiconductor layer corresponding to the flat portion 302 includes:
s3051, performing ashing treatment on the flat portion 302 to remove the flat portion 302 and form a second opening (not shown);
and S3052, etching away the metal oxide semiconductor layer 24 corresponding to the second opening.
S306, removing the protruding portion 303, forming a second metal layer 25 on the remaining metal oxide semiconductor layer 24, and patterning the second metal layer 25 to form a source 251, a drain 252, and a second metal portion 253; the source 251 and the drain 252 cover the first sub-portion 241, and the second metal portion 253 covers the second sub-portion 242 and the third sub-portion 243.
S307, forming a passivation layer 26 on the second metal layer 25;
s308, fabricating a color film 27 on the passivation layer 26, wherein the position of the color film 27 corresponds to the position of the second metal portion 222;
and S309, manufacturing a protective layer 28 on the color film layer 27. Wherein vias are made through the passivation layer 26 and the protective layer 28.
And S310, manufacturing a pixel electrode 29 on the protective layer 28.
Wherein the pixel electrode 29 is connected to the drain electrode 252 through a via hole.
Of course, in other embodiments, the above-mentioned manufacturing method may not include S308 and/or S309.
It will be appreciated that the particular manner of etching described above is not limiting.
The metal oxide semiconductor layer positioned at the outer sides of the source electrode and the drain electrode is etched, so that the metal oxide semiconductor layer is prevented from being exposed outside, the display quality is prevented from being influenced, and in addition, the opening ratio can be improved because the size of the grid electrode does not need to be increased.
The display panel and the manufacturing method thereof comprise the steps of patterning a light resistance layer by using a fine metal mask plate to form a plurality of flat parts and a plurality of convex parts, wherein the orthographic projection position of the flat part on a substrate is not overlapped with the orthographic projection position of a grid electrode on the substrate and the orthographic projection position of a first metal part on the substrate; etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion; removing the bulge part, manufacturing a second metal layer on the rest metal oxide semiconductor layer, and patterning the second metal layer to form a source electrode and a drain electrode; wherein the source and drain overlie the first subsection; the metal oxide semiconductor layer positioned at the outer sides of the source electrode and the drain electrode is etched, so that the metal oxide semiconductor layer is prevented from being exposed outside, the display quality is prevented from being influenced, and in addition, the opening ratio can be improved because the size of the grid electrode does not need to be increased.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (8)
1. A method for manufacturing a display panel is characterized by comprising the following steps:
manufacturing a first metal layer on a substrate, and patterning the first metal layer to form a grid and a first metal part;
sequentially manufacturing a gate insulating layer, a metal oxide semiconductor layer and a light resistance layer on the first metal layer;
patterning the photoresist layer by using a fine metal mask plate to form a plurality of flat parts and a plurality of convex parts, wherein the orthographic projection positions of the flat parts on the substrate are not overlapped with the orthographic projection positions of the grid electrodes on the substrate and the orthographic projection positions of the first metal parts on the substrate;
etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion;
removing the bulge part, manufacturing a second metal layer on the rest metal oxide semiconductor layer, and patterning the second metal layer to form a source electrode and a drain electrode; wherein the source and drain overlie the first subsection;
forming a passivation layer on the second metal layer;
manufacturing a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode;
wherein the etching away the metal oxide semiconductor layer corresponding to the flat portion to form the first sub-portion includes:
etching away the metal oxide semiconductor layer corresponding to the flat portion to form a first sub-portion, a second sub-portion and a third sub-portion;
the step of patterning the second metal layer to form a source electrode and a drain electrode comprises the following steps:
and patterning the second metal layer to form a source, a drain and a second metal part, wherein the second metal part covers the second sub-part and the third sub-part.
2. The method for manufacturing a display panel according to claim 1,
the step of etching away the metal oxide semiconductor layer corresponding to the flat portion includes:
performing ashing treatment on the flat part to remove the flat part and form a second opening;
and etching away the metal oxide semiconductor layer corresponding to the second opening.
3. The method according to claim 1, wherein the step of patterning the photoresist layer using a fine metal mask to form a plurality of flat portions and a plurality of protrusions comprises:
and patterning the photoresist layer by using a fine metal mask plate to form a plurality of flat parts, a plurality of convex parts and a first opening, wherein the first opening corresponds to the first metal part.
4. The method for manufacturing a display panel according to claim 3,
before the step of etching away the metal oxide semiconductor layer corresponding to the flat portion to form the first sub-portion, the second sub-portion, and the third sub-portion, the method further includes:
etching off the metal oxide semiconductor layer corresponding to the first opening, and etching the gate insulating layer positioned below the first opening to form a connecting hole;
the step of manufacturing a second metal layer on the rest of the metal oxide semiconductor layer comprises the following steps:
and manufacturing a second metal layer on the rest metal oxide semiconductor layer and in the connecting hole.
5. The method of manufacturing a display panel according to claim 1,
after the step of forming the passivation layer on the second metal layer and before the step of fabricating the pixel electrode on the passivation layer, the method further includes:
manufacturing a color film layer on the passivation layer, wherein the position of the color film layer corresponds to the position of the second metal part;
the step of manufacturing the pixel electrode on the passivation layer comprises the following steps:
and manufacturing a pixel electrode on the color film layer.
6. The method for manufacturing a display panel according to claim 5,
the step of manufacturing the pixel electrode on the color film layer comprises the following steps:
manufacturing a protective layer on the color film layer;
and manufacturing a pixel electrode on the protective layer.
7. A display panel, comprising:
a substrate base plate;
a first metal layer including a gate and a first metal portion;
the gate insulating layer is arranged on the first metal layer;
a metal oxide semiconductor layer disposed on the gate insulating layer, the metal oxide semiconductor layer including a first sub-portion; the position of the first sub-part corresponds to the position of the grid;
the second metal layer is arranged on the metal oxide semiconductor layer and comprises a source electrode and a drain electrode; the source electrode covers one end part of the first sub-part; the drain electrode covers the other end part of the first sub-part;
the passivation layer is arranged on the second metal layer;
a pixel electrode disposed on the passivation layer;
wherein the metal oxide semiconductor layer further comprises a second sub-portion and a third sub-portion; the second metal layer comprises a second metal part, and the second sub-part corresponds to the position of one end part of the first metal part; the third sub-portion corresponds to the other end of the first metal portion; the second metal part covers the second sub-part and the third sub-part.
8. The display panel according to claim 7,
the gate insulating layer is provided with a connecting hole, and the second metal part is connected with the first metal part through the connecting hole.
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| KR101294232B1 (en) * | 2007-06-08 | 2013-08-07 | 엘지디스플레이 주식회사 | Fringe field switching mode liquid crystal display device and the method for fabricating the same |
| TWI373141B (en) * | 2007-12-28 | 2012-09-21 | Au Optronics Corp | Liquid crystal display unit structure and the manufacturing method thereof |
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| CN101887897B (en) * | 2009-05-13 | 2013-02-13 | 北京京东方光电科技有限公司 | TFT-LCD (Thin Film Transistor Liquid Crystal Display) array base plate and manufacturing method thereof |
| KR101287478B1 (en) * | 2009-06-02 | 2013-07-19 | 엘지디스플레이 주식회사 | Display device having oxide thin film transistor and method of fabricating thereof |
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