CN1114265C

CN1114265C - New-type CMOS charge pump and its cascade method

Info

Publication number: CN1114265C
Application number: CN 99118961
Authority: CN
Inventors: 吉利久; 林斌; 郭胤; 傅一玲
Original assignee: Peking University
Current assignee: Peking University
Priority date: 1999-09-03
Filing date: 1999-09-03
Publication date: 2003-07-09
Anticipated expiration: 2019-09-03
Also published as: CN1256554A

Abstract

The present invention relates to a novel CMOS charge pump and a cascade method thereof. The novel CMOS charge pump is composed of a clock input part 11, a push-pull part 12, a voltage output part 13 and a clock conversion part 14. The present invention has the advantages of simple structure, stable output voltage and high energy efficiency; the present invention reduces threshold value loss, and is suitable for a booster device in an integrated circuit; the present invention can provide a power supply for a circuit module which needs high voltage; the present invention can also be applied to all circuits of which the outer parts are provided for single voltage and the inner parts need a plurality of electric levels; especially, the present invention has important function on the aspect that a non-volatility memory is provided for desired voltage.

Description

A kind of New-type CMOS charge pump and Cascading Methods thereof

The present invention relates to the increasing apparatus in a kind of integrated circuit fields.

The application of charge pump is very extensive, provides level except that supply voltage as giving the dc-to-dc transducer, as providing high voltage to operational amplifier, and is applied to that all outsides provide single voltage and the circuit of the multiple level of inner needs.Especially providing to nonvolatile memory aspect the required voltage, bringing into play important role.

The Dickson charge pump is a charge pump construction in the earliest the sheet, proposed with electric capacity elect voltage, with the basic ideas of diode limits charge transfer direction.Then, occurred several charge pump constructions again in succession, some performance of Dickson charge pump has been improved.Yet in these charge pumps, some is that output voltage boosts with the progression linearity, and the speed of boosting is slower; The output voltage of some has the threshold value loss; Some circuit structure more complicated, chip area is very big; The most important thing is that they all do not consider these extremely crucial performance index of energy efficiency, in the universal day by day raising of emphasizing energy efficiency today more of portable equipment.

The objective of the invention is in order to improve the energy efficiency of charge pump; Realize the inner multiplication of voltage cascade of charge pump, index boosts; Eliminate the threshold value loss in the charge pump; Simplify the electric charge pump structure, dwindle area; Improve charge pump output ripple quality.

Design of the present invention is to achieve these goals.The invention provides a kind of New-type CMOS charge pump, it elects part 12 by

clock importation

11, and 14 4 parts of voltage output 13 and clock conversion portion are formed.Clock importation 11 comprises the

inverter

15,16 of two serial connections.Inverter 15 is made up of PMOS pipe m7 and NMOS pipe m2, the grid of m7 and m2 all is connected on the input clock CLOCK, the source end of m7 and its substrate are connected together and link on the input voltage signal VIN, the source end of m2 and its substrate are connected together and link systematically, the drain terminal of m7 and the drain terminal of m2 are joined together to form the output of inverter 15, clocking nock; Inverter 16 is made up of PMOS pipe m8 and NMOS pipe m3, the grid of m8 and m3 all is connected on the output clock nock of inverter 15, the source end of m8 and its substrate are connected together and link on the input voltage signal VIN, the source end of m3 and its substrate are connected together and link systematically, the drain terminal of m8 and the drain terminal of m3 are joined together to form the output of inverter 16, clocking ck; Clock ck and nock are connected into and elect part 12 and clock conversion portion 14.Election part 12 is made up of NMOS pipe (electing pipe) m1, m6 and a pair of election capacitor C 9_10, the C8_11 of a pair of mutual coupling.The drain terminal of m1 and the drain terminal of m6 are connected together and link on the input voltage signal VIN, and the substrate of m1 and m6 is received systematically and gone up, and the source end that the grid of m1 is connected to m6 is node out2, and the source end that the grid of m6 is connected to m1 is node out1; Elect one of capacitor C 9_10 and terminate on the out1 node, the other end is received on the ck signal that is provided by clock importation 11; Elect one of capacitor C 8_11 and terminate on the node out2, the other end is received on the nock signal that is provided by clock importation 11.Elect part under the election effect of inversion clock ck and nock, produce at node out1, out2 place and to move the clock pulse of VIN (amplitude of supposition clock input signal CLOCK is VIN) (better under the situation on a pair of, voltage range is approximate from VIN to 2VIN), provide it to voltage output 13 and clock conversion portion 14.Voltage output 13 is managed (a pair of transfer tube m13, m10 and a pair of substrate tube m14, m9), 2 electric capacity (filter capacitor C3_2 and capacitance to substrate C2_12) and load resistance R19 by 4 PMOS and is formed.The source of transfer tube m13 terminates on the node out2, and grid is connected on the node out1, and drain terminal is connected on the output voltage node VOUT, and substrate is connected on the node high; The source of transfer tube m10 terminates on the node out1, and grid is connected on the node out2, and drain terminal is connected on the output voltage node VOUT, and substrate is connected on the node high; The source of substrate tube m14 terminates on the node out2, and grid is connected on the node out1, and drain terminal links to each other with substrate, is connected on the node high; The source of substrate tube m9 terminates on the node out1, and grid is connected on the node out2, and drain terminal links to each other with substrate, is connected on the node high; One of filter capacitor C3_2 terminates on the output voltage node VOUT, and the other end is received systematically; One of capacitance to substrate C2_12 terminates on the node high, and the other end is received systematically; One of load resistance R19 terminates on the output voltage node VOUT, and the other end is received systematically.Two transfer tube m13, m10 transmit ceiling voltage 2VIN to output voltage node VOUT by turns every the half period, and two substrate tube m14, m9 then transmit ceiling voltage 2VIN to node high by turns every the half period.Clock conversion portion 14 is made up of two

parts

17,18 that are similar to inverter.17 manage m5 by PMOS pipe m12 and NMOS forms, the grid of m12 is connected on the node out1, the grid of m5 is connected on the clock ck, the source end of m12 and its substrate are connected together and link on the output voltage node VOUT, the source end of m5 and its substrate are connected together and link systematically, and the drain terminal of m12 and the drain terminal of m5 are joined together to form 17 clock signal CKOUT and offer next stage; 18 manage m4 by PMOS pipe m11 and NMOS forms, the grid of m11 is connected on the node out2, the grid of m4 is connected on the clock nock, the source end of m11 and its substrate are connected together and link on the output voltage node VOUT, the source end of m4 and its substrate are connected together and link systematically, and the drain terminal of m11 and the drain terminal of m4 are joined together to form 18 clock signal NOCKOUT and offer next stage.The place different with inverter is that the PMOS of each parts and the grid of NMOS are received on the different clock pulse, the clock pulse scope that the gate pmos utmost point is connect is approximately VIN-2VIN, the clock pulse scope that the NMOS tube grid is connect is 0-VIN, and the output voltage range of two

parts

17,18 is approximate to be 0-2VIN.

In order to realize that output voltage is 2 exponential increase, the present invention also provides a kind of multiplication of voltage cascade system of above-mentioned CMOS charge pump.Its first order constitutes (not having resistance R 19) by above-mentioned charge pump unit module; It following at different levels by the election part 12 in the above-mentioned charge pump unit module, voltage output 13 (except that afterbody, not having resistance R 19) and clock conversion portion 14 constitute.The input of the first order is as the input of entire circuit, and the output of the voltage of the first order is as partial supply voltage input, and the clock output of the first order is as partial clock input, by that analogy; The output of afterbody is as the output of entire circuit.

In order to realize that output voltage is linear growth, the present invention also provides a kind of linear cascade mode of above-mentioned CMOS charge pump.Its first order constitutes (not having resistance R 19) by above-mentioned charge pump unit module; The following at different levels of it are made of election part 12 in the above-mentioned charge pump unit module and voltage output 13 (except that afterbody, not having resistance R 19).The input of the first order is as the input of entire circuit, and the output of the voltage of the first order is as partial supply voltage input, by that analogy; The clock output of the first order is as the clock input of subsequent stages; The output of afterbody is as the output of entire circuit.

Advantage of the present invention and effect: use CMOS charge pump provided by the invention, energy efficiency has obtained large increase, can reach about 99%; And can eliminate the threshold value loss of output voltage, make that output voltage can be near ideal value (be the input voltage of twice to one-level); This charge pump also has simple in structure, and the unit module area is less, output voltage stabilization, advantage such as the ripple quality is good.

The multiplication of voltage cascade operation pattern that the present invention proposes, i.e. multiplication of voltage Cascading Methods.Make the multi-stage cascade output voltage to be particularly useful for the application of the very big voltage amplification of those needs with progression with 2 exponential increase.Ifs circuit requires to be raised to about 24V from 1.5V, and the multiplication of voltage cascade only needs 4 grades of charge pump unit so; If the charge pump (as the Dickson charge pump) with linear growth then needs 20 grades at least.

Fig. 1 is a unit module circuit structure diagram of supporting the New-type CMOS charge pump that the multiplication of voltage cascade connects among the present invention.

Fig. 2 is a New-type CMOS charge pump circuit structure diagram of realizing that the cascade of two-stage multiplication of voltage connects.

Fig. 3 is a New-type CMOS charge pump circuit structure diagram of realizing that the two-stage linear cascade connects.

Below in conjunction with accompanying drawing the present invention is elaborated, provide this inventive embodiment.

The New-type CMOS charge pump unit module circuit that support multiplication of voltage cascade shown in Figure 1 connects is made up of four parts; Part 12, voltage output 13 and clock conversion portion 14 are elected in clock importation 11.

Clock importation 11 comprises the

inverter

15,16 of two serial connections.Inverter 15 is made up of PMOS pipe m7 and NMOS pipe m2, the grid of m7 and m2 all is connected on the input clock CLOCK, the source end of m7 and its substrate are connected together and link on the input voltage signal VIN, the source end of m2 and its substrate are connected together and link systematically, the drain terminal of m7 and the drain terminal of m2 are joined together to form the output of inverter 15, clocking nock; Inverter 16 is made up of PMOS pipe m8 and NMOS pipe m3, the grid of m8 and m3 all is connected on the output clock nock of inverter 15, the source end of m8 and its substrate are connected together and link on the input voltage signal VIN, the source end of m3 and its substrate are connected together and link systematically, the drain terminal of m8 and the drain terminal of m3 are joined together to form the output of inverter 16, clocking ck; Clock ck and nock are connected into and elect part 12 and clock conversion portion 14.

Election part 12 is made up of NMOS pipe (electing pipe) m1, m6 and a pair of election capacitor C 9_10, the C8_11 of a pair of mutual coupling.The drain terminal of m1 and the drain terminal of m6 are connected together and link on the input voltage signal VIN, and the substrate of m1 and m6 is received systematically and gone up, and the source end that the grid of m1 is connected to m6 is node out2, and the source end that the grid of m6 is connected to m1 is node out1; Elect one of capacitor C 9_10 and terminate on the out1 node, the other end is received on the ck signal that is provided by clock importation 11; Elect one of capacitor C 8_11 and terminate on the node out2, the other end is received on the nock signal that is provided by clock importation 11.Elect part under the election effect of inversion clock ck and nock, produce the clock pulse of moving VIN (amplitude of supposition clock input signal CLOCK is VIN) on a pair of (better under the situation, voltage range is similar to from V at node out1, out2 place _INTo 2V _IN, provide it to voltage output 13 and clock conversion portion 14.Particularly, when ck is ' 0 ', nock for ' 1 ' time, node out1, out2 have been charged to VIN-V in advance _TWhen ck become ' 1 ', when nock becomes ' 0 ' simultaneously, the voltage of node out1 is lifted to 2VIN-V _T, this make to elect pipe m6 and is in linear zone work, and power supply VIN to node out2 charging, reaches VIN until the voltage of node out2 by m6; When ck become ' 0 ' again, when nock becomes ' 1 ' simultaneously, VIN-V falls back in node out1 voltage more at the beginning _T, the voltage of node out2 then is lifted to 2VIN, and this make to elect pipe m1 and is in linear zone work, and power supply VIN to node out1 charging, reaches VIN until the voltage of node out1 by m1; Such process continues along with the variation of clock ck and nock, and the voltage of stable state lower node out1, out2 is between VIN-2VIN, and the voltage signal of node out1 and out2 remains anti-phase.From finding out, the high voltage of node out1, out2 can reach 2VIN, and power supply VIN manages m1 by electing, the m6 transmission voltage does not have the threshold value loss.

Voltage output 13 is managed (a pair of transfer tube m13, m10 and a pair of substrate tube m14, m9), 2 electric capacity (filter capacitor C3_2 and capacitance to substrate C2_12) and load resistance R19 by 4 PMOS and is formed.The source of transfer tube m13 terminates on the node out2, and grid is connected on the node out1, and drain terminal is connected on the output voltage node VOUT, and substrate is connected on the node high; The source of transfer tube m10 terminates on the node out1, and grid is connected on the node out2, and drain terminal is connected on the output voltage node VOUT, and substrate is connected on the node high; The source of substrate tube m14 terminates on the node out2, and grid is connected on the node out1, and drain terminal links to each other with substrate, is connected on the node high; The source of substrate tube m9 terminates on the node out1, and grid is connected on the node out2, and drain terminal links to each other with substrate, is connected on the node high; One of filter capacitor C3_2 terminates on the output voltage node VOUT, and the other end is received systematically; One of capacitance to substrate C2_12 terminates on the node high, and the other end is received systematically; One of load resistance R19 terminates on the output voltage node VOUT, and the other end is received systematically.The PMOS pipe does not have the threshold value loss when transmitting high voltage.Two transfer tube m13, m10 transmit ceiling voltage 2VIN to output voltage node VOUT by turns every the half period, and two substrate tube m14, m9 then transmit ceiling voltage 2VIN to node high by turns every the half period.Specifically, when node out1 voltage is VIN, when node out2 voltage was 2VIN, transfer tube m13 and substrate tube m14 conducting were given node VOUT charging by node out2 by m13, give node high charging by m14; When node out1 voltage is 2VIN, when node out2 voltage was VIN, transfer tube m10 and substrate tube m9 conducting were given node VOUT charging by node out1 by m10, give node high charging by m9.After reaching stable state, the magnitude of voltage of output voltage node VOUT and node high is all near 2VIN.Substrate tube m14, m9 and capacitance to substrate C2_12 acting in conjunction, the voltage of stable node high offers the substrate of 4 PMOS pipes in the high value, has realized the substrate substitute technology, it is partially anti-to have guaranteed that PMOS pipe source-substrate knot, leakage-substrate are tied, thereby has improved energy efficiency.Filter capacitor plays the effect of regulated output voltage in approximate 2VIN, can improve the ripple quality of output voltage.Output voltage signal VOUT also will offer clock conversion portion 14 as its supply voltage not only as the output voltage of unit module.

Clock conversion portion 14 is made up of two

parts

17,18 is approximate to be 0-2VIN.Specifically, 17 to be example, supply voltage is the 2VIN that output voltage node VOUT provides.When node out1 voltage is 2VIN, when clock ck is VIN, the m5 conducting, m12 turn-offs, and node CKOUT discharges by m5, reduces to 0V until its voltage; When node out1 voltage is VIN, when clock CK is 0V, the m12 conducting, m5 turn-offs, and power supply VOUT to node CKOUT charging, is raised to 2VIN until the voltage of node CKOUT by m12; 18 in like manner.In addition, between two

parts

17,18, input clock pulse signals constitutes anti-phase respectively accordingly, and the clock signal of being exported also is anti-phase.Clock pulse signal CKOUT, the NOCKOUT of these part 14 outputs will be as the clock input of next stage charge pump unit module.

Fig. 2 is that the two-stage multiplication of voltage cascade of indication New-type CMOS charge pump of the present invention connects circuit structure diagram, is the multiplication of voltage Cascading Methods.Its first order constitutes (not having resistance R 19) by the unit module among Fig. 1; Its second level is by the election part 12 in Fig. 1 unit module, and voltage output 13 and clock conversion portion 14 constitute.The input V1 of the first order and CLOCK are as the input of entire circuit; The voltage output V2 of the first order imports as partial supply voltage, and clock output twock, the twonock of the first order import as partial clock; Partial output V3, THREECK, THREENOCK are as the output of entire circuit, and this circuit can realize that output voltage is 2 exponential increase.

Fig. 3 is that the two-stage linear cascade of indication New-type CMOS charge pump of the present invention connects circuit structure diagram, is the linear cascade method.Its first order constitutes (not having clock conversion portion 14 and resistance R 19) by the unit module among Fig. 1; Its second level is made of election part 12 in Fig. 1 unit module and voltage output 13.The input V1 of the first order and CLOCK are as the input of entire circuit; The voltage output V2 of the first order imports as partial supply voltage, and clock CK, the NOCK of the first order is also as partial clock input; Partial output V3 is as the output of entire circuit, and this circuit can realize that output voltage is 2 linear multiplier.

Claims

1. a New-type CMOS charge pump comprises clock importation 11, is made up of the inverter 15,16 of two serial connections; Elect part 12, form by NMOS pipe m1, m6 and a pair of election capacitor C 9_10, the C8_11 of a pair of mutual coupling; Voltage output 13 is that a pair of transfer tube m13, m10 and a pair of substrate tube m14, m9,2 electric capacity are that filter capacitor C3_2 and capacitance to substrate C2_12 and load resistance R19 form by 4 PMOS pipes; With clock conversion portion 14, form by parts 17, parts 18, it is characterized in that: the parts 17 of clock conversion portion 14 are made up of PMOS pipe m12 and NMOS pipe m5 polyphone, the grid of m12 is connected on the node out1, the grid of m5 is connected on the clock ck, the source end of m12 and its substrate are connected together and link on the output voltage node VOUT, the source end of m5 and its substrate are connected together and link systematically, and the clock signal CKOUT that the drain terminal of m12 and the drain terminal of m5 are joined together to form parts 17 offers next stage; Parts 18 are made up of PMOS pipe m11 and NMOS pipe m4 polyphone, the grid of m11 is connected on the node out2, the grid of m4 is connected on the clock nock, the source end of m11 and its substrate are connected together and link on the output voltage node VOUT, the source end of m4 and its substrate are connected together and link systematically, and the clock signal NOCKOUT that the drain terminal of m11 and the drain terminal of m4 are joined together to form parts 18 offers next stage; Because the PMOS of each parts and the grid of NMOS are received on the different clock pulse, the clock pulse scope that the gate pmos utmost point is connect is approximately VIN-2VIN, the clock pulse scope that the NMOS tube grid is connect is 0-VIN, and therefore the output voltage range of two parts 17,18 is 0-2VIN.

2. CMOS charge pump according to claim 1 is characterized in that: it is that the clock pulse generation amplitude of 0-VIN is the generator of the clock pulse of 0-2VIN that its clock conversion portion can be used for by amplitude.

3. Cascading Methods that realize the described CMOS charge pump of claim 1 comprise multiplication of voltage cascade and linear cascade, to realize that respectively output voltage increases with charge pump progression index and two kinds of hoisting way of linear increase, it is characterized in that:

The multiplication of voltage cascade connects circuit structure: the first order is made of the described CMOS charge pump of claim 1; Subsequent stages is by the election part 12 of the described CMOS charge pump of claim 1, and voltage output 13 and clock conversion portion 14 constitute; The input V1 of the first order and CLOCK are as the input of entire circuit; The voltage output V2 (its value is 2 times of V1) of the first order imports as partial supply voltage, and clock output twock, the twonock of the first order import as partial clock, and voltage amplitude is 0 to 2 times of V1; Partial voltage output V3 (its value is 4 times of V1) is as the supply voltage input of the third level, and partial clock output THREECK, THREENOCK are as the clock input of the third level, and voltage amplitude is 0 to 4 times of V1; The output voltage of the third level is 8 times of V1; Below at different levels the rest may be inferred, the output of afterbody is as the output of entire circuit;

Linear cascade connects circuit structure: every grade clock input is CK and NOCK, and voltage amplitude is 0V to V1, and every grade output voltage promotes V1 than its input voltage; Therefore the output voltage of charge pump is with the progression linear growth, and the output voltage of the third level is 4 times of V1;

The multiplication of voltage cascade mixes use with linear cascade, can provide the output voltage of any multiple V1 with minimum charge pump progression.