CN111415945B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN111415945B
CN111415945B CN201910029547.7A CN201910029547A CN111415945B CN 111415945 B CN111415945 B CN 111415945B CN 201910029547 A CN201910029547 A CN 201910029547A CN 111415945 B CN111415945 B CN 111415945B
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layers
type
insulating
active
forming
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CN111415945A (en
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胡志玮
叶腾豪
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A semiconductor structure includes a plurality of stacked layers, a plurality of active pillar elements, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active columnar elements are disposed in the channels and are separated from each other in each of the channels. The active columnar elements respectively include two n-type heavily doped portions at both sides thereof. The n-type heavily doped portions extend in a substantially vertical direction, respectively. The n-type heavily doped portions are respectively connected with two corresponding stacked layers in the stacked layers. Insulating material is located in the remaining space between the active columnar elements in the trenches. The insulating material is a silica glass that includes an element that can be used as an n-type dopant.

Description

Semiconductor structure and forming method thereof
Technical Field
The invention relates to a semiconductor structure and a forming method thereof. More particularly, the present invention relates to a semiconductor structure including a heavily n-doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom and a method of forming the same.
Background
Three-dimensional (3D) semiconductor structures have been developed for reasons of reduced volume, reduced weight, increased power density, and improved portability. Typically, a stack comprising a plurality of layers may be formed on a substrate and separated from each other by high aspect ratio trenches. In some types of 3D semiconductor structures, a doped portion extending in a vertical direction may be further configured in the channel. Such doped portions may be manufactured by a process of forming a vertically arranged polysilicon layer and a subsequent (ion) implantation process. However, since the implantation process is typically performed from above the entire structure, and these portions are vertically disposed in the high aspect ratio channel, it is difficult to obtain a uniform doping concentration in the vertical direction. Generally, the doping concentration near the top is higher than near the bottom. This situation may result in an electrical difference between the device near the top and the device near the bottom.
Disclosure of Invention
The present invention is directed to a semiconductor structure and a method of forming the same. According to the present invention, it is possible to provide in the semiconductor structure an n-type heavily doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom.
According to some embodiments, the semiconductor structure includes a plurality of stacked layers, a plurality of active pillar elements, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active columnar elements are disposed in the channels and are separated from each other in each of the channels. The active columnar elements include two heavily n-doped portions on both sides of each of the active columnar elements, respectively. The n-type heavily doped portions extend in a substantially vertical direction, respectively. The n-type heavily doped portions are respectively connected to two corresponding stacked layers of the stacked layers. Insulating material is located in the remaining space between the active columnar elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant.
According to some embodiments, a method of forming such a semiconductor structure includes the following steps. First, an initial structure is provided. The initial structure includes a plurality of stacked layers separated from each other by a plurality of trenches. And forming a plurality of active columnar element semi-finished products in the channels. The active pillar element semifinished products are separated from each other in each of these channels. An insulating material is filled into the remaining space between the active pillar device semi-finished products in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant. Then, a plurality of n-type heavily doped portions are formed between the active pillar element semi-finished product and the insulating material by performing a thermal process of driving the element, which can be applied as an n-type dopant, into the active pillar element semi-finished product.
In order that the manner in which the above recited and other aspects of the invention are obtained will be readily understood, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings, in which:
drawings
Fig. 1 illustrates an exemplary semiconductor structure according to an embodiment.
Figures 2A-2B through 15A-15B illustrate various stages of a semiconductor structure during an exemplary method of forming a semiconductor structure according to an embodiment.
[ notation ] to show
100: semiconductor structure
102: laminate layer
104: conductive strip
106: insulating strip
108: channel
110: active columnar element
112: n-type heavily doped part
114: storage layer
116: channel layer
118: insulating layer
120: n-type heavily doped region
122: insulation part
124: insulating material
200: initial structure
202: substrate board
204: laminate layer
206: conductive strip
208: insulating strip
210: stress compensation layer
212: channel
214: initial storage layer
216: initial channel layer
218: gate control region
220: p-type doped region
222: insulating layer
224: intrinsic material
226: contact plug
228: semi-finished product of active columnar element
230: insulating material
232: heavily n-doped portion
234: contact element
BL11, BL12, BL21, BL22: bit line
SL11, SL12, SL21, SL22: source line
R: region(s)
Detailed Description
Various embodiments will now be described in greater detail with reference to the accompanying drawings, which are provided for purposes of illustration and explanation only and are not intended to be limiting. For clarity, elements may not be drawn to scale. In addition, some elements and/or element symbols may be omitted from some of the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
The semiconductor structure according to the embodiment comprises a plurality of stacked layers, a plurality of active columnar elements and an insulating material. The stacks are separated from each other by a plurality of trenches. The active columnar elements are disposed in the channels and are separated from each other in each of the channels. The active columnar elements respectively include two n-type heavily doped portions at both sides thereof. The n-type heavily doped portions extend in a substantially vertical direction, respectively. The n-type heavily doped portions are respectively connected to two corresponding stacked layers of the stacked layers. Insulating material is located in the remaining space between the active columnar elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant.
An example of such a semiconductor structure is illustrated in fig. 1. For clarity, the semiconductor structure is depicted as a 3D AND flash memory device (3D AND gate flash memory device), AND the insulating material in region R is removed. It can be appreciated, however, that embodiments of the invention are not so limited.
Referring to fig. 1, an exemplary semiconductor structure 100 includes a plurality of stacked layers 102. The stack 102 may include a plurality of conductive strips 104 and a plurality of insulating strips 106, respectively, that are alternately stacked. The number of conductive strips 104 and the number of insulating strips 106 are not particularly limited. Although not shown in fig. 1, the stack 102 may each further include one or more other layers. The stacks 102 are separated from each other by a plurality of channels 108.
The semiconductor structure 100 further includes a plurality of active pillar elements 110. Active columnar elements 110 are disposed in the channels 108 and are separated from each other in each of these channels 108. The active pillar elements 110 include two heavily n-doped portions 112 at both sides thereof, respectively. The two heavily n-doped portions 112 each extend in a substantially vertical direction. Herein, the vertical direction means a direction perpendicular to a major surface of the semiconductor structure, such as an upper surface of a substrate (not shown in fig. 1) on which the stack 102 is formed. In the drawings, the vertical direction is the Z direction, and as shown in fig. 2A to 15A, the upper surface of the substrate extends in the X-Y plane. The term "substantially vertical direction" allows for some slight angular deviation from a precisely vertical direction that is acceptable in semiconductor devices. Such deviations may be the result of, for example, process limitations. Two heavily n-doped portions 112 are respectively connected to two corresponding stacks 102 in the stacks 102. More specifically, on the X-Y plane, heavily n-doped portion 112 may extend in a direction perpendicular to the extending direction of stack 102.
As an and gate flash memory device, in the semiconductor structure 100, the active pillar element 110 may further include two memory layers 114, two channel layers 116, and an insulating layer 118, respectively. Two memory layers 114 are disposed on the sidewalls of two corresponding stacks 102, respectively. Two channel layers 116 are disposed between the two memory layers 114. Two via layers 116 are respectively disposed on sidewalls of the memory layer 114. An insulating layer 118 is disposed between the two channel layers 116. Two channel layers 116 and an insulating layer 118 are located between two heavily n-doped portions 112. Although not shown in fig. 1, the active pillar elements 110 may each further include one or more other elements. For example, the active pillar elements 110 may each further include a contact plug disposed on the insulating layer 118. The contact plug undergoes a p-type implant. The active pillar elements 110 may each further include a p-type doped region disposed below the insulating layer 118.
Correspondingly, the heavily n-doped portion 112 may include two heavily n-doped regions 120 and an insulating region 122, respectively. Two heavily n-doped regions 120 are respectively disposed adjacent to the two corresponding stacks 102. The insulating portion 122 is disposed between the two heavily n-doped portions 120. More specifically, the two heavily n-doped regions 120 correspond to the two channel layers 116, and the insulating region 122 corresponds to the insulating layer 118. According to some embodiments, the contact plug (not shown in fig. 1) has a first doping concentration, the two heavily n-doped regions 120 have a second doping concentration, and the second doping concentration is higher than the first doping concentration.
As an and gate flash memory device, in the semiconductor structure 100, a plurality of memory cells can be defined at the intersection of the conductive strip 104 and the channel layer 116. According to some embodiments, the conductive strip 104 may be a word line, and wherein for each of the active pillar elements 110, one of the two heavily n-doped portions 112 is electrically connected to a bit line and the other is electrically connected to a source line. In the semiconductor structure 100, the active columnar elements 110 are arranged in an alternating manner. Correspondingly, bit line pairs, such as bit lines BL11 and BL12 and BL21 and BL22, and source line pairs, such as source lines SL11 and SL12 and SL21 and SL22, are provided. It can be appreciated, however, that other types of configurations can be applied for the active pillar elements 110 and corresponding bit lines and source lines.
The semiconductor structure 100 further includes an insulating material 124. An insulating material 124 is located in the remaining spaces between the active columnar elements 110 in the trenches 108. Insulating material 124 is a silicon glass that includes an element that may be used as an n-type dopant. For example, the silica glass may be Phosphor Silica Glass (PSG) or Arsenic Silica Glass (ASG).
A method of forming a semiconductor structure according to an embodiment includes the following steps. First, an initial structure is provided. The initial structure includes a plurality of stacked layers separated from each other by a plurality of trenches. And forming a plurality of active columnar element semi-finished products in the channels. The active pillar element semifinished products are separated from each other in each of these channels. An insulating material is filled into the remaining spaces between the active pillar element semi-finished products in the trenches. The insulating material is a silica glass that includes an element that can be used as an n-type dopant. Then, a plurality of n-type heavily doped portions are formed between the active columnar element semi-finished product and the insulating material by performing a thermal process of driving the element, which can be applied as an n-type dopant, into the active columnar element semi-finished product.
The semiconductor structure is illustrated in fig. 2A-2B through 15A-15B at various stages of such a process, wherein the drawing indicated by "a" and the drawing indicated by "B" show a perspective view and a corresponding cross-sectional view, respectively, along the line C-C "in the corresponding drawing indicated by" a ". For clarity, only a single stack and portions of two adjacent channels are shown. The semiconductor structure is depicted as a 3D and gate flash memory device. It can be appreciated, however, that embodiments of the invention are not so limited.
Referring to fig. 2A-2B, an initial structure 200 is provided. The initial structure 200 includes a substrate 202. The initial structure 200 also includes a plurality of stacked layers 204, which may be formed on the substrate 202. The stack 204 may include a plurality of conductive strips 206 and a plurality of insulating strips 208, respectively, that are alternately stacked on top of each other. Conductive strip 206 may be formed of doped polysilicon or any other suitable material. The insulating strips 208 may be formed of silicon oxide. In some embodiments, the stack 204 further includes a stress compensation layer 210 over the conductive strips 206 and the insulating strips 208, respectively. The stress compensation layer 210 compensates for tensile stress and prevents the high aspect ratio stack 204 from collapsing or bending. The stress compensation layer 210 may be formed of silicon nitride. The stacks 204 are separated from each other by a plurality of channels 212.
Referring to fig. 3A-3B, an initial memory layer 214 is formed conformally on the initial structure 200. The initial memory layer 214 may BE a BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon) layer, ONONO (oxide-nitride-oxide) layer, or any other suitable layer.
Referring to fig. 4A-4B, an initial channel layer 216 is formed conformally on the initial memory layer 214. The initial channel layer 216 may be formed of polysilicon. The initial channel layer 216 includes a plurality of gate control regions 218 corresponding to the conductive strips 206, as shown in fig. 4B.
Referring to fig. 5A-5B, optionally, p-type dopants may be implanted into portions of the initial channel layer 216 at the bottom of the trenches 212. Thereby forming a plurality of p-type doped regions 220. This step ensures that the bottom part of the channel is p-doped, thus enabling a reduction of leakage paths. The p-type doped region 220 may be further cut at a subsequent stage (e.g., the stage described with reference to fig. 12A-12B) and form the p-type doped region of the active pillar element 110 disposed under the insulating layer 118 as described with reference to fig. 1.
Referring to fig. 6A to 6B, a plurality of insulating layers 222 are formed in the remaining space of the trench in a corresponding manner. The insulating layer 222 may be formed of oxide. Next, a planarization process may be performed, as shown in FIGS. 7A-7B. The planarization process terminates at the portion of the initial memory layer 214 above the stack 204. The planarization process may be a Chemical Mechanical Planarization (CMP) process, an etch back (etchback) process, or any other suitable planarization process.
Referring to fig. 8A-8B, the top portion of the insulating layer 222 is removed. Next, referring to fig. 9A-9B, an intrinsic material 224, such as polysilicon, is filled into the space created by the step of removing the top portion of the insulating layer 222. As shown in fig. 9A-9B, the intrinsic material 224 may form a layer over the semiconductor structure. Therefore, a planarization process may be performed, as shown in FIGS. 10A-10B. The planarization process also terminates at the portion of the initial memory layer 214 above the stack 204. Referring to fig. 11A-11B, an implantation process is performed using p-type dopants. In particular, intrinsic material 224 (polysilicon) is implanted using the p-type dopant. The p-type dopant may be, but is not limited to, boron (B). According to some embodiments, the doping concentration of polysilicon implanted with p-type dopants may fall within 10 15 cm -3 Of the order of magnitude. Thereby forming a plurality of contact plugs 226 of these active columnar element semi-finished products. Contact plug 226 provides sufficient silicon portion thickness for landing (plating) of the contact. The implantation process using p-type dopants can provide p-type doped contact plugs 226, particularly p-type heavily doped contact plugs 226, which can reduce the plug resistance and prevent punch through (punch through) from occurring.
Next, referring to fig. 12A-12B, at least the portions of the initial channel layer 216 and the insulating layer 222 in each of the trenches are cut. As a result, a plurality of active pillar device blanks 228 are formed in the trenches 212. In each of these channels 212, the active pillar element blanks 228 are separated from each other. The active pillar element blanks 228 may be configured, but are not limited to being, in an alternating manner. The openings formed by the cutting step may extend into the substrate 202 as shown in fig. 12B. Alternatively, the openings may terminate at the initial storage layer 214 without extending to the substrate 202.
Referring to fig. 13A-13B, an insulating material 230 is filled into the trenches 212 in the remaining space between the active pillar elements 228 (i.e., the openings formed at the previous stage). The insulating material is a silica glass that includes an element that can be used as an n-type dopant. The silica glass may be, for example, phosphosilicate glass (PSG) or Arsenic Silicate Glass (ASG). In other words, an element that can be applied As an n-type dopant in the silica glass is phosphorus (P) or arsenic (As). In some embodiments, PSG is preferred because of the higher thermal diffusion rate of phosphorus in PSG compared to arsenic in ASG. According to some embodiments, the doping concentration of the polysilicon implanted with the p-type dopant in the stage described with reference to fig. 8A-8B is lower than a doping concentration of the element that can be applied as an n-type dopant in the subsequent thermal process driven from the insulating material 230 into the active pillar element semi-finished product 228, so that the portions of the initial channel layer 216 and the contact plug 226 near the insulating material 230 after the cutting form the n-type heavily doped portion 232 (shown in fig. 14A-14B) after the thermal process. For example, the doping concentration in polysilicon implanted with p-type dopants falls at 10 15 cm -3 Of the order of magnitude, the doping concentration of the element applicable as an n-type dopant driven from the insulating material into the active pillar element semifinished product may be equal to or higher than 5 × 10 20 cm -3 . Correspondingly, in the insulating material 230, the doping concentration of the element applicable as n-type dopant is equal to or higher than 5 × 10 20 cm -3 。
Referring to fig. 14A-14B, a plurality of heavily n-doped portions 232 are formed between the active pillar element blank 228 and the insulating material 230 by performing a thermal process that drives elements that may be applied as n-type dopants into the active pillar element blank 228. In this way, the active pillar device described with reference to fig. 1 can be formed. The element that may be applied as an n-type dopant can be driven into the undoped or doped polysilicon portion of the active pillar element blank 228 by a thermal process because it tends to stay in the polysilicon more than in silicon glass. According to some embodiments, the thermal process may be performed at 950 ℃ for 30 minutes. It can be appreciated that higher temperatures and/or longer heating times can be used. As described above, in the case where the doping concentration of polysilicon is implanted with p-type dopants lower than the doping concentration of an element that can be applied as n-type dopants driven from the insulating material into the active pillar element semifinished product, the cut initial channel layer 216 and the portion of the contact plug 226 near the insulating material 230 form the n-type heavily doped portion 232 after the thermal process, as shown in fig. 14A to 14B.
Referring to fig. 15A-15B, a plurality of contacts 234 may be formed on the n-type heavily doped portions 232, respectively. The two heavily n-doped portions 232 of each active pillar element can serve as a source region and a drain region, respectively, while the contacts 234 thereon can be used to provide electrical connections to source and bit lines (as shown in fig. 1) to be disposed above the structure. It will be appreciated that some further processing, such as that of forming bit lines and source lines, may be performed after the stage shown in fig. 15A-15B.
According to the present invention, the dopants used in the implantation process for the heavily n-doped portion extending in a substantially vertical direction are provided from a lateral implantation source (i.e., a silicon glass comprising an element that can be used as an n-type dopant). So that a uniform doping concentration can be obtained in the vertical direction. The silica glass can be used to replace insulating materials conventionally used in semiconductor structures to isolate vertically extending elements. Thus, the above process can be easily performed in a self-aligned and controllable manner without much additional cost. Furthermore, these processes are compatible with the general processes of semiconductor devices.
The exemplary 3D and gate flash memory device and exemplary method of forming the same can be used in a variety of applications, particularly those in which a doped portion having a uniform doping concentration in the vertical direction is strongly desired. One example of this is the field of AI memory applications. Furthermore, although the above embodiments are exemplarily directed to 3D memory devices, it can be appreciated that the inventive concept is applicable to other semiconductor structures in which a uniformly n-type heavily doped portion extending in a substantially vertical direction is required.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Various modifications and alterations can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is defined by the claims.

Claims (8)

1. A semiconductor structure, comprising:
a plurality of stacks separated from each other by a plurality of trenches;
a plurality of active columnar elements arranged in the channels and separated from each other in each of the channels, wherein the active columnar elements respectively comprise two n-type heavily doped parts at two sides of each of the active columnar elements, the n-type heavily doped parts respectively extend in a vertical direction, and the n-type heavily doped parts are respectively connected with two corresponding laminated layers in the laminated layers; and
an insulating material in the remaining space between the active pillar elements in the trenches, wherein the insulating material is a silicate glass comprising an element that can be applied as an n-type dopant;
wherein the stacks respectively comprise a plurality of conductive strips and a plurality of insulating strips which are alternately stacked;
wherein the active columnar elements further include:
two memory layers respectively arranged on the sidewalls of the two corresponding stacks;
two channel layers disposed between the two memory layers, wherein the two channel layers are disposed on sidewalls of the two memory layers, respectively; and
an insulating layer disposed between the two channel layers;
wherein the two channel layers and the insulating layer are arranged between the two n-type heavily doped parts; and is
Wherein a plurality of memory cells are defined at the intersections of the conductive strips and the channel layers.
2. The semiconductor structure of claim 1, wherein the active pillar elements each further comprise:
a contact plug disposed on the insulating layer; and
a p-type doped region disposed under the insulating layer.
3. The semiconductor structure of claim 2, wherein the heavily n-doped portions respectively comprise:
two n-type heavily doped parts respectively arranged near the two corresponding laminated layers; and
an insulating part is arranged between the two n-type heavily doped parts.
4. The semiconductor structure of claim 3, wherein said contact plug is p-type implanted and has a first doping concentration, said two heavily n-doped portions have a second doping concentration, and said second doping concentration is higher than said first doping concentration.
5. The semiconductor structure of claim 1, wherein the silicate glass is phosphosilicate glass (PSG) or Arsenic Silicate Glass (ASG).
6. A method of forming a semiconductor structure, comprising:
providing an initial structure comprising a plurality of stacked layers separated from each other by a plurality of trenches;
forming a plurality of active pillar element semi-finished products in the channels, wherein the active pillar element semi-finished products are separated from each other in each of the channels;
filling an insulating material into the residual spaces between the active columnar element semi-finished products in the channels, wherein the insulating material is silicon glass, and the silicon glass comprises an element which can be used as n-type dopant; and
forming a plurality of n-type heavily doped portions between the active pillar element semi-finished products and the insulating material by performing a thermal process of driving the element, which can be applied as an n-type dopant, into the active pillar element semi-finished products;
wherein the step of forming the active columnar element semi-finished products comprises the following steps:
forming an initial storage layer on the initial structure in a conformal manner;
forming an initial channel layer on the initial storage layer in a conformal manner;
implanting portions of the initial channel layer at the bottom of the channels with p-type dopants;
forming a plurality of insulating layers in the residual spaces of the trenches in a corresponding manner;
performing a planarization process, the planarization process terminating at a portion of the initial memory layer on the plurality of layers;
removing a top portion of the insulating layers and forming a plurality of contact plugs of the active columnar device semi-finished products; and
at least portions of the initial channel layer and the insulating layers in each of the channels are cut.
7. The method of claim 6, wherein the initial channel layer is implanted with p-type dopants at a dopant concentration of 10 15 cm -3 Of the order of magnitude of 5 x 10 or higher, a doping concentration of the element applicable as n-type dopant being driven from the insulating material into the active pillar element semifinished products 20 cm -3 And forming the n-type heavily doped parts after the thermal process on the parts, close to the insulating material, of the initial channel layer and the contact plugs after cutting.
8. The method of forming a semiconductor structure of claim 6, wherein
The step of forming the contact plugs includes:
filling polysilicon into the space created by the step of removing the top portion of the insulating layers; and
an implantation process is performed using p-type dopants.
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