CN111415940A - Integrated structure manufacturing method, semiconductor device manufacturing process and integrated structure - Google Patents
Integrated structure manufacturing method, semiconductor device manufacturing process and integrated structure Download PDFInfo
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a manufacturing method of an integrated structure, a manufacturing process of a semiconductor device, the integrated structure and the semiconductor device. The method comprises the following steps: providing a preparation substrate; and etching the prepared substrate by adopting a metal auxiliary chemical etching process to form an integrated structure, wherein the integrated structure comprises the substrate and a plurality of strip-shaped parts which are positioned on the substrate at intervals. The strip-shaped parts formed by the method have good height uniformity, so that the good performance of the devices is ensured. For example, the method can be applied to 3D NAND, the base is a substrate, the stripe portion is a silicon epitaxial layer formed in the prior art, that is, a control gate, and the control gate has better uniformity of height than a control gate formed by a selective epitaxy technique in the prior art.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a manufacturing method of an integrated structure, a manufacturing process of a semiconductor device, the integrated structure and the semiconductor device.
Background
In recent years, Flash memories (Flash memories) have been developed rapidly, and have been widely used in various fields such as microcomputers and automation control, because they have the main characteristics of being able to maintain stored information for a long time without power-on, and have the advantages of high integration, fast access speed, easy erasing and rewriting.
In the prior art, in a 3D NAND process, a stacked structure is usually deposited on a substrate, then a channel is formed by etching, and a silicon epitaxial layer, i.e., a selection control gate, is formed in the channel by SEG.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a method for manufacturing an integrated structure, a process for manufacturing a semiconductor device, an integrated structure, and a semiconductor device, so as to solve the problem in the prior art that the uniformity of the height of a selected control gate formed by an SEG process is poor.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of manufacturing a unitary structure, the method including: providing a preparation substrate; and etching the preparation substrate by adopting a metal auxiliary chemical etching process to form an integrated structure, wherein the integrated structure comprises a substrate and a plurality of strip-shaped parts which are positioned on the substrate at intervals.
Further, etching the preparation substrate by using a metal-assisted chemical etching process to form an integrated structure, comprising: forming a metal layer on the preparation substrate; etching the metal layer to form a plurality of metal parts arranged at intervals; removing part of the preparation substrate below each metal part to form a substrate and the strip-shaped parts on the surface of the substrate; and removing the metal parts which are positioned on the substrate and are positioned at two sides of the strip-shaped part to form the integrated structure.
Further, the material of the metal layer includes gold and/or platinum.
Further, removing a portion of the preliminary substrate under each of the metal portions to form a substrate and the stripe portions on the surface of the substrate, includes: and removing part of the preparation substrate below the metal part by adopting a mixed solution of hydrofluoric acid and hydrogen peroxide.
Further, the preliminary substrate is a silicon preliminary substrate.
In order to achieve the above object, according to an aspect of the present application, there is provided a manufacturing process of the semiconductor device including: and forming an integral structure by adopting any one of the manufacturing methods.
Further, after forming the integral structure, the manufacturing process further includes: forming an insulating isolation layer on an exposed surface of the integrated structure; forming a preparation stacking structure on the surface of the insulation isolation layer, wherein the preparation stacking structure comprises sacrificial layers and insulation medium layers which are alternately arranged; etching and removing part of the preparation stacking structure to form a channel hole which enables the strip-shaped part to be exposed; forming a plurality of structural layers in the channel hole; removing each sacrificial layer; and forming a metal gate structure between two adjacent insulating medium layers.
Further, the preliminary stacked structure includes a plurality of stacked sub-structures, each of the sub-structures includes one of the sacrificial layers and one of the insulating dielectric layers, a preliminary stacked structure is formed on a surface of the insulating isolation layer, the preliminary stacked structure includes sacrificial layers and insulating dielectric layers alternately arranged, and includes: forming a first sub-structure on the surface of the insulating isolation layer, wherein the first sub-structure comprises a first sacrificial layer and a first insulating medium layer which are sequentially overlapped along the direction far away from the substrate, the first sacrificial layer is positioned between the insulating isolation layer and the first insulating medium layer, the distance between the surface of the first insulating medium layer far away from the first sacrificial layer and the lower surface of the substrate is H1, the distance between the surface of the strip part far away from the substrate and the lower surface of the substrate is H2, and H1 is more than or equal to H2; forming a plurality of other said substructures on a first said substructure, thereby forming said preliminary stack structure.
Further, forming a first one of the substructures includes: and sequentially depositing the first sacrificial layer and the first insulating medium layer on the surface of the insulating isolation layer by adopting a growth method of a corrosion inhibitor control enhancement method.
Further, forming a first one of the substructures includes: depositing a first preliminary sacrificial layer on a surface of the insulating isolation layer; carrying out planarization treatment on the first preliminary sacrificial layer to form a second preliminary sacrificial layer with a flat surface, wherein the distance between the surface, far away from the insulating isolation layer, of the second preliminary sacrificial layer and the lower surface of the substrate is H3, and H3 is more than or equal to H2; and carrying out oxidation treatment on the structure after the second preliminary sacrificial layer is formed to form the first sacrificial layer and a first insulating medium layer positioned on the surface of the first sacrificial layer.
Further, performing oxidation treatment on the structure after the second preliminary sacrificial layer is formed, including: and carrying out oxidation treatment on the structure after the second preparation sacrificial layer is formed by adopting an in-situ water vapor generation method.
Further, forming a plurality of structural layers in the channel hole includes: and sequentially forming a charge blocking layer, a charge trapping layer, a charge tunneling layer, a channel layer, an isolation layer and a drain contact structure in the channel.
Further, the sacrificial layer is a silicon nitride layer, and the insulating medium layer is a silicon oxide layer.
According to another aspect of the present application, there is provided a unitary structure formed using any of the fabrication methods.
According to another aspect of the present application, there is provided a semiconductor device formed using any one of the fabrication processes.
According to another aspect of the present application, there is provided a semiconductor device including: a unitary structure comprising a base and a plurality of spaced strips on the base; the stacking structure is positioned on the surface of the substrate and comprises metal gates and insulating medium layers which are alternately arranged, and the stacking structure is provided with a channel hole which enables the strip-shaped part to be exposed; and the structural layers are all positioned in the channel holes.
Further, the plurality of structural layers includes: a charge blocking layer on sidewalls and a bottom of the channel hole; a charge trapping layer on a surface of the charge blocking layer; the charge tunneling layer is positioned on the surface, far away from the charge blocking layer, of the charge trapping layer, a first groove is formed in the charge blocking layer, the charge trapping layer and the charge tunneling layer, and the first groove is abutted to part of the surface of the strip portion; the channel layer is positioned in the rest channel holes and the first groove; an isolation layer on a surface of the channel layer, top surfaces of the channel layer and the isolation layer being lower than an opening of the channel hole; and the drain electrode contact structure is embedded in the channel hole and is positioned on the surface of the channel layer and the surface of the isolating layer.
According to the technical scheme, in the manufacturing method, the prepared substrate is etched by adopting a metal auxiliary chemical etching process to form an integral structure comprising the substrate and a plurality of spaced strip-shaped parts positioned on the substrate, and the strip-shaped parts formed by adopting the metal auxiliary chemical etching process have good uniformity in height, namely the heights are basically the same. The method can be applied to any device needing to be manufactured into the integrated structure in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the base is a substrate, the stripe portion is a silicon epitaxial layer formed in the prior art, that is, a control gate, and the control gate has better uniformity of height than a control gate formed by a selective epitaxy technique in the prior art.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a flow chart of a method of fabricating a unitary structure according to the present application;
FIG. 2 shows a schematic structural view of a preparation substrate of the present application;
FIG. 3 shows a schematic structural view of a metal layer formed on the preliminary substrate of FIG. 2;
FIG. 4 is a schematic diagram illustrating a structure for etching away a portion of a metal layer in the structure of FIG. 3;
FIG. 5 shows a schematic diagram of a structure in which a portion of the substrate in the structure of FIG. 4 is etched away;
FIG. 6 shows a schematic diagram of the structure of FIG. 5 with the metal portion removed;
FIG. 7 is a schematic diagram of a structure in which an insulating spacer layer is formed on the surface of the structure of FIG. 6;
FIG. 8 shows a schematic of the structure of FIG. 7 with a first sub-structure formed on the surface of the structure;
FIG. 9 is a schematic diagram illustrating a structure of forming a first preliminary sacrificial layer on the surface of the structure of FIG. 7;
FIG. 10 shows a schematic diagram of a structure polished to form a second preliminary sacrificial layer in the structure of FIG. 9;
FIG. 11 shows a schematic of the structure of FIG. 7 with a plurality of sub-structures formed on the surface of the structure;
FIG. 12 is a schematic diagram showing the structure of etching away a portion of the preliminary stack structure in the structure of FIG. 11; and
fig. 13 shows a schematic structural diagram of a semiconductor device according to the present application.
Wherein the figures include the following reference numerals:
10', preparing a substrate; 10. a substrate; 11. a strip portion; 20. a metal layer; 21. a metal part; 30. an insulating isolation layer; 40. a first substructure; 41. a first sacrificial layer; 42. a first insulating dielectric layer; 41', a first preliminary sacrificial layer; 42', a second preliminary sacrificial layer; 50. a second substructure; 51. a second sacrificial layer; 52. a second insulating dielectric layer; 60. a third substructure; 61. a third sacrificial layer; 62. a third insulating medium layer; 70. a channel hole; 80. a structural layer; 81. a charge blocking layer; 82. a charge trapping layer; 83. a charge tunneling layer; 84. a channel layer; 85. an isolation layer; 86. and a drain contact structure.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the prior art has poor uniformity of the height of the selective control gate formed by the SEG process, and in order to solve the above problems, the present application provides a method for fabricating a unitary structure, a process for fabricating a semiconductor device, a unitary structure and a semiconductor device.
According to an embodiment of the present application, a method of fabricating a unitary structure is provided. As shown in fig. 1, the method comprises the steps of:
step S101, providing a preliminary substrate 10', as shown in fig. 2;
step S102, etching the preliminary substrate 10' by using a metal-assisted chemical etching process to form an integrated structure, where the integrated structure includes a substrate 10 and a plurality of spaced strips 11 on the substrate 10, as shown in fig. 6.
In the manufacturing method, the prepared substrate is etched by adopting a metal auxiliary chemical etching process to form an integral structure comprising the substrate and a plurality of spaced strip-shaped parts positioned on the substrate, and the strip-shaped parts formed by adopting the metal auxiliary chemical etching process have good uniformity in height, namely the heights are basically the same. The method can be applied to any device needing to be manufactured into the integrated structure in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip portion is a silicon epitaxial layer, i.e., a control gate, formed in the prior art, and the control gate has better uniformity of height compared with a control gate formed by a selective epitaxy technique in the prior art.
In an embodiment of the present application, the preparation substrate 10' is etched by a metal-assisted chemical etching process to form an integrated structure, which includes: forming a metal layer 20 on the preliminary substrate 10' as shown in fig. 3; etching the metal layer 20 to form a plurality of metal portions 21 arranged at intervals, as shown in fig. 4; removing a portion of the preliminary substrate 10' under each of the metal portions 21 to form a substrate 10 and the stripe 11 on the surface of the substrate 10, as shown in fig. 5; the metal portions 21 on the substrate and on both sides of the strip portion 11 are removed to form the integrated structure, as shown in fig. 6. Specifically, the preparation substrate 10 'is etched by using a metal-assisted chemical etching process, the size of the etched metal part 21 can be controlled, so as to control the size of the strip part 11, and the strip part 11 obtained by etching can be ensured to be consistent in height under the condition that the surface of the preparation substrate 10' is flat, so that the high uniformity of the selected control gate is further ensured to be good, and the problem of poor high uniformity of the selected control gate formed by using an SEG process is avoided.
The material of the metal layer can be any feasible metal material (suitable for metal-assisted chemical etching process) in the prior art, and one skilled in the art can select a suitable metal or metals to form the metal layer according to actual situations.
In order to further ensure that the etching effect of the metal-assisted chemical etching process is better, in an embodiment of the present application, the metal layer is made of a noble metal. Further preferably, the material of the metal layer includes gold and/or platinum. Specifically, after the metal part is formed, the metal part formed by gold and/or platinum can not be removed when the substrate is partially removed, so that a plurality of spaced strip-shaped parts are formed on the substrate.
In an embodiment of the present invention, removing a portion of the preliminary substrate 10' under each of the metal portions 21 to form a substrate 10 and the stripe 11 on the surface of the substrate 10 includes: and removing a part of the preliminary substrate 10' below the metal part 21 by using a mixed solution of hydrofluoric acid and hydrogen peroxide. Specifically, the mixed solution of hydrofluoric acid and hydrogen peroxide rapidly removes a portion of the preliminary substrate 10' below the metal portion 21 on the basis of ensuring that the metal portion 21 is not etched, so as to form a plurality of spaced stripe portions 11, as shown in fig. 5.
In an embodiment of the present application, the preliminary substrate is a silicon preliminary substrate, that is, a formed integrated structure is a silicon integrated structure, such an integrated structure may be applied to a device such as 3D NAND, of course, the integrated structure is applied to different devices, and a material of the corresponding preliminary substrate may be adjusted according to different requirements, that is, a person skilled in the art may select a preliminary substrate made of other suitable materials according to actual situations.
According to an embodiment of the present application, a process for fabricating a semiconductor device is provided. The manufacturing process of the semiconductor device comprises the following steps:
the manufacturing method is adopted to form an integrated structure.
In the manufacturing process, the integrated structure is formed by adopting the manufacturing method, namely the prepared substrate is etched by adopting a metal auxiliary chemical etching process to form the integrated structure comprising the substrate and a plurality of spaced strip-shaped parts positioned on the substrate, and the strip-shaped parts formed by adopting the metal auxiliary chemical etching process have good uniformity in height, namely the heights are basically the same. The method can be applied to any device needing to be manufactured into the integrated structure in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip portion is a silicon epitaxial layer, i.e., a control gate, formed in the prior art, and the control gate has better uniformity of height compared with a control gate formed by a selective epitaxy technique in the prior art.
In an embodiment of the present application, after the forming the integrated structure, the manufacturing process further includes: forming an insulating isolation layer 30 on the exposed surface of the integrated structure, as shown in fig. 7; forming a preliminary stacked structure on a surface of the insulating isolation layer 30, wherein the preliminary stacked structure includes sacrificial layers and insulating dielectric layers alternately arranged, for example, a first sacrificial layer 41, a first insulating dielectric layer 42, a second sacrificial layer 51, a second insulating dielectric layer 52, a third sacrificial layer 61 and a third insulating dielectric layer 62 sequentially stacked in a direction away from the substrate, as shown in fig. 11; etching and removing part of the preliminary stacked structure to form a trench hole 70 exposing the bar-shaped portion 11, as shown in fig. 12; forming a plurality of structural layers in the channel holes 70; removing each sacrificial layer; and forming a metal gate structure between two adjacent insulating medium layers. Specifically, the above method forms a preliminary stack structure, then forms the channel hole 70 exposing the stripe portion 11, and forms a plurality of structural layers in the channel hole 70, thus forming the 3D NAND.
In an embodiment of the present application, the preliminary stacked structure includes a plurality of stacked sub-structures, each of the sub-structures includes one of the sacrificial layers and one of the insulating medium layers, and the preliminary stacked structure is formed on a surface of the insulating isolation layer 30, and includes the sacrificial layers and the insulating medium layers alternately arranged, including: forming a first sub-structure 40 on the surface of the insulating isolation layer 30, wherein the first sub-structure 40 includes a first sacrificial layer 41 and a first insulating medium layer 42 sequentially stacked along a direction away from the substrate, as shown in fig. 8, wherein the first sacrificial layer 41 is located between the insulating isolation layer 30 and the first insulating medium layer 42, a distance between a surface of the first insulating medium layer 42 away from the first sacrificial layer 41 and the lower surface of the substrate is H1, a distance between a surface of the strip portion 11 away from the substrate and the lower surface of the substrate is H2, and H1 is ≧ H2; a plurality of other of the substructures described above are formed on the first substructure 40 to form the preliminary stack structure described above. Specifically, in the first sub-structure 40, since H1 is not less than H2, the first sacrificial layer 41 or the first insulating medium layer 42 covers the surface of the stripe portion 11 away from the substrate, that is, the stripe portion 11 is not exposed, so that the trench hole 70 exposing the stripe portion 11 can be obtained by etching even if only one sub-structure is provided.
It should be noted that a person skilled in the art may stack a suitable number of sub-structures according to practical situations, for example, as shown in fig. 11, the preliminary stacked structure includes a first sub-structure 40, a second sub-structure 50 and a third sub-structure 60, wherein the second sub-structure 50 includes a second sacrificial layer 51 and a second insulating medium layer 52 which are sequentially stacked in a direction away from the substrate, and the third sub-structure 60 includes a third sacrificial layer 61 and a third insulating medium layer 62 which are sequentially stacked in a direction away from the substrate.
In one embodiment of the present application, forming the first sub-structure 40 includes: the first sacrificial layer 41 and the first insulating dielectric layer 42 are sequentially deposited on the surface of the insulating isolation layer 30 by using an Inhibitor Controlled Enhanced (ICE) growth method, as shown in fig. 8. The ICE growth method can form the first sacrificial layer 41 and the first insulating dielectric layer 42 which are dense and flat. Of course, the deposition method is not limited to the ICE growth method, and those skilled in the art may select other deposition methods to deposit the first sacrificial layer 41 and the first insulating dielectric layer 42.
In another embodiment of the present application, forming the first sub-structure 40 includes: depositing a first preliminary sacrificial layer 41' on the surface of the insulating isolation layer 30 as shown in fig. 9; planarizing the first preliminary sacrificial layer 41 ' to form a second preliminary sacrificial layer 42 ' with a flat surface, as shown in fig. 10, wherein a distance between a surface of the second preliminary sacrificial layer 42 ' away from the insulating isolation layer 30 and the lower surface of the substrate is H3, and H3 is H2; the structure after the second preliminary sacrificial layer 42' is formed is subjected to oxidation treatment, so that the first sacrificial layer 41 and the first insulating dielectric layer 42 on the surface of the first sacrificial layer 41 are formed, as shown in fig. 8. Specifically, in the first sub-structure 40, because H3 is not less than H2, the first preliminary sacrificial layer 41 'or the second preliminary sacrificial layer 42' covers the surface of the strip portion 11 away from the substrate, that is, the first sacrificial layer 41 or the first insulating medium layer 42 obtained by the oxidation treatment covers the surface of the strip portion 11 away from the substrate, so that the strip portion 11 is not exposed, and the trench hole 70 exposing the strip portion 11 can be obtained by etching even if only one sub-structure is provided. According to the method, the planarization treatment is carried out after the first preliminary sacrificial layer is formed, so that the surface of the device is relatively flat, the pores of the device are less, the word line leakage current of the device is less, the subsequent manufacturing process difficulty of the device is further ensured to be smaller, and the performance of the device is further ensured to be better.
In an embodiment of the present application, the oxidizing process performed on the structure after the second preliminary sacrificial layer is formed includes: and oxidizing the structure with the second prepared sacrificial layer by an in-situ water vapor generation method. Of course, the method of the oxidation treatment is not limited to the in-situ water vapor generation method, and those skilled in the art may select other methods of the oxidation treatment to form the first sacrificial layer and the first insulating dielectric layer on the surface of the first sacrificial layer after the oxidation treatment.
In one embodiment of the present application, as shown in fig. 13, forming a plurality of structural layers 80 in the channel hole includes: a charge blocking layer 81, a charge trapping layer 82, a charge tunneling layer 83, a channel layer 84, an isolation layer 85, and a drain contact structure 86 are sequentially formed in the channel hole 70. Specifically, the plurality of structural layers can realize the functions of the semiconductor device and avoid electric leakage.
It should be noted that the material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, the channel layer may be a polysilicon layer, the isolation layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
It should be further noted that the material of the specific charge blocking layer may be any feasible material in the prior art, such as silicon dioxide, etc., and the formation manner of the charge blocking layer may also be any feasible manner in the prior art, and a person skilled in the art may select a suitable method and a suitable material according to practical situations to form the above-mentioned charge blocking layer of the present application. The material of the charge trapping layer includes at least one of a silicon oxide compound, a silicon nitride compound, a silicon oxynitride compound and a high-K dielectric, and of course, the material of the charge trapping layer is not limited thereto, and those skilled in the art can select a suitable material to form the matrix material of the present application according to practical situations.
In an embodiment of the present invention, the sacrificial layer is a silicon nitride layer, and the insulating dielectric layer is a silicon oxide layer. Specifically, the silicon nitride layer may be oxidized to form a silicon oxide layer, that is, the second preliminary sacrificial layer may be oxidized to form a first insulating dielectric layer on the surface of the first sacrificial layer, and of course, the materials of the sacrificial layer and the insulating dielectric layer are not limited thereto, and those skilled in the art may select a sacrificial layer and an insulating dielectric layer of appropriate materials according to actual situations.
According to an embodiment of the present application, there is provided an integrated structure formed by the above manufacturing method.
In the above-mentioned integrated structure, the integrated structure is formed by the above-mentioned manufacturing method, that is, the integrated structure includes a substrate and a plurality of spaced strip-shaped portions on the substrate, and the strip-shaped portions of the integrated structure have a better uniformity in height, that is, the heights are substantially the same. The integrated structure can be applied to any device needing to be manufactured in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3DNAND, the substrate is a substrate, the strip part is a silicon epitaxial layer formed in the prior art, namely a control gate, the control gate has better uniformity of height compared with the control gate formed by adopting a selective epitaxial technology in the prior art, and the stress change generated by the device is relatively smaller by adopting the integrated structure, so that the subsequent manufacturing process difficulty of the device is further ensured to be smaller, and the performance of the device is further ensured to be better.
According to an embodiment of the present application, there is provided a semiconductor device formed by using the above-described manufacturing process.
In the semiconductor device, the semiconductor device is formed by the manufacturing process, that is, the semiconductor device comprises the integrated structure, the integrated structure comprises a substrate and a plurality of spaced strip-shaped parts positioned on the substrate, and the heights of the strip-shaped parts of the integrated structure are uniform, that is, the heights are basically the same. The integrated structure can be applied to any device needing to be manufactured in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip part is a silicon epitaxial layer formed in the prior art, namely a control gate, the control gate has better uniformity of height compared with the control gate formed by adopting a selective epitaxial technology in the prior art, and by adopting the integrated structure, the stress variation generated by the device is relatively smaller, the subsequent manufacturing process difficulty of the device is further ensured to be smaller, and the performance of the device is further ensured to be better.
According to an embodiment of the present application, there is provided a semiconductor device including:
a unitary structure comprising a substrate 10 and a plurality of spaced strips 11 on said substrate 10, as shown in fig. 6;
a stack structure on the surface of the substrate, the stack structure including alternately arranged metal gates and insulating dielectric layers, the stack structure having a trench hole 70 exposing the strip portion 11, as shown in fig. 12;
a plurality of structural layers, all of which are located within the channel hole 70. Specifically, the stacked structure has a channel hole 70 exposing the bar portion 11, and a plurality of structural layers are located in an inner layer of the channel hole 70.
In the device, the substrate and the control gate are of an integrated structure, so that a complex process in the prior art is avoided, the problem of poor height uniformity of the control gate caused by epitaxial formation of the control gate in the prior art is avoided, and the good performance of the device is ensured.
In one embodiment of the present application, as shown in fig. 13, the plurality of structural layers 80 includes a charge blocking layer 81, a charge trapping layer 82, a charge tunneling layer 83, a channel layer 84, an isolation layer 85, and a drain contact structure 86, wherein the charge blocking layer 81 is located on the sidewall and the bottom of the channel hole 70; the charge trapping layer 82 on the surface of the charge blocking layer 81; the charge tunneling layer 83 is located on a surface of the charge trapping layer 82 away from the charge blocking layer 81, and the charge blocking layer 81, the charge trapping layer 82, and the charge tunneling layer 83 have a first recess therein, the first recess abutting against a portion of a surface of the stripe portion 11; the channel layer 84 located in the remaining channel hole 70 and the first recess; the isolation layer 85 on the surface of the channel layer 84, the top surfaces of the channel layer 84 and the isolation layer 85 being lower than the opening of the channel hole 70; the drain contact structure 86 is embedded in the channel hole 70 and is located on the surface of the channel layer 84 and the surface of the isolation layer 85. Specifically, the plurality of structural layers can realize the functions of the semiconductor device and avoid electric leakage.
It should be noted that the material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, the channel layer may be a polysilicon layer, the isolation layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
It should be further noted that the material of the specific charge blocking layer may be any feasible material in the prior art, such as silicon dioxide, etc., and the formation manner of the charge blocking layer may also be any feasible manner in the prior art, and a person skilled in the art may select a suitable method and a suitable material according to practical situations to form the above-mentioned charge blocking layer of the present application. The material of the charge trapping layer includes at least one of a silicon oxide compound, a silicon nitride compound, a silicon oxynitride compound and a high-K dielectric, and of course, the material of the charge trapping layer is not limited thereto, and those skilled in the art can select a suitable material to form the matrix material of the present application according to practical situations.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the manufacturing method, the prepared substrate is etched by adopting a metal auxiliary chemical etching process to form an integral structure comprising the substrate and a plurality of strip-shaped parts which are positioned on the substrate at intervals, and the strip-shaped parts formed by adopting the metal auxiliary chemical etching process have good uniformity in height, namely the heights are basically the same. The method can be applied to any device needing to be manufactured into the integrated structure in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip portion is a silicon epitaxial layer, i.e., a control gate, formed in the prior art, and the control gate has better uniformity of height compared with a control gate formed by a selective epitaxy technique in the prior art.
2) In the manufacturing process of the application, the integrated structure is formed by adopting the manufacturing method, namely the prepared substrate is etched by adopting a metal auxiliary chemical etching process to form the integrated structure comprising the substrate and a plurality of strip-shaped parts which are positioned on the substrate, and the strip-shaped parts formed by adopting the metal auxiliary chemical etching process have good uniformity in height, namely the heights are basically the same. The method can be applied to any device needing to be manufactured into the integrated structure in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip portion is a silicon epitaxial layer, i.e., a control gate, formed in the prior art, and the control gate has better uniformity of height compared with a control gate formed by a selective epitaxy technique in the prior art.
3) In the integrated structure of the present application, the integrated structure is formed by using the above manufacturing method, that is, the integrated structure includes a substrate and a plurality of spaced strip-shaped portions on the substrate, and the strip-shaped portions of the integrated structure have a better uniformity in height, that is, the heights are substantially the same. The integrated structure can be applied to any device needing to be manufactured in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip part is a silicon epitaxial layer formed in the prior art, namely a control gate, the control gate has better uniformity of height compared with the control gate formed by adopting a selective epitaxial technology in the prior art, and by adopting the integrated structure, the stress variation generated by the device is relatively smaller, the subsequent manufacturing process difficulty of the device is further ensured to be smaller, and the performance of the device is further ensured to be better.
4) In the semiconductor device of the present application, the semiconductor device is formed by using the above manufacturing process, that is, the semiconductor device includes the above integral structure, the integral structure includes a substrate and a plurality of spaced strip-shaped portions located on the substrate, and the strip-shaped portions of the integral structure have a better uniformity in height, that is, the heights are substantially the same. The integrated structure can be applied to any device needing to be manufactured in the prior art, and the formed strip-shaped parts are good in height uniformity, so that the good performance of the devices is guaranteed. For example, the method can be applied to 3D NAND, the substrate is a substrate, the strip part is a silicon epitaxial layer formed in the prior art, namely a control gate, the control gate has better uniformity of height compared with the control gate formed by adopting a selective epitaxial technology in the prior art, and by adopting the integrated structure, the stress variation generated by the device is relatively smaller, the subsequent manufacturing process difficulty of the device is further ensured to be smaller, and the performance of the device is further ensured to be better.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (17)
1. A method of making a unitary structure, comprising:
providing a preparation substrate;
and etching the preparation substrate by adopting a metal auxiliary chemical etching process to form an integrated structure, wherein the integrated structure comprises a substrate and a plurality of strip-shaped parts which are positioned on the substrate at intervals.
2. The method of claim 1, wherein etching the preliminary substrate using a metal-assisted chemical etching process to form a unitary structure comprises:
forming a metal layer on the preparation substrate;
etching the metal layer to form a plurality of metal parts arranged at intervals;
removing part of the preparation substrate below each metal part to form a substrate and the strip-shaped parts on the surface of the substrate;
and removing the metal parts which are positioned on the substrate and are positioned at two sides of the strip-shaped part to form the integrated structure.
3. The method of claim 2, wherein the material of the metal layer comprises gold and/or platinum.
4. The method according to claim 2, wherein removing a portion of the preliminary substrate under each of the metal portions to form a substrate and the strip portions on the surface of the substrate comprises:
and removing part of the preparation substrate below the metal part by adopting a mixed solution of hydrofluoric acid and hydrogen peroxide.
5. A method of fabricating as claimed in any one of claims 1 to 4, in which the preliminary substrate is a silicon preliminary substrate.
6. A manufacturing process of a semiconductor device is characterized by comprising the following steps:
forming a unitary structure using the method of manufacture of any of claims 1 to 5.
7. The fabrication process of claim 6, wherein after forming the unitary structure, the fabrication process further comprises:
forming an insulating isolation layer on an exposed surface of the integrated structure;
forming a preparation stacking structure on the surface of the insulation isolation layer, wherein the preparation stacking structure comprises sacrificial layers and insulation medium layers which are alternately arranged;
etching and removing part of the preparation stacking structure to form a channel hole which enables the strip-shaped part to be exposed;
forming a plurality of structural layers in the channel hole;
removing each sacrificial layer;
and forming a metal gate structure between two adjacent insulating medium layers.
8. The process of claim 7, wherein said preliminary stack structure comprises a plurality of stacked sub-structures, each of said sub-structures comprising one of said sacrificial layers and one of said insulating dielectric layers,
forming a preliminary stacked structure on a surface of the insulating isolation layer, the preliminary stacked structure including sacrificial layers and insulating dielectric layers alternately arranged, including:
forming a first sub-structure on the surface of the insulating isolation layer, wherein the first sub-structure comprises a first sacrificial layer and a first insulating medium layer which are sequentially overlapped along the direction far away from the substrate, the first sacrificial layer is positioned between the insulating isolation layer and the first insulating medium layer, the distance between the surface of the first insulating medium layer far away from the first sacrificial layer and the lower surface of the substrate is H1, the distance between the surface of the strip part far away from the substrate and the lower surface of the substrate is H2, and H1 is more than or equal to H2;
forming a plurality of other said substructures on a first said substructure, thereby forming said preliminary stack structure.
9. The process of claim 8, wherein forming a first of the sub-structures comprises:
and sequentially depositing the first sacrificial layer and the first insulating medium layer on the surface of the insulating isolation layer by adopting a growth method of a corrosion inhibitor control enhancement method.
10. The process of claim 8, wherein forming a first of the sub-structures comprises:
depositing a first preliminary sacrificial layer on a surface of the insulating isolation layer;
carrying out planarization treatment on the first preliminary sacrificial layer to form a second preliminary sacrificial layer with a flat surface, wherein the distance between the surface, far away from the insulating isolation layer, of the second preliminary sacrificial layer and the lower surface of the substrate is H3, and H3 is more than or equal to H2;
and carrying out oxidation treatment on the structure after the second preliminary sacrificial layer is formed to form the first sacrificial layer and a first insulating medium layer positioned on the surface of the first sacrificial layer.
11. The process of claim 10, wherein oxidizing the structure after forming the second preliminary sacrificial layer comprises:
and carrying out oxidation treatment on the structure after the second preparation sacrificial layer is formed by adopting an in-situ water vapor generation method.
12. The fabrication process of claim 7, wherein forming a plurality of structural layers in the channel hole comprises:
and sequentially forming a charge blocking layer, a charge trapping layer, a charge tunneling layer, a channel layer, an isolation layer and a drain contact structure in the channel.
13. The manufacturing process according to any one of claims 7 to 12, wherein the sacrificial layer is a silicon nitride layer and the insulating dielectric layer is a silicon oxide layer.
14. A unitary structure, characterized in that it is formed using the method of manufacture of any one of claims 1 to 5.
15. A semiconductor device formed by the manufacturing process according to any one of claims 6 to 13.
16. A semiconductor device, comprising:
a unitary structure comprising a base and a plurality of spaced strips on the base;
the stacking structure is positioned on the surface of the substrate and comprises metal gates and insulating medium layers which are alternately arranged, and the stacking structure is provided with a channel hole which enables the strip-shaped part to be exposed;
and the structural layers are all positioned in the channel holes.
17. The semiconductor device of claim 16, wherein the plurality of structural layers comprises:
a charge blocking layer on sidewalls and a bottom of the channel hole;
a charge trapping layer on a surface of the charge blocking layer;
the charge tunneling layer is positioned on the surface, far away from the charge blocking layer, of the charge trapping layer, a first groove is formed in the charge blocking layer, the charge trapping layer and the charge tunneling layer, and the first groove is abutted to part of the surface of the strip portion;
the channel layer is positioned in the rest channel holes and the first groove;
an isolation layer on a surface of the channel layer, top surfaces of the channel layer and the isolation layer being lower than an opening of the channel hole;
and the drain electrode contact structure is embedded in the channel hole and is positioned on the surface of the channel layer and the surface of the isolating layer.
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Application publication date: 20200714 |