CN111413648A - Secondary wiring is to traditional thread binding putting - Google Patents
Secondary wiring is to traditional thread binding putting Download PDFInfo
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- CN111413648A CN111413648A CN202010278751.5A CN202010278751A CN111413648A CN 111413648 A CN111413648 A CN 111413648A CN 202010278751 A CN202010278751 A CN 202010278751A CN 111413648 A CN111413648 A CN 111413648A
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Abstract
The invention discloses a secondary wiring and line aligning device which comprises a sending terminal and a receiving terminal. The transmitting terminal mainly comprises a processor and a pulse transceiving circuit; the receiving terminal mainly comprises a pulse receiving circuit, a processor and a display module. One end of a plurality of secondary cables needing to be aligned is connected to a sending terminal, the other end of the secondary cables needing to be aligned is connected to a receiving terminal, the sending terminal and the receiving terminal form a current loop through the secondary cables needing to be aligned, and a receiving terminal display module displays the serial number of the sending terminal corresponding to each cable. The invention has the advantages that the secondary cables needing to be aligned are utilized to construct the current loops of the transmitting terminal and the receiving terminal, no additional auxiliary loop is needed, a plurality of secondary cables can be detected simultaneously, the time for aligning is greatly shortened, and the workload of aligning is reduced.
Description
Technical Field
The invention relates to the field of secondary wiring, in particular to a secondary wiring and aligning device.
Background
At present, in power grids in railway, metallurgy, power transmission, iron making and other industries, each electric device needs to be subjected to secondary wiring during wiring, and when the number of wires is large, the wires may be connected in error and need to be checked one by one. At present, manual investigation is adopted in most cases, so that the workload is high, and the error rate is high.
The patent with publication number CN206990725U provides a novel transformer substation secondary cable is to line device, including setting up at the measured end and the measuring terminal and the voltage measurement device who measures of secondary cable both ends voltage at the secondary cable both ends that await measuring respectively, the measured end be provided with power, switch Kl, N wiring end and establish ties at power and switch both sides N +1 wiring resistance, N wiring end be connected with the wiring node of arbitrary two adjacent wiring resistance respectively, and correspond on the N wiring end and be provided with the reference numeral, the measuring terminal for the survey line that has the reference numeral row of inserting, and the number of the row's of inserting jack is not less than N, the voltage value between arbitrary two wiring ends is unequal. Although the method does not need an auxiliary cable for constructing a detection loop, a large number of resistors need to be connected in series, high direct-current voltage needs to be applied to two ends of the resistors connected in series, potential safety hazards exist when the direct-current voltage exceeds 36V, and the number of secondary cables which can be detected simultaneously by the method is very limited.
Disclosure of Invention
The present invention is directed to overcome the above problems in the prior art, and provides a secondary wiring and aligning apparatus, which can rapidly detect and distinguish each cable by only using the existing secondary cable without adding an additional auxiliary circuit, and can detect a plurality of cables at the same time, and has a low voltage level.
2. Therefore, the invention provides a secondary wiring and line-aligning device which comprises a transmitting terminal and a receiving terminal.
The sending terminal comprises a processor A and a plurality of pulse transceiving circuits, each pulse transceiving circuit is respectively connected with one end of one cable, the plurality of pulse transceiving circuits are sequentially in a pulse sending state under the control of the processor A, the types of pulses sent by each pulse transceiving circuit are different, meanwhile, the pulse transceiving circuits which are not in the pulse sending state are in a pulse receiving state, and the serial number of each cable corresponds to one type of pulse.
The receiving terminal comprises a processor B, a plurality of pulse receiving circuits and a display module, the other end of each two cables is connected to one pulse receiving circuit, each pulse receiving circuit transmits pulses to the processor B after receiving the pulses, the processor judges the cables corresponding to the serial numbers to be in a communicated state according to the types of the received pulses, and the serial numbers of the communicated cables are displayed on the display module.
Furthermore, the types of the pulses sent by the pulse transceiving circuit are distinguished by pulse widths, and each pulse width corresponds to one pulse type.
Furthermore, the pulse width values of the pulses transmitted by all the pulse transceiving circuits show an arithmetic progression from small to large.
Furthermore, the period of each pulse transceiving circuit in the pulse transmitting state is consistent, and the period is larger than the maximum value of the pulse width value.
Furthermore, the pulse receiving circuit comprises two signal detection units which are reversely connected in parallel, the output end of each signal detection unit is in signal connection with the processor B, and the cables are respectively connected to connecting lines which are connected with the two signal detection units in parallel.
Further, when the number of cables is an odd number, the cables already connected to the pulse receiving circuit are determined, and finally, the cables not connected to the pulse receiving circuit are obtained.
Further, the signal detection unit is an optical coupler, a magnetic isolation device or a current sensor.
Further, the number of pulse receiving circuits in the transmitting terminal is not necessarily equal to the number of pulse receiving circuits in the receiving terminal.
Further, the number of pulse transceiver circuits in the sending terminal is between 2 and 255, and the number of pulse receiver circuits in the receiving terminal is between 2 and 255.
Further, the display module is a display.
The secondary wiring line alignment device provided by the invention has the following beneficial effects:
1. the current loops of the sending terminal and the receiving terminal are constructed by using the secondary cables needing to be aligned, an auxiliary loop is not required to be additionally added, the whole device is simple and easy to operate, and the labor cost is saved;
2. the device can detect a plurality of cables simultaneously, greatly shortens the wire aligning time, is beneficial to operating personnel to better carry out wire aligning work, improves the working efficiency, reduces the workload of wire alignment and accelerates the progress of engineering construction;
3. under the condition that the number of cables is large and the number of cable cores is large, the wiring and wire aligning workload is large, the wire cores with poor insulation are not easy to find, a worker can make mistakes by negligence, the device can effectively improve the accuracy of wiring and wire aligning, and further improve the safety and reliability of the system.
Drawings
FIG. 1 is a schematic diagram of a system connection circuit of a secondary connection alignment apparatus according to the present invention;
fig. 2 is a schematic diagram of a pulse receiving circuit of a receiving terminal in a secondary wiring and alignment device according to the present invention.
Detailed Description
An embodiment of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the embodiment.
In the present application, the type and structure of components that are not specified are all the prior art known to those skilled in the art, and those skilled in the art can set the components according to the needs of the actual situation, and the embodiments of the present application are not specifically limited.
3. Specifically, as shown in fig. 1-2, an embodiment of the present invention provides a secondary wiring and line-aligning device, which includes a sending terminal and a receiving terminal.
The sending terminal comprises a processor A and a plurality of pulse transceiving circuits, each pulse transceiving circuit is respectively connected with one end of one cable, the plurality of pulse transceiving circuits are sequentially in a pulse sending state under the control of the processor A, the types of pulses sent by each pulse transceiving circuit are different, meanwhile, the pulse transceiving circuits which are not in the pulse sending state are in a pulse receiving state, and the serial number of each cable corresponds to one type of pulse.
The receiving terminal comprises a processor B, a plurality of pulse receiving circuits and a display module, the other end of each two cables is connected to one pulse receiving circuit, each pulse receiving circuit transmits pulses to the processor B after receiving the pulses, the processor judges the cables corresponding to the serial numbers to be in a communicated state according to the types of the received pulses, and the serial numbers of the communicated cables are displayed on the display module.
In this embodiment, the types of the pulses sent by the pulse transceiving circuits are distinguished by pulse widths, each pulse width corresponds to one pulse type, meanwhile, the pulse width values of the pulses sent by all the pulse transceiving circuits are in an arithmetic progression from small to large, the arithmetic progression is used, when the widths of the pulses are set, a constructor can easily master the corresponding relationship between the pulse width values and cables, and when the processor a is subjected to program setting, the arithmetic progression is equivalent to easily examine the program, meanwhile, the periods of each pulse transceiving circuit in a pulse transmission state are consistent, and the period is greater than the maximum value of the pulse width values.
In this embodiment, the pulse receiving circuit includes two signal detection units, and two signal detection units are parallelly connected in reverse, each signal detection unit's output with processor B signal connection, the cable is connected respectively on two signal detection unit parallel connection's connecting wire, simultaneously, when the quantity of cable is the odd number, confirms the cable that has connected on the pulse receiving circuit earlier, obtains the cable that does not connect on the pulse receiving circuit at last, promptly when the quantity of cable is the odd number, confirms the serial number of the cable that has connected on the pulse receiving circuit earlier, obtains the serial number of the cable that does not connect on the pulse receiving circuit at last, simultaneously, signal detection unit is optical coupler, the device or the current sensor of magnetic isolation.
In this embodiment, the number of pulse receiving circuits in the transmitting terminal is not necessarily equal to the number of pulse receiving circuits in the receiving terminal. The number of pulse transceiver circuits in the transmitting terminal is between 2 and 255, and the number of pulse receiver circuits in the receiving terminal is between 2 and 255. The display module is a display.
The present invention will be explained and illustrated in detail with reference to specific data. As shown in fig. 1, in this example, 20 cables are taken as an example, one end of each secondary cable is connected to each terminal of the pulse transmitting and receiving circuit 1A to 20A in the transmitting terminal in an unordered manner, and the other end of each secondary cable is connected to each terminal of the pulse receiving circuit 1B to 10B in the receiving terminal in an unordered manner.
The processor a in the transmitting terminal first controls the pulse transmitting/receiving circuit 1A to transmit a pulse having a pulse width of 100us and a period of 21ms, and controls the pulse transmitting/receiving circuits 2A to 20A to be in a pulse receiving state.
The processor a in the transmitting terminal controls the pulse time sent by the pulse transceiving circuit 1A to have a minimum allowable value, and the minimum allowable value affects the pulse period sent by the pulse transceiving circuit and the response time of the secondary pair line device, in this example, 100us is taken as an example, the time is a value that can be set arbitrarily, and preferably, the setting of the minimum allowable value is to ensure that the receiving terminal can respond to and acquire the pulse signal in the minimum allowable value, and to shorten the minimum allowable value as much as possible to reduce the pulse period sent by the pulse transceiving circuit.
After the pulse transceiving circuit 1A finishes transmitting the 100us pulse, the processor a in the transmitting terminal controls the pulse transceiving circuit 1A to be switched to a pulse receiving state, controls the pulse transceiving circuit 2A to transmit the pulse with the period of 21ms and the pulse width of 200us, and controls the pulse transceiving circuits 3A to 20A to be in the pulse receiving state.
After the pulse transceiver circuit 2A finishes transmitting 200us pulses, the processor a in the transmitting terminal controls the pulse transceiver circuit 2A to be switched to a pulse receiving state, controls the pulse transceiver circuit 3A to transmit pulses with a period of 21ms and a pulse width of 300us, and controls the pulse transceiver circuit 1A, the pulse transceiver circuit 4A and the pulse transceiver circuit 20A to be in the pulse receiving state.
Therefore, the processor a in the transmitting terminal sequentially controls each of the pulse transceiving circuits 1A to 20A to transmit pulses, the pulse time transmitted by each of the pulse transceiving circuits is different, the time for the latter to transmit pulses is increased by 100us of pulses based on the pulse time of the former pulse transceiving circuit, and the pulse time transmitted by the pulse transceiving circuit 20A is 21 ms.
The pulse cycle transmitted from the pulse transceiver circuit 1A to the pulse transceiver circuit 20A is the sum of the pulse transmission times of each of the pulse transceiver circuits 1A to the pulse transceiver circuit 20A. When the number of the pulse transceiving circuits is different, the pulse period is also different.
The circuit principles of the pulse transceiving circuit 1A to the pulse transceiving circuit 20A are completely consistent, and the working state of each pulse transceiving circuit is independently controlled by the processor A.
The pulse transceiver circuit can adopt NPN and PNP triode to form a push-pull circuit in a matching mode, or adopt N-channel MOSFET and P-channel MOSFET to form a pair transistor circuit in a matching mode, and can also adopt other forms of controlled switch circuits and integrated chip circuits. When the pulse transceiver circuit receives a high-level control signal from a processor A, the pulse transceiver circuit serves as a signal driving source to output a high-level signal, and the time width of the high-level signal output by the pulse transceiver circuit is consistent with that of the high-level control signal received by the pulse transceiver circuit. When the high-level signal is output by the pulse transceiving circuit, the current output capacity of the pulse transceiving circuit is related to devices adopted by the pulse transceiving circuit. And when the pulse transceiver circuit receives a low-level control signal from the processor A, the signal output end of the pulse transceiver circuit and a signal ground form a passage, and the signal output end of the pulse transceiver circuit is clamped to the signal ground, so that the signal of the pulse transceiver circuit outputs low level. When the pulse transceiver circuit outputs a low-level signal, the current input capacity of the pulse transceiver circuit is related to devices adopted by the pulse transceiver circuit. The pulse transceiving circuit maintains the time width of low level to be consistent with the low level control signal received by the pulse transceiving circuit.
The basic circuit principles of the pulse receiving circuit 1B to the pulse receiving circuit 10B are completely the same, and all are in a pulse receiving state. As shown in fig. 2, taking a pulse receiving circuit 1B as an example, the pulse receiving circuit unit includes two signal detecting units 1C and 2C, the signal detecting units 1C and 2C are in an inverse parallel relationship, and each path of the pulse receiving circuit status signal is independently transmitted to the processor B for detecting the operating status of the pulse receiving circuit.
The signal detection unit can adopt signal isolation devices such as a light coupler, a signal transmitter, a pulse transformer and the like, and can also adopt non-isolated current drive type devices
The forward input end CON1 of the signal detecting unit 1C is connected in parallel with the reverse input end CON4 of the pulse receiving circuit to serve as the signal input end P1 of the pulse receiving circuit, and the reverse input end CON2 of the signal detecting unit 1C is connected in parallel with the forward input end CON3 of the pulse receiving circuit to serve as the signal input end P2 of the pulse receiving circuit.
The signal detection units 1C and 2C may employ optical couplers, magnetic isolation devices, or current sensors, and may implement detection of 0 to 20mA current.
When the signal input end P1 receives a pulse signal from any one of the pulse transceiver circuits in the transmitting terminal, the other pulse transceiver circuits are all in a pulse receiving state, and the signal input end P2 is either connected to any one of the pulse transceiver circuits in the transmitting terminal or is floating; all secondary cables to be paired have odd numbers or even numbers, when the number of the secondary cables to be paired is an even number, the signal input terminal P2 is inevitably connected to any one of the pulse receiving and generating circuits in the transmitting terminal, in this case, the pulse signal from the pulse transceiving circuit in the transmitting terminal flows into the forward input terminal CON1 of the signal detection unit 1C through the P1 terminal, flows out to the P2 through the reverse input terminal CON2 of the signal detection unit 1C, and flows back to the pulse receiving circuit in the transmitting terminal through the secondary cable. At this time, the signal detecting unit 1C outputs the pulse signal SIG1 to the processor B, the processor B determines the corresponding number of the secondary cable connected to the P1 terminal in the transmitting terminal by detecting the time width of the SIG1 pulse, and the signal detecting unit 2C outputs no pulse signal.
Similarly, when the signal input terminal P2 receives the pulse signal from any one of the pulse transceiving circuits in the transmitting terminal, the other pulse transceiving circuits are all in a pulse receiving state, the signal input terminal P1 is inevitably connected to any one of the pulse transceiving circuits in the transmitting terminal, the pulse signal from the pulse transceiving circuit in the transmitting terminal flows into the forward input terminal CON3 of the signal detection unit 2C through the P2 terminal, flows out to the P1 through the reverse input terminal CON4 of the signal detection unit 2C, and flows back to the pulse receiving circuit in the transmitting terminal through a secondary cable. At this time, the signal detecting unit 2C outputs the pulse signal SIG2 to the processor B, the processor B determines the corresponding number of the secondary cable connected to the P2 terminal in the transmitting terminal by detecting the time width of the SIG2 pulse, and the signal detecting unit 1C does not output the pulse signal.
When the number of the secondary cables to be paired is odd, the pulse receiving circuit connected with the last secondary cable cannot form a current loop with any pulse transceiver circuit in the transmitting terminal, and the serial number of the cable can be determined by an exclusion method.
Similarly, the sending terminal and the receiving terminal form a current loop through an existing secondary cable, the receiving terminal judges the corresponding relation of the secondary cables of the sending terminal and the receiving terminal by detecting the pulse time sent by the sending terminal, and a display module in the receiving terminal displays the corresponding relation of the secondary cables, so that the secondary alignment function is realized.
The above disclosure is only for a few specific embodiments of the present invention, however, the present invention is not limited to the above embodiments, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (10)
1. A secondary wiring and line aligning device is characterized by comprising a transmitting terminal and a receiving terminal;
the sending terminal comprises a processor A and a plurality of pulse transceiving circuits, each pulse transceiving circuit is respectively connected with one end of one cable, the plurality of pulse transceiving circuits are sequentially in a pulse transmitting state under the control of the processor A, the types of pulses sent by each pulse transceiving circuit are different, meanwhile, the pulse transceiving circuits which are not in the pulse transmitting state are in a pulse receiving state, and the serial number of each cable corresponds to one type of pulse;
the receiving terminal comprises a processor B, a plurality of pulse receiving circuits and a display module, the other end of each two cables is connected to one pulse receiving circuit, each pulse receiving circuit transmits pulses to the processor B after receiving the pulses, the processor judges the cables corresponding to the serial numbers to be in a communicated state according to the types of the received pulses, and the serial numbers of the communicated cables are displayed on the display module.
2. A secondary wire alignment device as claimed in claim 1, wherein the types of pulses transmitted by the pulse transceiving circuitry are distinguished by pulse widths, each pulse width corresponding to a pulse type.
3. A secondary wiring line-aligning device as claimed in claim 2, wherein the pulse width values of the pulses transmitted by all the pulse transceiving circuits are in an arithmetic progression from small to large.
4. A secondary wire alignment device as claimed in claim 3, wherein each of the pulse transmission and reception circuits is in the pulse transmission state for a period which is substantially equal to the maximum value of the pulse width.
5. A secondary wire-aligning apparatus as claimed in claim 1, wherein said pulse receiving circuit includes two signal detecting units connected in anti-parallel, each having an output connected to said processor B, said cables being connected to the connecting wires of the two signal detecting units connected in parallel, respectively.
6. A secondary wire alignment device as claimed in claim 5, wherein when the number of cables is odd, the cables connected to the pulse receiving circuit are determined first, and the cables not connected to the pulse receiving circuit are obtained last.
7. A secondary wire alignment device as claimed in claim 5, wherein the signal detection unit is an optocoupler, a magnetically isolated device or a current sensor.
8. A secondary wire alignment device as claimed in claim 1, wherein the number of pulse receiving circuits in the transmitting terminal is not necessarily equal to twice the number of pulse receiving circuits in the receiving terminal.
9. A secondary wire alignment device as claimed in claim 1, wherein the number of pulse transceiver circuits in the transmitting terminal is between 2 and 255 and the number of pulse receiver circuits in the receiving terminal is between 2 and 255.
10. A secondary wire alignment device as claimed in claim 1, wherein the display module is a display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010278751.5A CN111413648B (en) | 2020-04-10 | 2020-04-10 | Secondary wiring alignment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010278751.5A CN111413648B (en) | 2020-04-10 | 2020-04-10 | Secondary wiring alignment device |
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| CN111413648A true CN111413648A (en) | 2020-07-14 |
| CN111413648B CN111413648B (en) | 2023-07-18 |
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| CN202010278751.5A Active CN111413648B (en) | 2020-04-10 | 2020-04-10 | Secondary wiring alignment device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435766A (en) * | 2020-11-13 | 2021-03-02 | 中广核工程有限公司 | Nuclear power station containment leakage rate measurement network precision measurement system |
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| CN109358258A (en) * | 2018-09-14 | 2019-02-19 | 国网福建省电力有限公司 | Intelligent secondary circuit cable alignment device |
| CN110244166A (en) * | 2019-07-01 | 2019-09-17 | 中冶宝钢技术服务有限公司 | A kind of cable checking instrument and cable school line method |
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| US4418312A (en) * | 1981-10-23 | 1983-11-29 | Bell Telephone Laboratories, Incorporated | Apparatus for testing multi-conductor cables |
| CN2044075U (en) * | 1988-09-21 | 1989-09-06 | 董梁 | Cable matching device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112435766A (en) * | 2020-11-13 | 2021-03-02 | 中广核工程有限公司 | Nuclear power station containment leakage rate measurement network precision measurement system |
| CN112435766B (en) * | 2020-11-13 | 2024-04-30 | 中广核工程有限公司 | Nuclear power station containment leak rate measurement network precision measurement system |
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| Publication number | Publication date |
|---|---|
| CN111413648B (en) | 2023-07-18 |
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