CN111404560B - Error correction method for sequence in state machine - Google Patents

Error correction method for sequence in state machine Download PDF

Info

Publication number
CN111404560B
CN111404560B CN202010213889.7A CN202010213889A CN111404560B CN 111404560 B CN111404560 B CN 111404560B CN 202010213889 A CN202010213889 A CN 202010213889A CN 111404560 B CN111404560 B CN 111404560B
Authority
CN
China
Prior art keywords
sequence
input
state
path
state machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010213889.7A
Other languages
Chinese (zh)
Other versions
CN111404560A (en
Inventor
叶崇光
张远
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Original Assignee
Shanghai IC R&D Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai IC R&D Center Co Ltd filed Critical Shanghai IC R&D Center Co Ltd
Priority to CN202010213889.7A priority Critical patent/CN111404560B/en
Publication of CN111404560A publication Critical patent/CN111404560A/en
Application granted granted Critical
Publication of CN111404560B publication Critical patent/CN111404560B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4115—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors list output Viterbi decoding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

The invention provides an error correction method for a sequence in a state machine, which comprises the following steps: constructing state sequences for indicating different states in a state machine, and adopting a preset convolution method to encode each state sequence to obtain and store different indication sequences; the state machine obtains an input signal, determines a next state sequence corresponding to a next state of the state machine based on the input signal, obtains a next indication sequence corresponding to the next state sequence, decodes the next indication sequence based on a preset convolution method by using a Viterbi decoding method to obtain a verification sequence, and compares whether the verification sequence is consistent with the next indication sequence or not so as to judge whether the next indication sequence is in error or not; when the indication sequences are inconsistent, error correction operation is performed on the next indication sequence based on the verification sequence. The method provided by the invention can automatically correct the sequence stored in the state machine so as to ensure that the sequence stored in the state machine is always correct, thereby enabling the state machine to correctly switch states.

Description

Error correction method for sequence in state machine
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method for correcting errors in a sequence in a state machine.
Background
The state machine is mainly used for completing switching of different states so as to realize key functions of time sequence, response, control and the like of the circuit. The state machine stores state sequences used for indicating different states, and the state opportunity stores a certain state sequence as a current state sequence in a certain time period so as to indicate the current state of the state machine. And the state machine also stores switching conditions among different states, receives an input signal, judges whether the input signal accords with the switching conditions of the current state of the state machine, determines the next state corresponding to the current state based on the input signal when the input signal accords with the switching conditions of the current state, and stores a state sequence of the next state as a current state sequence so as to realize state switching.
However, in the related art, when the state sequence is stored in the state machine, the state is easily interfered by the external environment or other factors and is not correctly indicated, and when the state machine switches states, the state machine is easily caused to enter an error state, and the state machine is likely to be locked, so that the state machine cannot operate correctly and the performance of the state machine is affected. Therefore, there is a need for a method for correcting a sequence in a state machine, so as to ensure that the state sequence stored in the state machine is free from errors, ensure that the state sequence can always indicate a state correctly, and further ensure that the state machine can switch states correctly.
Disclosure of Invention
The invention aims to provide an error correction method for a sequence in a state machine, so as to prevent the sequence stored in the state machine from generating errors, and enable the state machine to correctly switch states.
To achieve the above object, the present invention provides a method for correcting errors in a sequence in a state machine, the method comprising:
constructing state sequences for indicating different states in a state machine, adopting a preset convolution method to encode each state sequence to obtain different indication sequences, and storing the indication sequences into the state machine;
the state machine obtains an input signal, determines a next state sequence corresponding to a next state of the state machine based on the input signal, obtains a next indication sequence corresponding to the next state sequence, decodes the next indication sequence based on the preset convolution method by using a viterbi decoding method to obtain a verification sequence, compares whether the verification sequence is consistent with the next indication sequence, and judges whether the next indication sequence is in error or not;
when the two instruction sequences are consistent, storing the next instruction sequence as a current instruction sequence of a state machine so as to indicate the state of the state machine;
And when the indication sequences are inconsistent, performing error correction operation on the next indication sequence based on the verification sequence, and storing the next indication sequence after error correction as a current indication sequence of a state machine so as to indicate the state of the state machine.
Optionally, the method for encoding the state sequence by using a preset convolution method to obtain the indication sequence includes:
dividing all code elements in the state sequence into at least two code element groups from the first bit in sequence and arranging the code element groups in sequence, wherein the number of the code elements in each code element group is a first preset value;
sequentially acquiring each code element group of the state sequence, and determining a constraint sequence corresponding to the currently acquired code element group when each code element group is acquired, wherein the constraint sequence corresponding to the currently acquired code element group consists of a second preset value code element which is acquired immediately before the current code element group is acquired, and supplementing by using a code element 0 if the number of the code elements which are acquired immediately before the current code element group is acquired is smaller than the second preset value; then, performing exclusive OR operation on the currently acquired code element group and the corresponding constraint sequence to calculate a code sequence corresponding to the currently acquired code element group, wherein the number of code elements in the code sequence is a third preset value; and calculating the code sequence corresponding to each code element group of the state sequence, and combining each code sequence in turn to obtain the indication sequence corresponding to the state sequence.
Optionally, the state machine further includes a register, where the register is configured to perform viterbi decoding;
the method for decoding the next indication sequence by the register based on the preset convolution method by utilizing the viterbi decoding method to obtain the verification sequence comprises the following steps:
determining at least two input sequences, wherein the bit length of the input sequences is a first preset value, and the at least two input sequences comprise all sequences with the bit length of the first preset value;
the second step of respectively inputting the at least two input sequences into a register at the time t0 to determine at least two first input paths, enabling the register to obtain at least two first arrival states based on the first input paths, and determining the metric value of each first input path based on the next instruction sequence by using the preset convolution method;
thirdly, respectively inputting the at least two input sequences into the register at the time t0+1 for each first arrival state of the register to determine a plurality of second input paths, enabling the register to obtain a plurality of second arrival states based on the second input paths, and determining the measurement value of each second input path based on the next instruction sequence by using the preset convolution method;
Fourth, for each second arrival state of the register, respectively inputting the at least two input sequences into the register at time t0+2 to determine a plurality of third input paths, obtaining a plurality of third arrival states by the register based on the third input paths, and determining the measurement value of each third input path based on the next instruction sequence by using the preset convolution method; each third arrival state corresponds to at least two third input paths;
a fifth step of calculating a measurement accumulated value of each third input path corresponding to each third arrival state, wherein the measurement accumulated value is the sum of the measurement values of the third input paths of the third arrival states and the measurement values of all the input paths corresponding to the third input paths, and then selecting the path with the smallest measurement accumulated value corresponding to each third arrival state as a surviving path of each third arrival state, and deleting the input paths except the surviving paths;
and the fourth step and the fifth step are circularly executed until the register obtains a plurality of mth arrival states, the value of m is the same as the value of the group number of the code element group, the surviving paths corresponding to the mth arrival states are determined, the surviving path with the smallest measurement accumulated value in all surviving paths corresponding to the mth arrival states is determined to be the final surviving path, a decoding sequence is traced back based on the final surviving path, and the decoding sequence is determined to be the verification sequence.
Optionally, before decoding with the register, the method further comprises: acquiring the next indication sequence, dividing all code elements in the next indication sequence into at least two groups of code element sequences from the first bit in sequence, and sequencing the code element sequences in sequence, wherein the number of the code elements in each group of code element sequences is a third preset value;
and determining the metric value of each input path based on the next indication sequence by using the preset convolution method, wherein the method comprises the following steps:
encoding each input sequence input into a register at the time t0 by adopting a preset convolution method to obtain a first path sequence corresponding to each first input path, wherein the bit length of the first path sequence is a third preset value, and determining the inter-code distance value between each first path sequence and a first group of code element sequences and taking the inter-code distance value as the metric value of each first input path;
encoding each input sequence input into a register at the time t0+1 by adopting a preset convolution method to obtain a second path sequence corresponding to each second input path, wherein the bit length of the second path sequence is a third preset value, and determining the inter-code distance value between each second path sequence and a second group of code element sequences and taking the inter-code distance value as the measurement value of each second input path;
And the like to determine the corresponding metric value of each input path.
Optionally, the at least two input sequences include 2 A first preset value A sequence of inputs.
Optionally, the bit length of the next state sequence is the product of the group number of the code element group and a first preset value;
and, the bit lengths of the next indication sequence and the verification sequence are equal and are all (third preset value/first preset value) times of the bit length of the next state sequence.
Optionally, the first preset value is 1, the second preset value is 2, and the third preset value is 2.
Optionally, the method for performing error correction operation on the next indication sequence based on the verification sequence includes:
performing a flipping operation on a symbol in the next indication sequence that is different from the verification sequence; alternatively, the next indicator sequence is directly replaced with the verification sequence.
Optionally, the method further comprises: and in the process that the current indication sequence is stored in the state machine, performing real-time error checking on the current indication sequence based on the preset convolution method by utilizing a viterbi decoding method, and performing error correction operation on the current indication sequence when the current indication sequence is checked to be in error.
Optionally, the state sequence indicates the state by using a single hot code or gray code.
In summary, after the state sequences corresponding to the states are constructed, the error correction method for the sequences in the state machine provided by the invention encodes the state sequences by adopting a preset convolution method to obtain the indication sequences, and stores the indication sequences in the state machine for indicating the states of the state machine. And after the state machine determines the next indication sequence corresponding to the next state, firstly verifying whether the next indication sequence is wrong or not based on a preset convolution method by using a Viterbi decoding method, and when the next indication sequence is wrong, executing error correction operation on the next indication sequence, and then switching the state of the state machine based on the next indication sequence. Then in the present invention, since the indication sequence for indicating the state is a sequence obtained by using the convolutional encoding, it can be verified by the viterbi decoding method, and in the present invention, the next indication sequence is verified by using the viterbi decoding method before the state machine switches the state to the next state. That is, the present invention automatically performs error detection and error correction operation on the next indication sequence before the state machine switches the state to the next state, so that it can be ensured that the next indication sequence will not make an error so that it can correctly indicate the state, further ensuring that the state machine can correctly switch the state, and ensuring the performance of the state machine.
Drawings
Fig. 1 is a flow chart of a method for correcting errors of sequences in a state machine according to the present embodiment;
fig. 2-8 are schematic diagrams of decoding grids for viterbi decoding according to embodiments of the present invention.
Detailed Description
The error correction method for the sequence in the state machine according to the present invention is described in further detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flow chart of an error correction method for a state sequence of a state machine according to the present embodiment, as shown in fig. 1, the method may include:
step 100, a state sequence for indicating different states is constructed in a state machine, each state sequence is encoded by a preset convolution method to obtain different indication sequences, and the indication sequences are stored in the state machine.
Wherein the state machine has at least two states, for example, the state machine may have an initialized state, an idle state, and the like. And the state machine can correspondingly construct a state sequence for different states based on a preset rule, for example, the state sequence can be constructed in a single-hot coding mode or a gray coding mode, and the state sequence can be a binary sequence.
Further, in this embodiment, the state machine may include a register, where the register is configured to convolutionally encode each state sequence by using a preset convolution method to obtain at least two indication sequences and store the two indication sequences, so that the state of the state machine is indicated by the indication sequences subsequently.
Meanwhile, the state sequence is subjected to convolution coding to obtain the indication sequence, so that the indication sequence can be verified correspondingly by using a Viterbi decoding method.
In this embodiment, the convolution method may specifically be an (n, k, v) convolution method, where k represents the number of bits of a symbol input to the register each time when the convolution code is performed, k may be preset to a first preset value, v represents a constraint length of the register each time when the convolution code is performed, v may be preset to a second preset value, n represents the number of bits of a symbol output by the register each time after the symbol is input to the register, and n may be preset to a third preset value.
Based on this, a method for performing convolutional encoding on a state sequence by using a preset convolution method to obtain an indication sequence by using a register in this embodiment is specifically described, and the encoding method specifically may include the following steps:
Step one, all code elements in the state sequence are divided into at least two code element groups from the first bit in sequence and are arranged in sequence, and the number of the code elements in each code element group is a first preset value.
By way of example, taking the preset convolution method as the (2, 1, 2) convolution method as an example (the following example is also taken as an example of the (2, 1, 2) convolution method), the first preset value is 1, the second preset value is 2, the third preset value is 2, and the state sequence to be encoded is 11011. Then in step one, the state sequence 11011 is divided sequentially from the first bit into five symbol groups, each of which includes 1 symbol. The five groups of code tuples are respectively: the first symbol group "1", the second symbol group "1", the third symbol group "0", the fourth symbol group "1", and the fifth symbol group "1".
Sequentially acquiring each code element group of the state sequence, determining a constraint sequence corresponding to the currently acquired code element group when each code element group is acquired, and performing exclusive OR operation on the currently acquired code element group and the corresponding constraint sequence to calculate a code sequence corresponding to the currently acquired code element group, wherein the number of code elements in the code sequence is a third preset value; and calculating the code sequence corresponding to each code element group of the state sequence, and combining each code sequence in turn to obtain the indication sequence corresponding to the state sequence.
In this embodiment, the constraint sequence corresponding to the current acquired symbol group mainly includes a second preset value of symbols acquired immediately before the current symbol group is acquired, and if the number of symbols acquired immediately before the current symbol group is acquired is less than the second preset value, the constraint sequence is supplemented with symbol 0.
For example, since the second preset value is 2, the bit length of the constraint sequence is the second preset value of 2. On this basis, if the register sequentially acquires the first symbol group "1", the second symbol group "1", the third symbol group "0", the fourth symbol group "1", and the fifth symbol group "1". Then when the currently acquired symbol set is the first symbol set "1", the constraint sequence corresponding to the first symbol set "1" should be composed of 2 symbols acquired immediately before the first symbol set "1" is acquired. Since no symbol is acquired before the first symbol group "1" is acquired, that is, the number of acquired symbols before the first symbol group is acquired is 0 and less than the second preset value 2, the symbol 0 should be used for supplementing. Whereby the first constraint sequence corresponding to the first symbol group "1" should be "00".
Similarly, when the currently acquired symbol set is the second symbol set "1", the second constraint sequence corresponding to the second symbol set "1" should be formed by 2 symbols acquired immediately before the second symbol set "1" is acquired. Wherein, since the symbols acquired before the second symbol group is acquired only include the first symbol group "1", the number of which is 1 and less than 2, the symbol 0 should be used for supplementing. Thus, the second constraint sequence corresponding to the second symbol group "1" should consist of the first symbol group "1" and symbol 0, i.e., the second constraint sequence should be "10".
And when the currently acquired symbol group is a third symbol group "0", the third constraint sequence corresponding to the third symbol group "0" should be composed of 2 symbols acquired immediately before the third symbol group is acquired. Wherein, the symbols immediately before the third symbol group "0" is acquired include the first symbol group "1" and the second symbol group "1", the number of which is 2 and is not less than the second preset value, so that the symbol 0 need not be used for supplementing. Whereby the third constraint sequence corresponding to the third symbol group "0" should be "11".
And so on, determining the constraint sequence corresponding to each symbol group. Wherein, table 1 is a table of correspondence between symbol groups and constraint sequences provided in an embodiment of the present invention.
TABLE 1
As shown in table 1, the fourth constraint sequence corresponding to the fourth symbol group is "01", and the fifth constraint sequence corresponding to the fifth symbol group is "10".
And after determining the constraint sequence corresponding to the currently acquired code element group, performing exclusive OR operation on the currently acquired code element group and the corresponding constraint sequence to calculate a code sequence corresponding to the currently acquired code element group, wherein the number of code elements in the code sequence is a third preset value.
It should be noted that, for different preset convolution methods, the execution methods of the exclusive or operation are also different. In this embodiment, the description is mainly directed to a specific operation method of the exclusive or operation adopted when the preset convolution method is the (2, 1, 2) convolution method, where the operation method specifically may be: performing exclusive-or operation on the code element in the currently acquired code element group and two code elements in the corresponding constraint sequence to obtain a first numerical value, performing exclusive-or operation on the code element in the currently acquired code element group and a second code element in the corresponding constraint sequence to obtain a second numerical value, and combining the first numerical value and the second numerical value to form a coding sequence.
For example, if the currently acquired symbol group is a first symbol group "1", it is determined that a first constraint sequence corresponding to the first symbol group is "00", so that the method for performing an exclusive-or operation on the first symbol group "1" and the first constraint sequence "00" to obtain a first coding sequence includes: exclusive-or operation is performed on the first symbol group "1" and two symbols in the first constraint sequence "00": 1 ∈0 ∈0=1, then the first value corresponding to the first symbol group should be "1"; exclusive-or the first symbol group "1" with the second symbol "0" in the first constraint sequence "00": 1 +.0=1, the second value corresponding to the first symbol group should be "1". Thus, the first code sequence corresponding to the first symbol group "1" can be determined as "11".
And similarly, calculating the code sequence corresponding to each code element group of the state sequence, and combining each code sequence in turn to obtain the indication sequence corresponding to the state sequence. Wherein, table 2 is a corresponding relation diagram of the symbol group, the constraint sequence and the coding sequence provided by the embodiment of the invention.
TABLE 2
As shown in table 2, the second code sequence corresponding to the second symbol group is "01", the third code sequence corresponding to the third symbol group is "01", the fourth code sequence corresponding to the fourth symbol group is "00", and the fifth code sequence corresponding to the fifth symbol group is "01".
Thereafter, the first coding sequence 11, the second coding sequence 01, the third coding sequence 01, the fourth coding sequence 00, and the fifth coding sequence 01 may be combined to obtain an indication sequence 1101010001.
Thus, the state sequence can be convolutionally encoded, and a corresponding instruction sequence can be obtained. As can be seen from the foregoing, in this embodiment, the bit length of the state sequence is specifically the product of the number of the symbol groups and the first preset value. And, the indication sequence is (third preset value/first preset value) times the bit length of the state sequence.
For example, taking the state sequence 11011 as an example, and the preset convolution method is a (2, 1, 2) convolution encoding method, where the bit length of the state sequence 11011 is 5, the bit length of the indication sequence 1101010001 is 10, and the bit length of the indication sequence is a third preset value/a first preset value=2/1=2 times the bit length of the state sequence.
Step 200, a state machine obtains an input signal, determines a next state sequence corresponding to a next state of the state machine based on the input signal, obtains a next indication sequence corresponding to the next state sequence, decodes the next indication sequence based on the preset convolution method by using a viterbi decoding method to obtain a verification sequence, compares whether the verification sequence is consistent with the next indication sequence, judges whether the next indication sequence is in error, and executes step 300 when the verification sequence is consistent with the next indication sequence; when there is no agreement, step 400 is performed.
The state machine may receive an input signal sent by the external device, where the input signal is used to indicate a next state of the state machine, and the state machine may determine the next state based on the input signal, and obtain a next indication sequence corresponding to the next state, so as to implement switching of the state machine based on the next indication sequence.
And, it should be noted that, in this embodiment, the next instruction sequence acquired by the state machine in this step 200 is substantially stored in the state machine for a period of time. At this time, if the next indication sequence is in error due to interference during the stored period of time, the next indication sequence acquired in step 200 should be the indication sequence after error.
For example, assume that the predetermined indication sequence obtained by encoding the state sequence for a certain state in the above step 100 is 1101010001, and that the predetermined indication sequence 1101010001 is interfered when stored in the state machine, so that the predetermined indication sequence is changed to 1101011001 by error. If the state machine determines that the next state of the state machine is the state corresponding to the predetermined instruction sequence based on the input signal, the next instruction sequence acquired in step 200 should be the predetermined instruction sequence 1101011001 stored in the state machine at the current time, so that the next instruction sequence acquired by the state machine is not the correct instruction sequence, but is the wrong instruction sequence, and cannot correctly indicate the corresponding state.
Therefore, in this embodiment, after the state machine determines the next state and obtains the next instruction sequence corresponding to the next state, the register in the state machine decodes the next instruction sequence based on the preset convolution method by using the viterbi decoding method to obtain the verification sequence, and determines whether the next instruction sequence is correct by using the verification sequence, so as to ensure that the state machine can be correctly switched to the next state subsequently.
It should be noted that, in this embodiment, after the state machine acquires the next indication sequence, all symbols in the next indication sequence need to be divided into at least two groups of symbol sequences from the first bit and arranged in sequence, so that the next indication sequence can be decoded based on the multiple groups of symbol sequences. The number of code elements in each group of code element sequences is a third preset value.
For example, all the symbols in the acquired next indication sequence 1101011001 may be sequentially divided into at least two groups of symbol sequences from the first bit, where the number of symbols in each group of symbol sequences is a third preset value. The third preset value is 2, taking the preset convolution method as the (2, 1, 2) convolution method as an example for explanation. At this time, the currently stored next indication sequence 1101011001 can be divided into five sets of symbol sequences, and the number of symbols in each set of symbol sequences is 2. Based on this, table 3 is a correspondence table between an indication sequence and a plurality of groups of symbol sequences provided in the embodiment of the present invention.
TABLE 3 Table 3
As shown in table 3, the five sets of symbol sequences corresponding to the next indicator sequence 1101011001 are respectively: the first set of symbol sequences "11", the second set of symbol sequences "01", the third set of symbol sequences "01", the fourth set of symbol sequences "10", and the fifth set of symbol sequences "01". In this way, viterbi decoding may be subsequently performed based on the first-fifth set of symbol sequences to verify whether the next indicator sequence is correct.
Further, fig. 2 to fig. 8 are schematic diagrams of decoding grids of viterbi decoding according to an embodiment of the present invention, based on which a method for decoding a next instruction sequence based on the preset convolution method by using a viterbi decoding method in a register with reference to fig. 2 and fig. 8 is described in detail. The following description also uses the preset convolution method (2, 1, 2), that is, the first preset value is 1, the second preset value and the third preset value are 2 as examples, and the decoding method specifically may include:
the method comprises the steps of determining at least two input sequences, wherein the bit length of the input sequences is a first preset value, and the at least two input sequences comprise all sequences with the bit length of the first preset value.
It should be noted that, for the sequences in the state machine, each symbol value is only "0" or "1", and based on this, since the sequence with the bit length of the first preset value includes the first preset value symbols, all the sequences with the bit length of the first preset value should include 2 A first preset value A sequence of inputs.
Specifically, when the first preset value is 1, all sequences with bit length of 1 should include 2 1 Group=2, "0" and "1", respectively, whereby it can be determined that the at least two input sequences include "0" and "1".
And when the first preset value is 2, all sequences with bit length of 2 should be comprised of 2 2 Set=4, including "00", "01", "10" and "11", respectively, then the at least two input sequences include "00", "01", "10" and "11" at this time.
And a second step of respectively inputting the at least two input sequences into a register at the time t0 to determine at least two first input paths, enabling the register to obtain at least two first arrival states based on the first input paths, and determining the metric value of each first input path based on the next instruction sequence by using the preset convolution method.
In this embodiment, when the preset convolution method is (2, 1, 2), the first preset value is 1, and the at least two input sequences specifically include a first input sequence "0" and a second input sequence "1". Based on this, a first input sequence "0" and a second input sequence "1" are input to the register at time t0, and two first input paths may be determined, where the first input paths correspond to the first input sequence "0" and the first input paths correspond to the second input sequence "1" respectively.
Then referring to fig. 2, it is assumed that the register has an initial arrivalState s0, and, in this embodiment, a first input sequence "0" and a second input sequence "1" are input for the arrival state s0 at time t0 to obtain first input paths A1 and A2, respectively, so that the register obtains two first arrival states s 1 0 and s 1 2。
In fig. 2 and the following fig. 3 to 8, the dashed line is mainly used to indicate the input path corresponding to the input of the first input sequence "0", and the solid line is mainly used to indicate the input path corresponding to the input of the second input sequence "1".
And further, after determining the first input paths, determining the metric value of each first input path based on the next indication sequence by using the preset convolution method, and specifically, the method for determining the metric value of the first input path includes:
and a first substep, encoding each input sequence input into the register at the time t0 by adopting a preset convolution method to obtain a first path sequence corresponding to each first input path, wherein the bit length of the first path sequence is a third preset value.
It should be noted that, the register may encode each input sequence by using the preset convolution method described in step 100. Specifically, the register may determine a second preset value of symbols acquired immediately before the input sequence currently acquired to determine the constraint sequence, where if the number of symbols acquired by the register before the current time is less than the second preset value, the symbols 0 are used for supplementing.
And performing exclusive OR operation based on the currently acquired input sequence and the corresponding constraint sequence to obtain a first path sequence. Specifically, an exclusive-or operation may be performed on the symbol in the currently acquired input sequence and two symbols in the corresponding constraint sequence to obtain a third value, and an exclusive-or operation may be performed on the symbol in the currently acquired input sequence and the second symbol in the corresponding constraint sequence to obtain a fourth value, and then the third value and the fourth value are combined to form the first path sequence.
For example, when the first input sequence "0" is input into the register at time t0, since no symbol is input into the register before time t0, the number of symbols input into the register before time t0 is 0 and less than 2, and thus it is necessary to supplement with symbol "0". It may be determined that the constraint sequence corresponding to the first input sequence "0" in the register at the time t0 should be "00", that is, the constraint sequence corresponding to the first input path A1 is "00".
Then, an exclusive or operation may be performed on two symbols in a constraint sequence "00" corresponding to the first input path A1 and symbol "0" in the first input sequence input to the register at time t 0: 0 +.0 #, 0=0, then the third value corresponding to the first input path A1 should be "0". And exclusive-or operation is performed on a second symbol "0" in a constraint sequence of "00" corresponding to the first input path A1, which is a symbol "0" in the first input sequence inputted into the register at the time t 0: 0 ∈0=0, the fourth value corresponding to the first input path A1 should be "0". Thus, the first path sequence corresponding to the first input path A1 can be determined to be "00".
Similarly, the first path sequence corresponding to the second input path A2 may be calculated as "11".
And a second sub-step of determining the inter-code distance value between the first path sequence corresponding to each first input path and the first group of code element sequences and taking the inter-code distance value as the metric value of each first input path.
The inter-code distance value mainly refers to the number of different code elements between the first path sequence and the first group of code element sequences.
For example, for the first path sequence "00" and the first group of symbol sequences "11" corresponding to the first input path A1 (as shown in table 3), the number of different symbols between the two is 2, and then the metric value of the first input path A1 should be 2. And for the first path sequence "11" and the first group of symbol sequences "11" corresponding to the first input path A2, the number of different symbols between the first path sequence "11" and the first group of symbol sequences "11" is 0, and then the metric value of the first input path A1 should be 0.
Thus, the metric value corresponding to each first input path can be determined.
In addition, in the embodiment, in fig. 2 to 3, each input path is marked with a path sequence and a metric value corresponding to the input path. The numerical value located on the input path and located in the bracket is a measurement value of the input path, and the numerical value located outside the bracket is a path sequence corresponding to the input path.
For example, as shown in fig. 2, a value 2 located on the first input path A1 and located in a bracket is a measurement value of the first input path A1, and a value 00 located on the first input path A1 and located outside the bracket is a first path sequence corresponding to the first input path A1. Similarly, as can be seen from fig. 2, the metric value of the first input path A2 is 0, and the first path sequence corresponding to the first input path A2 is 11.
And thirdly, respectively inputting the at least two input sequences into the register at the time t0+1 for each first arrival state of the register to determine a plurality of second input paths, enabling the register to obtain a plurality of second arrival states based on the second input paths, and determining the measurement value of each second input path based on the next instruction sequence by using the preset convolution method.
Wherein, as shown in FIG. 2, for the first arrival state s 1 The 0 input first input sequence '0' corresponds to a second input path B1, and the register is caused to obtain a second arrival state s based on the second input path B1 2 0. For the first arrival state s 1 The 0 input second input sequence "1" corresponds to a second input path B2, and the register is caused to obtain a second arrival state s based on the second input path B2 2 2. For the first arrival state s 1 2 input of the first input sequence "0" corresponds to the second input path B3, and the register is caused to obtain the second arrival state s based on the second input path B3 2 1. For the first arrival state s 1 2 input of the second input sequence "1" corresponds to the secondAn input path B4, and a second arrival state s of the register based on the second input path B4 2 3。
Further, after determining the second input paths, the method for determining the metric value of each second input path based on the next indication sequence by using the preset convolution method may include:
and a third substep, encoding each input sequence input into the register at the time t0+1 by adopting a preset convolution method to obtain a second path sequence corresponding to each second input path, wherein the bit length of the second path sequence is a third preset value.
The method for encoding each input sequence input into the register at time t0+1 based on the preset convolution method to obtain the second path sequence is similar to the first sub-step in the second step.
The second path sequence corresponding to the second input path B1 is calculated as an example.
As shown in fig. 2, the second input path B1 corresponds to a first input path A1 before the current time, where the first input path A1 is used to instruct to input a first input sequence "0" into the register. As can be seen from this, the number of symbols input to the register before time t0+1 is 0, which is 1 and smaller than the second preset value 2, and therefore it is necessary to supplement the symbol with "0". It may be determined that the constraint sequence corresponding to the first input sequence "0" in the register at time t0+1 should be "00", that is, the constraint sequence corresponding to the second input path B1 is "00".
Then, an exclusive or operation may be performed on two symbols in a constraint sequence "00" corresponding to the second input path B1 and symbol "0" in the first input sequence input to the register at time t0+1: 0 +.0 × 0 × 0=0, then the third value corresponding to the second input path B1 should be "0". And exclusive-or operation is performed on a second symbol "0" in a constraint sequence of "00" corresponding to a symbol "0" in the first input sequence inputted to the register at a time t0+1 and a second input path B1: 0 +.0=0, the fourth value corresponding to the second input path B1 should be "0". Thus, the second path sequence corresponding to the second input path B1 can be determined to be "00".
With this, the second path sequence corresponding to the second input path B2 may be calculated as "11", the second path sequence corresponding to the second input path B3 may be calculated as "10", and the second path sequence corresponding to the second input path B4 may be calculated as "01" (as may be known with reference to fig. 2).
And a fourth sub-step of determining the inter-code distance value between the second path sequence corresponding to each second input path and the second group of code element sequences and taking the inter-code distance value as the measurement value of each second input path.
The method for determining the metric value of the second input path is similar to the method for determining the metric value of the first input path in the second substep, and the embodiments of the present invention are not described herein.
And, as shown in fig. 2, the metric value of the second input path B1 is 1, the metric value of the second input path B2 is 1, the metric value of the second input path B3 is 2, and the metric value of the second input path B4 is 0.
From this, a metric value for each second input path can be determined.
Fourth, for each second arrival state of the register, the at least two input sequences are respectively input into the register at time t0+2 to determine a plurality of third input paths, the register is enabled to obtain a plurality of third arrival states based on the third input paths, and the measurement value of each third input path is determined based on the next instruction sequence by using the preset convolution method.
Wherein, as shown in FIG. 2, for the second arrival state s 2 The 0 input first input sequence "0" corresponds to a third input path C1, and the register is made to be in a third arrival state s based on the third input path C1 3 0. For the second arrival state s 2 The 0 input second input sequence "1" corresponds to the second input path C2 and causes the register to be in the third arrival state s based on the third input path C2 3 2. Thus, the determination of theThe third input paths include eight third input paths C1, C2, C3, C4, C5, C6, C7, and C8, respectively.
And wherein the register is brought to a third arrival state s based on third input paths C1 and C3 3 0, based on the third input paths C5 and C7, to bring the register to a third arrival state s 3 1, based on the third input paths C2 and C4, bringing the register into a third arrival state s 3 2, based on the third input paths C6 and C8, putting the register in a third arrival state s 3 3. It can be seen that there are two input paths entering each third arrival state.
And after determining the third input paths, calculating third path sequences of the third input paths corresponding to the third arrival states, and taking the inter-code distance values between the third path sequences corresponding to the third input paths and the third group of code element sequences as the measurement values of the third path sequences.
The method for determining the third path sequence of each third input path and the metric value corresponding to each third input path is similar to the method for determining the second path sequence and the metric value of the second input path in the third step, and this embodiment is not described herein.
As can be seen from fig. 2, the third path sequence corresponding to the third input path C1 is "00", and the metric value is 1; the third path sequence corresponding to the third input path C2 is 11, and the metric value is 1; the third path sequence corresponding to the third input path C3 is 11, and the metric value is 1; the third input path C4 corresponds to a third path sequence of "00" and a metric value of 1. And the third path sequence corresponding to the third input path C5 is 10, and the measurement value is 2. The third input path C6 corresponds to a third path sequence of "01" and a metric value of 0. The third input path C7 corresponds to a third path sequence of "01" and a metric value of 0. And the third path sequence corresponding to the third input path C8 is 10, and the measurement value is 2.
And fifthly, calculating a measurement accumulated value of each input path corresponding to each third arrival state, wherein the measurement accumulated value is the sum of measurement values of the third input paths of the third arrival states and all input paths corresponding to the third input paths, and then selecting a path with the smallest measurement accumulated value corresponding to each third arrival state as a surviving path of each third arrival state, and deleting input paths except the surviving paths.
As can be seen from fig. 2 to 8, after at least two input sequences are input into the register at time t0+2 and later, there are two input paths entering each arrival state, and at this time, the input paths entering each arrival state need to be screened to preserve a surviving path, so that a correct verification sequence can be obtained based on the decoding of the input paths.
For example, refer to FIG. 2 to calculate a third arrival state s 3 A metric accumulation value of 0 is illustrated as an example. Wherein for the third arrival state s 3 0 corresponds to two third input paths C1 and C3. All input paths corresponding to the third input path C1 include: the second input path B1 and the first input path A1, the second input path B1, and the third input path C1 constitute path one: s0→s 1 0→s 2 0→s 3 0, the metric accumulated value of the path one is: metric value 2 of first input path A1 + metric value 1 of second input path B1 + metric value 1=4 of third input path C1. And all input paths corresponding to the third input path C3 include: the first input path A2 and the second input path B3, and the first input path A2, the second input path B3, and the third input path C3 constitute a path two: s0→s 1 2→s 2 1→s 3 0, the accumulated value of the metrics corresponding to the second path is: metric value 0 of the first input path A2 + metric value 2 of the second input path B3 + metric value 1=3 of the third input path C3, less than metric value 4 of path one. Then path two s 0-s 1 2→s 2 1→s 3 0 is determined as a third arrival state s 3 Surviving path of 0.
Similarly, the third arrival states s are calculated 3 1、s 3 2、s 3 3 and deleting the input paths outside the survivor paths.
Wherein fig. 3 is a decoding trellis diagram of an input path excluding a surviving path for a third arrival state. As shown in FIG. 3, the third arrival state s 3 1 is s 0-s 1 2→s 2 3→s 3 1, a step of; the third arrival state s 3 2 is s 0-s 1 2→s 2 1→s 3 2; the third arrival state s 3 3 is s 0-s 1 2→s 2 3→s 3 3。
And similarly, circularly executing the fourth step and the fifth step until the register obtains a plurality of mth arrival states, wherein the value of m is the same as the value of the group number of the code element group, the surviving paths corresponding to the mth arrival states are determined, the surviving path with the smallest measurement accumulated value in all surviving paths corresponding to the mth arrival states is determined as a final surviving path, a decoding sequence is traced back based on the final surviving sequence, and the decoding sequence is determined as the verification sequence.
For example, referring to the number of symbol groups in step 100 being 5, the m may be 5. And based on this, by cycling the fourth and fifth steps a plurality of times to determine a plurality of fourth input paths and fourth arrival states at time t0+3, and determine surviving paths corresponding to the respective fourth arrival states. And determining a plurality of fifth input paths and fifth arrival states at time t0+4, determining surviving paths corresponding to the fifth arrival states, and determining final surviving paths to trace back a decoding sequence based on the final surviving paths to serve as a verification sequence.
Specifically, referring to fig. 4, fourth input paths D1, D2, D3, D4, D5, D6, D7, and D8 are corresponding at time t0+3. And, based on the fourth input paths D1 and D3, causing the register to be in a fourth arrival state s 4 0, based on the fourth input paths D5 and D7, to bring the register to a fourth arrival state s 4 1, based on the fourth input paths D2 and D4, to cause the register to be locatedIn the fourth arrival state s 4 2, based on the fourth input paths D6 and D8, putting the register in a fourth arrival state s 4 3。
And, referring to FIG. 5, the fourth arrival state s 4 The surviving path corresponding to 0 is s 0-s 1 2→s 2 3→s 3 1→s 4 0; the fourth arrival state s 4 1 is s 0-s 1 2→s 2 1→s 3 2→s 4 1, a step of; the fourth arrival state s 4 2 is s 0-s 1 2→s 2 3→s 3 1→s 4 2; the fourth arrival state s 3 3 is s 0-s 1 2→s 2 3→s 3 3→s 4 3。
Similarly, referring to fig. 6, at time t0+4, fifth input paths E1, E2, E3, E4, E5, E6, E7, and E8 are corresponding. And, based on the fifth input paths E1 and E3, causing the register to be in a fifth arrival state s 5 0, based on the fifth input paths E5 and E7, to bring the register to a fifth arrival state s 5 1, based on the fifth input paths E2 and E4, putting the register in a fifth arrival state s 5 2, based on the fifth input paths E6 and E8, putting the register in a fifth arrival state s 5 3。
And, further, referring to FIG. 7, the fifth arrival state s 5 The surviving path corresponding to 0 is s 0-s 1 2→s 2 3→s 3 1→s 4 0→s 5 0, and the fifth arrival state s 5 Surviving paths s0→s corresponding to 0 1 2→s 2 3→s 3 1→s 4 0→s 5 The metric accumulation value of 0 is: metric value 0 of the first input path A2 + metric value 0 of the second input path B4 + metric value 0 of the third input path C2 + metric value 1 of the fourth input path D3 + metric value 1=2 of the fifth input path E1. The fifth arrival state s 5 1 is s 0-s 1 2→s 2 3→s 3 3→s 4 3→s 5 1 and the corresponding metric accumulation value is 2. The fifth stepReach state s 5 2 is s 0-s 1 2→s 2 3→s 3 1→s 4 0→s 5 2, and the corresponding metric accumulation value is 2. The fifth arrival state s 5 3 is s 0-s 1 2→s 2 3→s 3 1→s 4 2→s 5 3 and the corresponding metric accumulation value is 1.
Then a fifth arrival state s can be determined 5 3, the fifth arrival state s can be set to be the smallest value of the accumulated metrics of the surviving paths 5 3 are determined to be the final surviving paths, as shown in FIG. 8, which are s0→s 1 2→s 2 3→s 3 1→s 4 2→s 5 3。
Thereafter, based on the final surviving path s0→s 1 2→s 2 3→s 3 1→s 4 2→s 5 3 backtracking a decoding sequence and determining the decoding sequence as the verification sequence.
Specifically, the survivor sequences corresponding to the input sequences in the final survivor sequences may be sequentially combined to obtain the decoding sequence. Specifically, referring to fig. 8, the coding sequence should be: the sequence 1101010001 composed of the first survivor sequence 11 corresponding to the first input path A2, the second survivor sequence 01 corresponding to the second input path B4, the third survivor sequence 01 corresponding to the third input path C7, the fourth survivor sequence 00 corresponding to the fourth input path D4, and the fifth survivor sequence 01 corresponding to the fifth input path E1 is taken as a decoding sequence, that is, the verification sequence is 1101010001. Wherein the bit length of the verification sequence is equal to the bit degree of the indication sequence.
Thereafter, it may be compared whether the verification sequence 1101010001 and the obtained next state indication sequence 1101011001 are consistent, so as to verify whether the currently stored next state indication sequence is erroneous, and when they are consistent, step 300 is performed, otherwise step 400 is performed.
From the foregoing, it can be seen that the viterbi decoding method is mainly used for exhausting all possible sequences, and determining the sequence closest to the sequence to be verified in all possible sequences as the decoded sequence to verify the sequence to be verified.
And 300, storing the indication sequence corresponding to the next state as a current state indication sequence of a state machine so as to indicate the state of the state machine.
When the next indication sequence is consistent with the verification sequence, it is indicated that the next indication sequence is not in error, and the indication sequence corresponding to the next state can be stored as a current state indication sequence of a state machine, so that the state of the state machine can be correctly switched to the next state.
And 400, executing error correction operation on the indication sequence corresponding to the next state based on the verification sequence, and storing the error corrected sequence as a current state indication sequence to indicate the current state of the state machine.
When the next indication sequence is inconsistent with the verification sequence, indicating that an error occurs in the next indication sequence in the storage process, performing error correction operation on the indication sequence corresponding to the next state based on the verification sequence. Specifically, in this embodiment, the method for performing error correction operation on the indication sequence corresponding to the next state based on the verification sequence includes: and executing the turning operation on a symbol which is different from the verification sequence in the indication sequence corresponding to the next state, or directly replacing the indication sequence corresponding to the next state by the verification sequence.
The error corrected sequence may then be stored as a current state indication sequence for the state machine so that the state of the state machine can be correctly switched to the next state.
In addition, it should be noted that, in this embodiment, after the next instruction sequence is stored as the currently stored instruction sequence, and before the state machine switches states next time, the register in the state machine further decodes the currently stored instruction sequence in real time by using the viterbi decoding method based on a preset convolution method, so as to determine whether the currently stored instruction sequence is in error, and when the currently stored instruction sequence is in error, performs an error correction operation. Thereby ensuring that the state machine can correctly indicate the state in real time.
In summary, after the state sequences corresponding to the states are constructed, the error correction method for the sequences in the state machine provided by the invention encodes the state sequences by adopting a preset convolution method to obtain the indication sequences, and stores the indication sequences in the state machine for indicating the states of the state machine. And after the state machine determines the next indication sequence corresponding to the next state, firstly verifying whether the next indication sequence is wrong or not based on a preset convolution method by using a Viterbi decoding method, and when the next indication sequence is wrong, executing error correction operation on the next indication sequence, and then switching the state of the state machine based on the next indication sequence. Then in the present invention, since the indication sequence for indicating the state is a sequence obtained by using the convolutional encoding, it can be verified by the viterbi decoding method, and in the present invention, the next indication sequence is verified by using the viterbi decoding method before the state machine switches the state to the next state. That is, the present invention automatically performs error detection and error correction operation on the next indication sequence before the state machine switches the state to the next state, so that it can be ensured that the next indication sequence will not make an error so that it can correctly indicate the state, further ensuring that the state machine can correctly switch the state, and ensuring the performance of the state machine.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, the description is relatively simple because of corresponding to the method disclosed in the embodiment, and the relevant points refer to the description of the method section.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A method of error correction of a sequence in a state machine, the method comprising:
constructing state sequences for indicating different states in a state machine, and adopting a preset convolution method to encode each state sequence to obtain different indication sequences and storing the indication sequences into the state machine, wherein the preset convolution method is an (n, k, v) convolution method;
the state machine obtains an input signal, determines a next state sequence corresponding to a next state of the state machine based on the input signal, obtains a next indication sequence corresponding to the next state sequence, decodes the next indication sequence based on the preset convolution method by using a viterbi decoding method to obtain a verification sequence, compares whether the verification sequence is consistent with the next indication sequence, and judges whether the next indication sequence is in error or not;
When the two instruction sequences are consistent, storing the next instruction sequence as a current instruction sequence of a state machine so as to indicate the state of the state machine;
and when the indication sequences are inconsistent, performing error correction operation on the next indication sequence based on the verification sequence, and storing the next indication sequence after error correction as a current indication sequence of a state machine so as to indicate the state of the state machine.
2. The method of error correction of a sequence in a state machine of claim 1, wherein the method of encoding the state sequence using a predetermined convolution method to obtain the indication sequence comprises:
dividing all code elements in the state sequence into at least two code element groups from the first bit in sequence and arranging the code element groups in sequence, wherein the number of the code elements in each code element group is a first preset value;
sequentially acquiring each code element group of the state sequence, and determining a constraint sequence corresponding to the currently acquired code element group when each code element group is acquired, wherein the constraint sequence corresponding to the currently acquired code element group consists of a second preset value code element which is acquired immediately before the current code element group is acquired, and supplementing by using a code element 0 if the number of the code elements which are acquired immediately before the current code element group is acquired is smaller than the second preset value; then, performing exclusive OR operation on the currently acquired code element group and the corresponding constraint sequence to calculate a code sequence corresponding to the currently acquired code element group, wherein the number of code elements in the code sequence is a third preset value; and calculating the code sequence corresponding to each code element group of the state sequence, and combining each code sequence in turn to obtain the indication sequence corresponding to the state sequence.
3. The method of error correction of a sequence in a state machine of claim 2, wherein the state machine further comprises a register for performing viterbi decoding;
the method for decoding the next indication sequence by the register based on the preset convolution method by utilizing the viterbi decoding method to obtain the verification sequence comprises the following steps:
determining at least two input sequences, wherein the bit length of the input sequences is a first preset value, and the at least two input sequences comprise all sequences with the bit length of the first preset value;
the second step of respectively inputting the at least two input sequences into a register at the time t0 to determine at least two first input paths, enabling the register to obtain at least two first arrival states based on the first input paths, and determining the metric value of each first input path based on the next instruction sequence by using the preset convolution method;
thirdly, respectively inputting the at least two input sequences into the register at the time t0+1 for each first arrival state of the register to determine a plurality of second input paths, enabling the register to obtain a plurality of second arrival states based on the second input paths, and determining the measurement value of each second input path based on the next instruction sequence by using the preset convolution method;
Fourth, for each second arrival state of the register, respectively inputting the at least two input sequences into the register at time t0+2 to determine a plurality of third input paths, obtaining a plurality of third arrival states by the register based on the third input paths, and determining the measurement value of each third input path based on the next instruction sequence by using the preset convolution method; each third arrival state corresponds to at least two third input paths;
a fifth step of calculating a measurement accumulated value of each third input path corresponding to each third arrival state, wherein the measurement accumulated value is the sum of the measurement values of the third input paths of the third arrival states and the measurement values of all the input paths corresponding to the third input paths, and then selecting the path with the smallest measurement accumulated value corresponding to each third arrival state as a surviving path of each third arrival state, and deleting the input paths except the surviving paths;
and the fourth step and the fifth step are circularly executed until the register obtains a plurality of mth arrival states, the value of m is the same as the value of the group number of the code element group, the surviving paths corresponding to the mth arrival states are determined, the surviving path with the smallest measurement accumulated value in all surviving paths corresponding to the mth arrival states is determined to be the final surviving path, a decoding sequence is traced back based on the final surviving path, and the decoding sequence is determined to be the verification sequence.
4. A method of error correction of a sequence in a state machine as claimed in claim 3, wherein prior to decoding with a register, the method further comprises: acquiring the next indication sequence, dividing all code elements in the next indication sequence into at least two groups of code element sequences from the first bit in sequence, and sequencing the code element sequences in sequence, wherein the number of the code elements in each group of code element sequences is a third preset value;
and determining the metric value of each input path based on the next indication sequence by using the preset convolution method, wherein the method comprises the following steps:
encoding each input sequence input into a register at the time t0 by adopting a preset convolution method to obtain a first path sequence corresponding to each first input path, wherein the bit length of the first path sequence is a third preset value, and determining the inter-code distance value between each first path sequence and a first group of code element sequences and taking the inter-code distance value as the metric value of each first input path;
encoding each input sequence input into a register at the time t0+1 by adopting a preset convolution method to obtain a second path sequence corresponding to each second input path, wherein the bit length of the second path sequence is a third preset value, and determining the inter-code distance value between each second path sequence and a second group of code element sequences and taking the inter-code distance value as the measurement value of each second input path;
And the like to determine the corresponding metric value of each input path.
5. The method for error correction of sequences in a state machine of claim 3, wherein said at least two input sequences comprise 2 A first preset value A sequence of inputs.
6. The method of error correction of a sequence in a state machine of claim 3, wherein a bit length of the next state sequence is a product of a group number of the symbol groups and a first preset value;
and, the bit lengths of the next indication sequence and the verification sequence are equal and are all (third preset value/first preset value) times of the bit length of the next state sequence.
7. A method of error correction of a sequence in a state machine as claimed in claim 2 or 3, characterized in that the first preset value is 1, the second preset value is 2 and the third preset value is 2.
8. The method of error correction of a sequence in a state machine of claim 1, wherein the method of performing an error correction operation on the next sequence of indications based on the verification sequence comprises:
performing a flipping operation on a symbol in the next indication sequence that is different from the verification sequence; alternatively, the next indicator sequence is directly replaced with the verification sequence.
9. The method of error correction of a sequence in a state machine of claim 1, further comprising: and in the process that the current indication sequence is stored in the state machine, performing real-time error checking on the current indication sequence based on the preset convolution method by utilizing a viterbi decoding method, and performing error correction operation on the current indication sequence when the current indication sequence is checked to be in error.
10. The method of error correction of a sequence in a state machine of claim 1, wherein the sequence of states indicates states by way of a one-hot code or gray code.
CN202010213889.7A 2020-03-24 2020-03-24 Error correction method for sequence in state machine Active CN111404560B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010213889.7A CN111404560B (en) 2020-03-24 2020-03-24 Error correction method for sequence in state machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010213889.7A CN111404560B (en) 2020-03-24 2020-03-24 Error correction method for sequence in state machine

Publications (2)

Publication Number Publication Date
CN111404560A CN111404560A (en) 2020-07-10
CN111404560B true CN111404560B (en) 2023-08-25

Family

ID=71431186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010213889.7A Active CN111404560B (en) 2020-03-24 2020-03-24 Error correction method for sequence in state machine

Country Status (1)

Country Link
CN (1) CN111404560B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8009773B1 (en) * 2008-04-04 2011-08-30 Hellosoft India Pvt. Ltd. Low complexity implementation of a Viterbi decoder with near optimal performance
CN102386935A (en) * 2011-11-03 2012-03-21 中国科学院深圳先进技术研究院 Viterbi decoding method and Viterbi decoder
CN109462407A (en) * 2018-12-13 2019-03-12 锐捷网络股份有限公司 Viterbi coding method, equipment and storage medium

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8904266B2 (en) * 2010-08-10 2014-12-02 Nxp, B.V. Multi-standard viterbi processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8009773B1 (en) * 2008-04-04 2011-08-30 Hellosoft India Pvt. Ltd. Low complexity implementation of a Viterbi decoder with near optimal performance
CN102386935A (en) * 2011-11-03 2012-03-21 中国科学院深圳先进技术研究院 Viterbi decoding method and Viterbi decoder
CN109462407A (en) * 2018-12-13 2019-03-12 锐捷网络股份有限公司 Viterbi coding method, equipment and storage medium

Also Published As

Publication number Publication date
CN111404560A (en) 2020-07-10

Similar Documents

Publication Publication Date Title
US8370730B2 (en) Soft output viterbi detector with error event output
KR100187964B1 (en) Viterbi decoding method and apparatus with balance among memory and processing requirements
TWI785309B (en) Multi-mode channel coding
JP4806673B2 (en) Decoding device and decoding method
CN111858142A (en) Data processing method and device, electronic equipment and storage medium
CN101431388A (en) Method and apparatus of decoding encoded data frame
KR100853139B1 (en) Transport format detecting apparatus and method
US7277507B2 (en) Viterbi decoder
CN110806948B (en) Data verification method and device
CN111404560B (en) Error correction method for sequence in state machine
US5887007A (en) Viterbi decoding method and viterbi decoding circuit
JP2008118327A (en) Viterbi decoding method
KR20060086676A (en) Viterbi decoder for executing trace-back work in parallel, and, method thereof
CN110492889B (en) Encoding and decoding method, encoding and decoding device and processor for detecting and correcting two-bit errors
JP5169771B2 (en) Decoder and decoding method
JPWO2005117272A1 (en) Viterbi decoding apparatus and Viterbi decoding method
US20070201586A1 (en) Multi-rate viterbi decoder
US7263653B2 (en) Algorithm for a memory-based Viterbi decoder
CN113098811A (en) Demodulation and decoding method and device for GFSK signal
US8181098B2 (en) Error correcting Viterbi decoder
JP3272173B2 (en) Error correction code / decoding device
JP4047697B2 (en) Viterbi decoder
CN113098532B (en) Low-delay low-complexity polar code decoding method and system
JP2591332B2 (en) Error correction decoding device
KR100431162B1 (en) coderate detection circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant