CN111402774B

CN111402774B - Shift register unit and driving method thereof, gate drive circuit and display device

Info

Publication number: CN111402774B
Application number: CN202010230119.3A
Authority: CN
Inventors: 冯思林; 李红敏; 唐锋景
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2020-03-27
Filing date: 2020-03-27
Publication date: 2022-09-09
Anticipated expiration: 2040-03-27
Also published as: CN111402774A

Abstract

The invention provides a shift register unit, comprising: an input sub-circuit configured to charge a pull-up node; an output sub-circuit configured to transmit a clock signal to an output terminal; a reset sub-circuit configured to reset the pull-up node and the output terminal; a first control sub-circuit configured to control a potential of the first pull-down node; a first noise reduction sub-circuit configured to reduce noise of the pull-up node and the output terminal according to a potential of the first pull-down node; a second control sub-circuit configured to control a potential of the second pull-down node; a second noise reduction sub-circuit configured to reduce noise of the pull-up node and the output terminal according to a potential of the second pull-down node; a first gating unit configured to pull down the second pull-down node; and a second gating unit configured to pull down the first pull-down node. The invention also provides a driving method of the shift register unit, a grid driving circuit and a display device.

Description

Shift register unit and driving method thereof, gate drive circuit and display device

Technical Field

The invention relates to the field of display, in particular to a shift register unit, a driving method thereof, a grid driving circuit and a display device.

Background

In the Array substrate line drive (GOA) technology, a thin film transistor is integrated in a peripheral area of an Array substrate to replace a Gate drive IC, so that the size of the peripheral area can be effectively reduced, and narrow-frame implementation is facilitated.

At present, a shift register unit generally adopts a double pull-down circuit to pull down the potential of a pull-up node alternately, and the double pull-down circuit responds to the control of the respective corresponding pull-down node to conduct the pull-up node and a low level voltage end, so as to reduce noise of the pull-up node. However, in the actual driving process, when one of the pull-down nodes is at the effective potential, the pull-down node corresponding to the other pull-down circuit may be in a floating state, so that the pull-down circuit is easily interfered by the outside, and the noise reduction of the pull-up node is interfered, thereby affecting the noise reduction effect.

Disclosure of Invention

The present invention is directed to at least one of the technical problems in the prior art, and provides a shift register unit, a driving method thereof, a gate driving circuit and a display device.

In order to achieve the above object, the present invention provides a shift register unit, including: an input sub-circuit and an output sub-circuit, the input sub-circuit configured to: in response to control of the input to charge the pull-up node, the output sub-circuit is configured to: transmitting a signal of a clock signal terminal to a shift signal output terminal and a scan signal output terminal in response to the control of the pull-up node, wherein the shift register unit further includes:

a reset sub-circuit configured to: resetting the pull-up node, the shift signal output terminal and the scan signal output terminal in response to control of a reset terminal;

a first control sub-circuit configured to: charging a first pull-down node in response to an active level signal of a first voltage terminal, and pulling down the first pull-down node in response to control of the pull-up node and the input terminal;

a first noise reduction sub-circuit configured to: de-noising the pull-up node, the shift signal output and the scan signal output in response to control of the first pull-down node;

a second control sub-circuit configured to: charging a second pull-down node in response to an active level signal of a second voltage terminal, and pulling down the second pull-down node in response to control of the pull-up node and the input terminal;

a second noise reduction sub-circuit configured to: de-noising the pull-up node, the shift signal output terminal and the scan signal output terminal in response to control of the second pull-down node;

a first gating unit configured to: responding to an effective level signal of the first voltage end, and pulling down the second pull-down node;

a second gating unit configured to: responding to an effective level signal of the second voltage end, and pulling down the first pull-down node;

wherein the first voltage terminal and the second voltage terminal are provided with an active level signal and an inactive level signal alternately, and at any time, one of the first voltage terminal and the second voltage terminal provides an active level signal and the other provides an inactive level signal.

Optionally, the first gating unit includes: a first gating transistor, the second gating unit including: a second gating transistor;

a first pole of the first gating transistor is connected with the second pull-down node, a grid electrode of the first gating transistor is connected with the first voltage end, and a second pole of the first gating transistor is connected with a third voltage end;

and the first pole of the second gating transistor is connected with the first pull-down node, the grid of the second gating transistor is connected with the second voltage end, and the second pole of the second gating transistor is connected with the third voltage end.

Optionally, the output sub-circuit comprises: a first output transistor, a second output transistor and a first capacitor;

one end of the first capacitor is connected with the pull-up node, the other end of the first capacitor is connected with the shift signal output end, the first pole of the first output transistor and the first pole of the second output transistor are both connected with the clock signal end, the grid of the first output transistor and the grid of the second output transistor are both connected with the pull-up node, the second pole of the first output transistor is connected with the shift signal output end, and the second pole of the second output transistor is connected with the scanning signal output end.

Optionally, the reset sub-circuit comprises: a first reset transistor, a second reset transistor, and a third reset transistor;

the first pole of the first reset transistor is connected with the pull-up node, the second pole of the first reset transistor is connected with the third voltage end, the first pole of the second reset transistor is connected with the shift signal output end, the second pole of the second reset transistor is connected with the third voltage end, the first pole of the third reset transistor is connected with the scanning signal output end, the second pole of the third reset transistor is connected with the fourth voltage end, and the grid electrode of the first reset transistor, the grid electrode of the second reset transistor and the grid electrode of the third reset transistor are connected with the reset end.

Optionally, the first control sub-circuit comprises: a first control transistor, a second control transistor, and a third control transistor, the second control sub-circuit comprising: a fourth control transistor, a fifth control transistor, and a sixth control transistor;

a first pole and a grid of the first control transistor are connected with the first voltage end, a second pole of the first control transistor is connected with the first pull-down node, a first pole of the second control transistor and a first pole of the third control transistor are connected with the first pull-down node, a second pole of the second control transistor and a second pole of the third control transistor are connected with a third voltage end, a grid of the second control transistor is connected with the input end, and a grid of the third control transistor is connected with the pull-up node;

the first pole and the grid of the fourth control transistor are both connected with the second voltage end, the second pole of the fourth control transistor is connected with the second pull-down node, the first pole of the fifth control transistor and the first pole of the sixth control transistor are both connected with the second pull-down node, the second pole of the fifth control transistor and the second pole of the sixth control transistor are both connected with the third voltage end, the grid of the fifth control transistor is connected with the input end, and the grid of the sixth control transistor is connected with the pull-up node.

Optionally, the first noise reduction sub-circuit comprises: a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor, the second noise reduction sub-circuit comprising: a fourth noise reduction transistor, a fifth noise reduction transistor and a sixth noise reduction transistor;

the grid electrode of the first noise reduction transistor, the grid electrode of the second noise reduction transistor and the grid electrode of the third noise reduction transistor are all connected with the first pull-down node, the second pole of the first noise reduction transistor and the second pole of the second noise reduction transistor are all connected with a third voltage end, the second pole of the third noise reduction transistor is connected with a fourth voltage end, the first pole of the first noise reduction transistor is connected with the pull-up node, the first pole of the second noise reduction transistor is connected with the shift signal output end, and the first pole of the third noise reduction transistor is connected with the scanning signal output end;

the grid electrode of the fourth noise reduction transistor, the grid electrode of the fifth noise reduction transistor and the grid electrode of the sixth noise reduction transistor are all connected with the second pull-down node, the second pole of the fourth noise reduction transistor and the second pole of the fifth noise reduction transistor are all connected with the third voltage end, the second pole of the sixth noise reduction transistor is connected with the fourth voltage end, the first pole of the fourth noise reduction transistor is connected with the pull-up node, the first pole of the fifth noise reduction transistor is connected with the shift signal output end, and the first pole of the sixth noise reduction transistor is connected with the scan signal output end.

Optionally, the input sub-circuit comprises: and the first pole and the grid electrode of the input transistor are connected with the input end, and the second pole of the input transistor is connected with the pull-up node.

Optionally, the shift register unit further comprises a reset sub-circuit configured to: and responding to the control of a reset terminal to reset the pull-up node.

Optionally, the reset submodule includes a reset transistor, a first pole of the reset transistor is connected to the pull-up node, a second pole of the reset transistor is connected to the third voltage terminal, and a gate of the reset transistor is connected to the reset terminal.

The invention also provides a grid driving circuit, which comprises a plurality of cascaded shift register units, wherein the shift register units are the shift register units, and except the last stage of shift register unit, the shift signal output ends of other shift register units at each stage are connected with the input end of the corresponding shift register unit at the next stage;

except the first stage of shift register unit, the shift signal output ends of other shift register units are connected with the reset end of the corresponding previous shift register unit.

The invention also provides a display device, which comprises the grid drive circuit.

The invention further provides a driving method applied to the shift register unit, wherein the driving method comprises the following steps:

in the input stage, an active level signal is provided to the input end, an inactive level signal is provided to the clock signal end, so that the input sub-circuit charges a pull-up node, and the second control sub-circuit pulls down the first pull-down node;

an output stage, providing an effective level signal to the clock signal terminal, and outputting the effective level signal of the clock signal terminal to the shift signal output terminal and the scan signal output terminal by the output sub-circuit;

a reset stage, which provides an active level signal to the reset terminal, so that the first reset circuit resets the pull-up node, the shift signal output terminal and the scan signal output terminal;

a noise reduction stage, providing an active level signal to the first voltage terminal and providing an inactive level signal to the second voltage terminal, so that the first control circuit charges the first pull-down node and the second gating unit pulls down the second pull-down node; or, providing an invalid level signal to the first voltage terminal, and providing an effective level signal to the second voltage terminal, so that the second control sub-circuit charges the second pull-down node, and the first gating unit pulls down the first pull-down node.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a diagram illustrating a shift register unit according to the related art;

FIG. 2 is a schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 3 is a second schematic circuit diagram of a shift register unit according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating a driving method of a shift register unit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 6 is a driving timing diagram of the gate driving circuit according to the embodiment of the invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Similarly, the word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 1 is a schematic structural diagram of a shift register unit in the related art, and as shown in fig. 1, the shift register unit includes an input sub-circuit 1, an output sub-circuit 2, a reset sub-circuit 3, a first voltage terminal VDDO, a first control sub-circuit 41, a first pull-down sub-circuit 42, a second voltage terminal VDDE, a second control sub-circuit 51, and a second pull-down sub-circuit 52, where the first voltage terminal VDDO and the second voltage terminal VDDE alternately provide active level signals. Taking the first voltage terminal VDDO for raising the active level signal and the second voltage terminal VDDE for providing the inactive level signal as an example, the operation process of the shift register unit is as follows:

in the input phase, the pull-up node PU charges in response to the control of the input sub-circuit 1. The first and

second control sub-circuits

41 and 51 pull down the first and second pull-down nodes PD1 and PD2 in response to the control of the pull-up node PU.

In the output stage, the output sub-circuit 2 transmits a clock control signal to the output terminal in response to the control of the pull-up node PU.

In the reset phase, the reset sub-circuit 3 resets the pull-up node PU in response to the control of the reset terminal.

In the noise reduction stage, the first control sub-circuit 41 responds to the control of the first voltage terminal VDDO to reduce the noise of the pull-up node PU, at this time, the second pull-down node PD2 is in a suspended state, so that the pull-up node PU is in a suspended state, and the external interference may cause the potential of the pull-up node PU to rise, thereby affecting the noise reduction effect of the pull-up node PU.

In view of the above, an embodiment of the present invention provides a shift register unit, and fig. 2 is a schematic circuit diagram of the shift register unit according to the embodiment of the present invention, as shown in fig. 2, the shift register unit includes: an input sub-circuit 1 and an output sub-circuit 2, the input sub-circuit 1 being configured to: in response to the control of the Input terminal to charge the pull-up node PU, the output sub-circuit 2 is configured to: the signal of the clock signal terminal CLK is transmitted to the shift signal Output terminal OC and the scan signal Output terminal Output in response to the control of the pull-up node PU. Wherein, shift register unit still includes: a reset sub-circuit 3, a first control sub-circuit 41, a first noise reduction sub-circuit 42, a second control sub-circuit 51, a second noise reduction sub-circuit 52, a first gating unit 43, and a second gating unit 53. The reset sub-circuit 3 is configured to: the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output are reset in response to control of the reset terminal REST. The first control sub-circuit 41 is configured to: the first pull-down node PD1 is charged in response to an active level signal of the first voltage terminal VDDO, and the first pull-down node PD1 is pulled down in response to control of the pull-up node PU and the Input terminal Input. The first noise reduction sub-circuit 42 is configured to: the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output are denoised in response to the control of the first pull-down node PD 1. The second control sub-circuit 51 is configured to: the second pull-down node PD2 is charged in response to the active level signal of the second voltage terminal VDDE, and the second pull-down node PD2 is pulled down in response to the control of the pull-up node PU and the Input terminal Input. The second noise reduction sub-circuit 52 is configured to: the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output are denoised in response to the control of the second pull-down node PD 2. The first gating unit 43 is configured to: the second pull-down node PD2 is pulled down in response to the active level signal of the first voltage terminal VDDO. The second gating unit 53 is configured to: the first pull-down node PD1 is pulled down in response to the active level signal of the second voltage terminal VDDE. Wherein the first voltage terminal VDDO and the second voltage terminal VDDE each alternately provide an active level signal and an inactive level signal, and at any time, one of the first voltage terminal VDDO and the second voltage terminal VDDE provides an active level signal and the other one provides an inactive level signal.

In the embodiment of the present invention, the first voltage terminal VDDO and the second voltage terminal VDDE may each alternately provide the active level signal and the inactive level signal every 2 seconds. The shift signal Output terminal OC is used for providing input signals for other cascaded shift register units, the scan signal Output terminal Output is used for providing driving signals for the pixel circuit, and Output signals of the shift signal Output terminal OC and the scan signal Output terminal Output can be the same. The reset sub-circuit 3 provides an invalid level signal to the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output in response to the valid level signal of the reset terminal REST, thereby resetting the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output. The first control sub-circuit 41 provides an active level signal to the first pull-down node PD1 in response to the active level signal of the first voltage terminal VDDO, thereby charging the first pull-down node PD 1. The first control sub-circuit 41 supplies an inactive level signal to the first pull-down node PD1 in response to an active level signal of the Input terminal and an active level signal of the pull-up node PU, thereby pulling down the first pull-down node PD 1. The first gating unit 43 supplies an inactive level signal to the second pull-down node PD2 in response to the active level signal of the first voltage terminal VDDO, thereby pulling down the second pull-down node PD 2. The first noise reduction sub-circuit 42 supplies an invalid level signal to the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output in response to the valid level signal of the PD1, thereby reducing noise on the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output. The second control sub-circuit 51 provides an active level signal to the second pull-down node PD2 in response to the active level signal of the second voltage terminal VDDE, thereby charging the second pull-down node PD 2. The second control sub-circuit 51 supplies an inactive level signal to the second pull-down node PD2 in response to an active level signal of the Input terminal and an active level signal of the pull-up node PU, thereby pulling down the second pull-down node PD 2. The second noise reduction sub-circuit 52 provides an invalid level signal to the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output in response to the valid level signal of the PD2, thereby reducing noise on the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output. The second gating unit 53 supplies an inactive level signal to the first pull-down node PD1 in response to an active level signal of the second voltage terminal VDDE, thereby pulling down the second pull-down node PD 2.

In the noise reduction stage in the embodiment of the present invention, when the first voltage terminal VDDO provides an active level signal, the first pull-down node PD1 may be charged by the first control sub-circuit 41, and the second pull-down node PD2 may be pulled down by the first gating unit 43; when the second voltage terminal VDDE provides an active level signal, the second pull-down node PD2 may be charged by the second control sub-circuit 51, and the first pull-down node PD1 may be pulled down by the second gating unit 53. Since the first voltage terminal VDDO and the second voltage terminal VDDE alternately provide effective level signals, the shift register unit provided in the embodiment of the present invention can prevent any one of the first pull-down node PD1 and the second pull-down node PD2 from being in a floating state, thereby preventing noise reduction of the pull-up node PU from being interfered due to the first pull-down node PD1 or the second pull-down node PD2 being in a floating state, and improving noise reduction effect.

The operation of the shift register unit according to the embodiment of the present invention will be described below by taking the example that the first voltage terminal VDDO provides an active level signal and the second voltage terminal VDDE provides an inactive level signal:

in the Input stage, the Input terminal Input provides an active level signal, and the Input sub-circuit 1 charges the pull-up node PU in response to the active level signal of the Input terminal Input. The first control sub-circuit 41 pulls down the first pull-down node PD1 in response to the active level signal of the Input terminal Input and the active level signal of the pull-up node PU, and the second control sub-circuit 51 pulls down the second pull-down node PD2 in response to the active level signal of the Input terminal Input and the active level signal of the pull-up node PU. The clock signal terminal CLK outputs an invalid level signal, and the Output sub-circuit 2 transmits the invalid level signal Output from the clock signal terminal CLK to the shift signal Output terminal OC and the scan signal Output terminal Output in response to the valid level signal of the pull-up node PU.

In the output stage, the Input terminal provides an inactive level signal, the first control sub-circuit 41 makes the first pull-down node PD1 keep pulling down in response to an active level signal of the pull-up node PU, and the second control sub-circuit 51 makes the second pull-down node PD2 keep pulling down in response to an active level signal of the pull-up node PU. The clock signal terminal CLK provides an active level signal, and the Output sub circuit 2 transmits the active level signal Output from the clock signal terminal CLK to the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level signal of the pull-up node PU.

In the reset phase, the reset terminal REST provides an active level signal, and the reset sub-circuit 3 resets the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output in response to the active level signal of the reset terminal REST. The first control sub-circuit 41 charges the first pull-down node PD1 in response to the active level signal of the first voltage terminal VDDO, the first noise reduction sub-circuit 42 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level signal of the first pull-down node PD1, and the first gating unit 43 pulls down the second pull-down node PD2 in response to the active level signal of the first voltage terminal VDDO.

In the noise reduction stage, the reset terminal REST provides an invalid level signal, the first control sub-circuit 41 charges the first pull-down node PD1 in response to the valid level signal of the first voltage terminal VDDO, the first noise reduction sub-circuit 42 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the valid level signal of the first pull-down node PD1, and the first gating unit 43 pulls down the second pull-down node PD2 in response to the valid level signal of the first voltage terminal VDDO.

It is to be understood that when the second voltage terminal VDDE provides an active level signal and the first voltage terminal VDDO provides an inactive level signal, the second control sub-circuit 51 pulls down the second pull-down node PD2 in response to the active level signal of the Input terminal and the active level signal of the pull-up node PU during the Input phase; in the reset phase and the noise reduction phase, the second control sub-circuit 51 charges the second pull-down node PD2 in response to the active level signal of the second voltage terminal VDDE, the second noise reduction sub-circuit 52 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level signal of the second pull-down node PD2, and the second gating unit 53 pulls down the first pull-down node PD1 in response to the active level signal of the second voltage terminal VDDE.

In summary, with the shift register unit according to the embodiment of the present invention, in the above-mentioned stages, the first pull-down node PD1 and the second pull-down node PD2 are not in a floating state, so that a better noise reduction effect is achieved.

The specific structure of the shift register unit according to the embodiment of the present invention is described in detail with reference to fig. 2 and fig. 3, and it should be noted that the transistor according to the embodiment of the present invention may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics. Transistors generally include three poles: the gate, source and drain, the source and drain in a transistor are symmetrical in structure, and the two may be interchanged as desired. In the embodiment of the invention, one of the first pole and the second pole is a source electrode, and the other is a drain electrode.

Further, the transistors may be classified into N-type transistors and P-type transistors according to transistor characteristics. In the invention, an "active level signal" refers to a voltage signal capable of controlling the turn-on of a corresponding transistor, and an "inactive level signal" refers to a voltage signal capable of controlling the turn-off of a corresponding transistor; therefore, when the transistor is an N-type transistor, the active level signal refers to a high level signal, and the inactive level signal refers to a low level signal; when the transistor is a P-type transistor, the active level signal is a low level signal, and the inactive level signal is a high level signal.

In the following description of the embodiments, the transistors are exemplified as being N-type transistors. In this case, the active level signal is a high level signal, and the inactive level signal is a low level signal. In addition, each transistor in the embodiment of the present invention may be an oxide thin film transistor.

Fig. 3 is a second schematic circuit diagram of a shift register unit according to an embodiment of the present invention, and as shown in fig. 3, the first gating unit 43 includes: the first gating transistor M9A, the second gating unit 53 includes: the second gating transistor M9B. A first pole of the first gating transistor M9A is connected to the second pull-down node PD2, a gate of the first gating transistor M9A is connected to the first voltage terminal VDDO, and a second pole of the first gating transistor M9A is connected to the third voltage terminal VSS 1. A first pole of the second gate transistor M9B is connected to the first pull-down node PD1, a gate of the second gate transistor M9B is connected to the second voltage terminal VDDE, and a second pole of the second gate transistor M9B is connected to the third voltage terminal VSS 1.

In some embodiments, the output sub-circuit 2 comprises: a first output transistor M11, a second output transistor M3, and a first capacitor C1. One end of the first capacitor C1 is connected to the pull-up node PU, and the other end of the first capacitor C1 is connected to the shift signal output terminal OC. A first pole of the first Output transistor M11 and a first pole of the second Output transistor M3 are both connected to the clock signal terminal CLK, a gate of the first Output transistor M11 and a gate of the second Output transistor M3 are both connected to the pull-up node PU, a second pole of the first Output transistor M11 is connected to the shift signal Output terminal OC, and a second pole of the second Output transistor M3 is connected to the scan signal Output terminal Output.

In some embodiments, the shift register unit further includes a reset sub-circuit 6, and the reset sub-circuit 6 is configured to reset the potential of the pull-up node PU in response to the control of the reset terminal T _ REST. Wherein the reset terminal T _ REST is used to provide an active level signal before each frame of a picture. The reset sub-circuit 6 includes a reset transistor M10, a first pole of the reset transistor M10 is connected to the pull-up node PU, a second pole of the reset transistor M10 is connected to the third voltage terminal VSS1, and a gate of the reset transistor M10 is connected to the reset terminal T _ REST. When the reset terminal T _ REST provides an active level signal, the reset transistor M10 turns on the pull-up node PU and the third voltage terminal VSS1, thereby resetting the potential of the pull-up node PU of all the shift register units. Wherein, the reset ends of all the shift register units can be connected together.

The inventor of the present invention has noticed in research that, in the related art, the reset of some nodes is controlled only by the pull-up node PU (for example, the shift signal output terminal OC), and the reset performed only by the pull-up node PU has a certain hysteresis, and in order to improve the hysteresis, in the embodiment of the present invention, a plurality of reset transistors are provided, and the plurality of reset transistors are respectively controlled by the respective corresponding reset sub-terminals, specifically, in some embodiments, the reset sub-circuit 3 includes: a first reset transistor M2, a second reset transistor M4A, and a third reset transistor M4B. A first pole of the first reset transistor M2 is connected to the pull-up node PU, a second pole of the first reset transistor M2 is connected to the third voltage terminal VSS1, a first pole of the second reset transistor M4A is connected to the shift signal Output terminal OC, a second pole of the second reset transistor M4A is connected to the third voltage terminal VSS1, a first pole of the third reset transistor M4B is connected to the scan signal Output terminal Output, a second pole of the third reset transistor M4B is connected to the fourth voltage terminal VSS2, and a gate of the reset transistor M10, a gate of the first reset transistor M2, a gate of the second reset transistor M4A, and a gate of the third reset transistor M4B are connected to the reset terminal REST.

In an embodiment of the present invention, the reset terminal includes: a first reset sub terminal REST1 and a second reset sub terminal REST 2. The first reset sub-terminal REST1 is connected to the gate of the first reset transistor M2, and the second reset sub-terminal REST2 is connected to the gates of the second reset transistor M4A and the third reset transistor M4B. The first reset sub-terminal REST1 may be connected to the shift signal output terminal OC of the next stage shift register unit, and is configured to control the first reset transistor M2 of the present stage shift register unit to reset the pull-up node PU when the shift signal output terminal OC of the next stage shift register unit outputs an active level signal. The second reset sub-terminal REST2 may be connected to the scan signal Output terminal Output of the next-stage shift register unit, and is configured to control the second reset transistor M4A of the shift register unit of this stage to reset the shift signal Output terminal OC when the scan signal Output terminal Output of the next-stage shift register unit outputs a valid level signal, and control the third reset transistor M4B to reset the scan signal Output terminal Output. The multiple reset transistors of the embodiment of the invention can effectively improve the problem of hysteresis and improve the reliability of reset.

The inventor of the present invention has noticed in the research that, in the related art, since it takes a certain time for the pull-up node PU to be charged from the inactive level signal to the active level signal, the third control transistor M7A and the sixth control transistor M7B pull down the first pull-down node PD1 with a certain hysteresis, and therefore, in the embodiment of the present invention, the second control transistor M6A and the fifth control transistor M6B are further provided to pull down the first pull-down node PD 1. Specifically, the first control sub-circuit 41 includes: the first control transistor M5A, the second control transistor M6A, and the third control transistor M7A, the second control sub-circuit 51 includes: a fourth control transistor M5B, a fifth control transistor M6B, and a sixth control transistor M7B. A first pole and a gate of the first control transistor M5A are both connected to the first voltage terminal VDDO, a second pole of the first control transistor M5A is connected to the first pull-down node PD1, a first pole of the second control transistor M6A and a first pole of the third control transistor M7A are both connected to the first pull-down node PD1, a second pole of the second control transistor M6A and a second pole of the third control transistor M7A are both connected to the third voltage terminal VSS1, a gate of the second control transistor M6A is connected to the Input terminal Input, and a gate of the third control transistor M7A is connected to the pull-up node PU. A first pole and a gate of the fourth control transistor M5B are both connected to the second voltage terminal VDDE, a second pole of the fourth control transistor M5B is connected to the second pull-down node PD2, a first pole of the fifth control transistor M6B and a first pole of the sixth control transistor M7B are both connected to the second pull-down node PD2, a second pole of the fifth control transistor M6B and a second pole of the sixth control transistor M7B are both connected to the third voltage terminal VSS1, a gate of the fifth control transistor M6B is connected to the Input terminal Input, and a gate of the sixth control transistor M7B is connected to the pull-up node PU. In the embodiment of the invention, the third voltage terminal VSS1 is used for providing an invalid level signal.

In the embodiment of the present invention, since the second control transistor M6A and the fifth control transistor M6B are responsive to the active level signal of the Input terminal to pull down the pull-up node PU, the hysteresis problem when the third control transistor M7A and the sixth control transistor M7B pull down the first pull-down node PD1 can be effectively improved.

In some embodiments, the first noise reduction sub-circuit 42 includes: a first noise reduction transistor M8A, a second noise reduction transistor M12A, and a third noise reduction transistor M13A, the second noise reduction sub-circuit 52 including: a fourth noise reduction transistor M8B, a fifth noise reduction transistor M12B, and a sixth noise reduction transistor M13B. A gate of the first noise reduction transistor M8A, a gate of the second noise reduction transistor M12A, and a gate of the third noise reduction transistor M13A are all connected to the first pull-down node PD1, a second pole of the first noise reduction transistor M8A and a second pole of the second noise reduction transistor M12A are all connected to the third voltage terminal VSS1, a second pole of the third noise reduction transistor M13A is connected to the fourth voltage terminal VSS2, a first pole of the first noise reduction transistor M8A is connected to the pull-up node PU, a first pole of the second noise reduction transistor M12A is connected to the shift signal Output terminal OC, and a first pole of the third noise reduction transistor M13A is connected to the scan signal Output terminal Output. A gate of the fourth noise reduction transistor M8B, a gate of the fifth noise reduction transistor M12B, and a gate of the sixth noise reduction transistor M13B are all connected to the second pull-down node PD2, a second pole of the fourth noise reduction transistor M8B and a second pole of the fifth noise reduction transistor M12B are all connected to the third voltage terminal VSS1, a second pole of the sixth noise reduction transistor M13B is connected to the fourth voltage terminal VSS2, a first pole of the fourth noise reduction transistor M8B is connected to the pull-up node PU, a first pole of the fifth noise reduction transistor M12B is connected to the shift signal Output terminal OC, and a first pole of the sixth noise reduction transistor M13B is connected to the scan signal Output terminal Output. In the embodiment of the present invention, the fourth voltage terminal VSS2 is used for providing an inactive level signal.

In some embodiments, the input sub-circuit 1 comprises: the first pole and the gate of the Input transistor M1 are connected to the Input terminal Input, and the second pole of the Input transistor M1 is connected to the pull-up node PU, of the Input transistor M1.

Fig. 4 is a timing diagram of driving the shift register unit according to the embodiment of the present invention, and the following description will be made in detail with reference to fig. 4, taking the first voltage terminal VDDO providing an active level signal and the second voltage terminal VDDE providing an inactive level signal as an example:

in the first reset period T1, the reset terminal T _ REST provides an active level signal, and the reset transistor M10 turns on the pull-up node PU and the third voltage terminal VSS1, thereby resetting the pull-up node PU. The first control transistor M5A turns on the first voltage terminal VDDO and the first pull-up node PD1, so as to charge the first pull-up node PD1, and the first pull-up node PD1 is charged to an active potential. The first noise reduction transistor M8A turns on the pull-up node PU and the third voltage terminal VSS1, the second noise reduction transistor M12A turns on the shift signal Output terminal OC and the third voltage terminal VSS1, and the third noise reduction transistor M13A turns on the scan signal Output terminal Output and the third voltage terminal VSS1, so that noise reduction is performed on the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output. The fourth control transistor M5B disconnects the second voltage terminal VDDE from the second pull-up node PD2, and the first gating transistor M9A turns on the second pull-down node PD2 and the third voltage terminal VSS1 to pull down the second pull-down node PD2, thereby turning off the fourth noise reduction transistor M8B, the fifth noise reduction transistor M12B, and the sixth noise reduction transistor M13B.

In the input period T2, the reset terminal T _ REST provides an inactive level signal, and the reset transistor M10 disconnects the pull-up node PU from the third voltage terminal VSS 1. An active level signal is provided to the Input terminal Input, and the Input transistor M1 turns on the Input terminal Input and the pull-up node PU, so as to charge the pull-up node PU, and the pull-up node PU is charged to the active level signal. The second control transistor M6A and the third control transistor M7A both turn on the first pull-down node PD1 and the third voltage terminal VSS1 to pull down the first pull-down node PD1, so as to turn off the first noise reduction transistor M8A, the second noise reduction transistor M12A and the third noise reduction transistor M13A, thereby preventing the first noise reduction sub-circuit 42 from affecting the level signal of the pull-up node PU. The clock signal terminal CLK provides an invalid level signal, the first Output transistor M11 switches the clock signal terminal CLK on the shift signal Output terminal OC, the second Output transistor M3 switches the clock signal terminal CLK on the scan signal Output terminal Output, and the invalid level signal Output by the clock signal terminal CLK is transmitted to the shift signal Output terminal OC and the scan signal Output terminal Output, respectively.

In the output phase t3, the Input terminal Input provides an inactive level signal, and the Input transistor M1 disconnects the Input terminal Input from the pull-up node PU. The clock signal terminal CLK provides an effective level signal, the first capacitor C1 further raises the potential of the pull-up node PU due to a bootstrap action, the first Output transistor M11 and the second Output transistor M3 are fully turned on, and the effective level signal Output by the clock signal terminal CLK is transmitted to the shift signal Output terminal OC and the scan signal Output terminal Output, respectively.

In the second reset phase t4, the first reset sub-terminal REST1 and the second reset sub-terminal REST2 provide active level signals, the first reset transistor M2 turns on the pull-up node PU and the third voltage terminal VSS1, the second reset transistor M4A turns on the shift signal Output terminal OC and the third voltage terminal VSS1, and the third reset transistor M4B turns on the scan signal Output terminal Output and the fourth voltage terminal VSS2, so that the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output are reset. The first control transistor M5A turns on the first voltage terminal VDDO and the first pull-up node PD1, so as to charge the first pull-up node PD1, and the first pull-up node PD1 is charged to an active potential. The first noise reduction transistor M8A turns on the pull-up node PU and the third voltage terminal VSS1, the second noise reduction transistor M12A turns on the shift signal Output terminal OC and the third voltage terminal VSS1, and the third noise reduction transistor M13A turns on the scan signal Output terminal Output and the third voltage terminal VSS1, so that noise reduction is performed on the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output.

During the noise reduction period t5, the first control transistor M5A turns on the first voltage terminal VDDO and the first pull-up node PD1, so as to charge the first pull-up node PD1, and the first pull-up node PD1 is charged to the active potential. The first noise reduction transistor M8A turns on the pull-up node PU and the third voltage terminal VSS1, the second noise reduction transistor M12A turns on the shift signal Output terminal OC and the third voltage terminal VSS1, and the third noise reduction transistor M13A turns on the scan signal Output terminal Output and the third voltage terminal VSS1, so that noise reduction is performed on the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output.

It is understood that, in the embodiment of the present invention, when the first voltage terminal VDDO provides an inactive level signal and the second voltage terminal VDDE provides an active level signal, the second control transistor M5B turns on the second voltage terminal VDDE and the second pull-up node PD2 during the first reset phase t1, the second reset phase t4 and the noise reduction phase t5, so as to charge the second pull-up node PD2 and the second pull-up node PD2 to an active potential. The fourth noise reduction transistor M8B turns on the pull-up node PU and the third voltage terminal VSS1, the fifth noise reduction transistor M12B turns on the shift signal Output terminal OC and the third voltage terminal VSS1, and the sixth noise reduction transistor M13B turns on the scan signal Output terminal Output and the third voltage terminal VSS1, so that noise reduction is performed on the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output. The first control transistor M5A disconnects the first voltage terminal VDDO from the first pull-up node PD1, and the second gating transistor M9B turns on the first pull-down node PD1 and the third voltage terminal VSS1 to pull down the first pull-down node PD1, thereby turning off the first noise reduction transistor M8A, the third noise reduction transistor M12A, and the third noise reduction transistor M13A; in the input stage t2, the fifth control transistor M6B and the sixth control transistor M7B both turn on the second pull-down node PD2 and the third voltage terminal VSS1 to pull down the second pull-down node PD2, so as to turn off the fourth noise reduction transistor M8B, the fifth noise reduction transistor M12B and the sixth noise reduction transistor M13B, and prevent the second noise reduction sub-circuit 52 from affecting the potential of the pull-up node PU.

The invention further provides a gate driving circuit, which comprises a plurality of cascaded shift register units, wherein the shift register units are the shift register units provided in the embodiment, except for the last stage of shift register unit, the shift signal output ends of other shift register units at each stage are connected with the input end of the corresponding shift register unit at the next stage. Except the first stage of shift register unit, the shift signal output ends of other shift register units are connected with the reset end of the corresponding previous shift register unit. The scanning signal output end of the shift register unit is connected with the grid line of the display panel and used for providing a scanning signal for the grid line.

Fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and fig. 6 is a driving timing diagram of the gate driving circuit according to the embodiment of the present invention, which is combined with fig. 5 and fig. 6, and takes 3 shift register units SR _1, SR _2, and SR _3 of a plurality of cascaded shift register units as an example, the gate driving circuit corresponds to two clock signal lines CLK1 and CLK2, wherein a clock signal terminal CLK of an nth stage shift register unit is connected to a first clock signal line CLK1, and a clock signal terminal CLK of an n +1 th stage shift register unit is connected to a second clock signal line CLK 2. The clock signal terminal CLK of the (n + 1) th stage shift register unit is connected to the second clock signal line CLK 2. The Input end Input of the nth stage shift register unit is connected with the shift signal output end OC of the (n-1) th stage shift register unit. And the reset end REST of the nth-stage shift register unit is connected with the shift signal Output end OC and the scanning signal Output end Output of the (n + 1) th-stage shift register unit. The reset terminal T _ REST of the shift register unit is connected to a reset control line RESTL. The first clock signal line CLK1 and the second clock signal line CLK2 alternately provide an active level signal, and after a scan start signal is provided to the Input terminal Input of the first shift register unit SR _1, the Output terminal Output1 of the first shift register unit SR _1, the Output terminal Output2 of the second shift register unit SR _1, and the Output terminal Output3 of the third shift register unit SR _1 sequentially Output the active level signal, so that the corresponding light-emitting units in the display panel are driven by the gate lines to emit light. In the embodiment of the invention, the first voltage end VDDO and the second voltage end VDDE can alternately provide an effective level signal and an ineffective level signal every 2 seconds so as to reduce noise of the shift register unit, and in the noise reduction process, the first gating unit and the second gating unit ensure that any one of the first pull-down node and the second pull-down node is not in a suspended state, so that the noise reduction effect is improved.

The invention also provides a display device, which comprises the gate driving circuit in the embodiment. The display device may be: the display device comprises any product or component with a display function, such as electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

An embodiment of the present invention further provides a driving method applied to the shift register unit provided in the foregoing embodiment, and as shown in fig. 2, the driving method includes:

in the Input stage, an active level signal is provided to the Input terminal Input, and an inactive level signal is provided to the clock signal terminal CLK, so that the Input sub-circuit 1 charges the pull-up node PU, and the second control sub-circuit 51 pulls down the first pull-down node PD 1.

In the Output stage, the clock signal terminal CLK is provided with an active level signal, and the Output sub-circuit 2 outputs the active level signal of the clock signal terminal to the shift signal Output terminal OC and the scan signal Output terminal Output.

In the reset stage, an effective level signal is provided to the reset terminal REST, so that the first reset sub-circuit 3 resets the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output.

The noise reduction stage provides an active level signal to the first voltage terminal VDDO and provides an inactive level signal to the second voltage terminal VDDE to cause the first control circuit to charge the first pull-down node PD1 and cause the second gating unit 53 to pull down the second pull-down node PD 2. Alternatively, the inactive level signal is provided to the first voltage terminal VDDO, and the active level signal is provided to the second voltage terminal VDDE, so that the second control sub-circuit 51 charges the second pull-down node PD2, and the first gating unit 43 pulls down the first pull-down node PD 1.

The following describes the driving method of the embodiment of the present invention by taking the first voltage terminal VDDO providing an active level signal and the second voltage terminal VDDE providing an inactive level signal as an example:

in the Input stage, the Input terminal Input provides an active level signal, and the Input sub-circuit 1 charges the pull-up node PU in response to the active level signal of the Input terminal Input. The first control sub-circuit 41 pulls down the first pull-down node PD1 in response to the effective potential of the Input terminal Input and the effective level potential of the pull-up node PU, and the second control sub-circuit 51 pulls down the second pull-down node PD2 in response to the effective level potential of the Input terminal Input and the effective level potential of the pull-up node PU. The clock signal terminal CLK outputs an invalid level signal, and the Output sub-circuit 2 transmits the invalid level signal Output from the clock signal terminal CLK to the shift signal Output terminal OC and the scan signal Output terminal Output in response to the valid level potential of the pull-up node PU.

In the output stage, the Input terminal provides an inactive level signal, the first control sub-circuit 41 makes the first pull-down node PD1 keep pulling down in response to the active level signal of the pull-up node PU, and the second control sub-circuit 51 makes the second pull-down node PD2 keep pulling down in response to the active level potential of the pull-up node PU. The clock signal terminal CLK provides an active level signal, and the Output sub circuit 2 transmits the active level signal Output from the clock signal terminal CLK to the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level signal of the pull-up node PU.

In the reset phase, the reset terminal REST provides an active level signal, and the reset sub-circuit 3 resets the pull-up node PU, the shift signal Output terminal OC, and the scan signal Output terminal Output in response to the active level signal of the reset terminal REST. The first control sub-circuit 41 charges the first pull-down node PD1 in response to the active level signal of the first voltage terminal VDDO, the first noise reduction sub-circuit 42 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level potential of the first pull-down node PD1, and the first gating unit 43 pulls down the second pull-down node PD2 in response to the active level signal of the first voltage terminal VDDO.

In the noise reduction stage, the reset terminal REST provides an invalid level signal, the first control sub-circuit 41 charges the first pull-down node PD1 in response to the valid level signal of the first voltage terminal VDDO, the first noise reduction sub-circuit 42 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the valid level potential of the first pull-down node PD1, and the first gating unit 43 pulls down the second pull-down node PD2 in response to the valid level signal of the first voltage terminal VDDO.

It is understood that when the second voltage terminal VDDE provides an active level signal, the first voltage terminal VDDO, in the Input phase, the second control sub-circuit 51 pulls down the second pull-down node PD2 in response to the active level signal at the Input terminal Input and the active level potential of the pull-up node PU; in the reset phase and the noise reduction phase, the second control sub-circuit 51 charges the second pull-down node PD2 in response to the active level signal of the second voltage terminal VDDE, the second noise reduction sub-circuit 52 reduces noise of the pull-up node PU, the shift signal Output terminal OC and the scan signal Output terminal Output in response to the active level potential of the second pull-down node PD2, and the second gating unit 53 pulls down the first pull-down node PD1 in response to the active level signal of the second voltage terminal VDDE. The input stage and the output stage are the same as the above embodiments, and are not described herein again.

In summary, by using the driving method of the embodiment of the invention, in the above-mentioned stages, the first pull-down node PD1 and the second pull-down node PD2 are not in a floating state, so that a better noise reduction effect is achieved.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register unit, comprising: an input sub-circuit and an output sub-circuit, the input sub-circuit configured to: in response to control of the input to charge the pull-up node, the output sub-circuit is configured to: responding to the control of the pull-up node, transmitting the signal of the clock signal terminal to the shift signal output terminal and the scan signal output terminal, wherein the shift register unit further comprises:

a first noise reduction sub-circuit configured to: de-noising the pull-up node, the shift signal output terminal, and the scan signal output terminal in response to control of the first pull-down node;

wherein the first voltage terminal and the second voltage terminal alternately provide an active level signal and an inactive level signal, and at any time, one of the first voltage terminal and the second voltage terminal provides an active level signal and the other provides an inactive level signal.

2. The shift register unit according to claim 1, wherein the first strobe unit includes: a first gating transistor, the second gating unit including: a second gating transistor;

a first pole of the first gating transistor is connected with the second pull-down node, a grid electrode of the first gating transistor is connected with the first voltage end, and a second pole of the first gating transistor is connected with the third voltage end;

3. The shift register cell according to claim 1 or 2, wherein the output sub-circuit comprises: a first output transistor, a second output transistor and a first capacitor;

4. The shift register unit according to claim 1 or 2, wherein the reset sub-circuit comprises: a first reset transistor, a second reset transistor, and a third reset transistor;

5. The shift register cell according to claim 1 or 2, wherein the first control sub-circuit comprises: a first control transistor, a second control transistor, and a third control transistor, the second control sub-circuit comprising: a fourth control transistor, a fifth control transistor, and a sixth control transistor;

6. The shift register cell according to claim 1 or 2, wherein the first noise reduction sub-circuit comprises: a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor, the second noise reduction sub-circuit comprising: a fourth noise reduction transistor, a fifth noise reduction transistor and a sixth noise reduction transistor;

the grid electrode of the first noise reduction transistor, the grid electrode of the second noise reduction transistor and the grid electrode of the third noise reduction transistor are all connected with the first pull-down node, the second pole of the first noise reduction transistor and the second pole of the second noise reduction transistor are all connected with a third voltage end, the second pole of the third noise reduction transistor is connected with a fourth voltage end, the first pole of the first noise reduction transistor is connected with the pull-up node, the first pole of the second noise reduction transistor is connected with the shift signal output end, and the first pole of the third noise reduction transistor is connected with the scan signal output end;

7. The shift register cell according to claim 1 or 2, wherein the input sub-circuit comprises: and the first pole and the grid of the input transistor are connected with the input end, and the second pole of the input transistor is connected with the pull-up node.

8. The shift register unit according to claim 1 or 2, further comprising a reset sub-circuit configured to: and responding to the control of a reset terminal to reset the pull-up node.

9. The shift register cell of claim 8, wherein the reset subcircuit includes a reset transistor, a first pole of the reset transistor is coupled to the pull-up node, a second pole of the reset transistor is coupled to a third voltage terminal, and a gate of the reset transistor is coupled to a reset terminal.

10. A gate drive circuit, characterized by comprising a plurality of cascaded shift register units, wherein the shift register units are the shift register units according to any one of claims 1 to 9, and except the last shift register unit, the shift signal output ends of the other shift register units are connected with the input end of the corresponding next shift register unit;

11. A display device comprising the gate driver circuit according to claim 10.

12. A driving method applied to the shift register unit according to any one of claims 1 to 9, the driving method comprising:

a reset stage, which provides an active level signal to the reset terminal, so that the reset sub-circuit resets the pull-up node, the shift signal output terminal and the scan signal output terminal;

a noise reduction stage, providing an effective level signal to the first voltage terminal and providing an ineffective level signal to the second voltage terminal, so that the first control sub-circuit charges the first pull-down node and the first gating unit pulls down the second pull-down node; or, providing an invalid level signal to the first voltage terminal, and providing an effective level signal to the second voltage terminal, so that the second control sub-circuit charges the second pull-down node, and the second gating unit pulls down the first pull-down node.