CN111385494A

CN111385494A - Solid-state image pickup device

Info

Publication number: CN111385494A
Application number: CN201911345727.2A
Authority: CN
Inventors: 芦田伸之; 饭塚邦彦; 田口滋也; 盐田昌弘
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 2018-12-26
Filing date: 2019-12-24
Publication date: 2020-07-07
Also published as: US20200213552A1

Abstract

The invention provides a solid-state imaging element which reduces 1/f noise by using the functions of a general solid-state imaging element such as row selection control. A solid-state imaging element (1A) is provided with: a pixel array (A) in which a plurality of rows of pixels (P) are arranged; a row selection unit (13) that specifies a read row of the pixel array (A); and a control device (30) that controls the row selection unit (13) so as to scan the information held by each pixel (P) a plurality of times, and that outputs an output value corresponding to the result of reading the information from each pixel (P) obtained by the scanning a plurality of times.

Description

Solid-state image pickup device

Technical Field

One aspect of the present invention relates to a solid-state imaging device including a sensor element that generates an electric signal based on a dose of incident radiation.

Background

As a sensor element that outputs an electric signal corresponding to the amount of incident radiation, for example, X-rays, a direct conversion type sensor element that directly converts X-rays into an electric signal is known. In addition, an indirect conversion type sensor element is also known, in which X-rays are converted into light by a scintillator and then converted into an electrical signal by a photoelectric conversion element such as a photodiode.

The panel for X-ray image shooting is composed of the following components: the sensor elements are provided for each pixel, and the pixels are arranged in a two-dimensional matrix on a substrate (panel). In such a panel, a Thin Film Transistor (TFT) element is used for controlling each pixel. In both of the direct conversion type and the indirect conversion type, an electric signal (charge) generated in accordance with the dose of X-rays is accumulated in a capacitor in each pixel.

A structure in which the electric signal (charge) accumulated in the capacitor is transmitted to an amplifier located outside the panel via the TFT element is referred to as a passive pixel type. A structure in which a TFT element is used as an amplification element, and an electric signal (charge) stored in a capacitor is amplified and transmitted to an external circuit is referred to as an active pixel type. In the active pixel type, since the electric signal (charge) accumulated in the capacitor can be amplified in the pixel, a larger signal can be obtained for the same dose of radiation, compared with the passive pixel type. Therefore, there is an advantage that an appropriate signal can be obtained even with a low irradiation amount.

In such a solid-state imaging device, there is a method of integrating a signal as a technique of obtaining a signal having a relatively high S/N ratio. By integrating and averaging the signals, random noise such as thermal noise can be reduced. However, there is a time dependency for 1/f noise. That is, even if the integration time is increased, the signal and noise increase in an equal manner. As a result, the S/N ratio is not improved even if the signals are integrated and averaged. Therefore, the 1/f noise greatly affects the operation of the product.

Here, the 1/f noise is noise that is output in inverse proportion to the frequency f and is dominant mainly on the low frequency side. The 1/f noise is not related to such timing as a reset period or a pixel output period, and is always a randomly generated offset.

In order to reduce the influence of the above-described 1/f noise to an arbitrary low level, for example, the image sensor disclosed in patent document 1 is configured such that a transistor is cycled between at least two bias states in a pixel reading stage. As a result, the 1/f noise of the read signal has a small time dependency. Therefore, by oversampling the signal whose correlation becomes small and performing averaging processing, 1/f noise can be reduced.

Documents of the prior art

Patent document

Patent document 1: japanese laid-open patent publication No. 2011- "

Disclosure of Invention

Technical problem to be solved by the invention

An object of one aspect of the present invention is to provide a solid-state imaging element capable of reducing 1/f noise by using a function of a general solid-state imaging element such as row selection control.

Means for solving the problems

(1) One aspect of the present invention is a solid-state imaging element including: a pixel array in which a plurality of rows of pixels are arranged; a row selecting section that designates a read row of the pixel array; and a control unit that controls the row selection unit to scan the information held by each pixel a plurality of times and output an output value corresponding to a result of reading the information from each pixel a plurality of times, the result being obtained by the scanning.

(2) In addition to the configuration of (1), the solid-state imaging device according to an embodiment of the present invention may be configured such that the control unit outputs an average value of the reading results obtained by the plurality of scans as the output value.

(3) In the solid-state imaging device according to an embodiment of the present invention, in addition to the configuration of (2), the control unit calculates the average value by correcting leakage of electric charges generated during the plurality of scanning periods.

(4) In addition to the configuration of (3), the solid-state imaging device according to an embodiment of the present invention may be configured such that the controller performs the correction based on a leakage amount measured in advance using the solid-state imaging device.

(5) In addition to the configurations (1) to (4), in the solid-state imaging device according to an embodiment of the present invention, when the pixel is in the non-read state, the source potential of the transistor included in the pixel changes, and thus the bias state of the transistor changes.

(6) In addition to the configurations (1) to (4), in the solid-state imaging device according to an embodiment of the present invention, when the pixel is in the non-read state, the drain potential of the transistor included in the pixel changes, and the bias state of the transistor changes.

(7) In addition to the configurations (1) to (4), the solid-state imaging device according to an embodiment of the present invention may be configured such that the control unit changes a potential of the gate electrode of the transistor included in the pixel when the pixel is in a non-read state.

Effects of the invention

According to one aspect of the present invention, it is possible to reduce 1/f noise by using the function of a general solid-state imaging element such as row selection control.

Drawings

Fig. 1 is a block diagram showing a configuration of a solid-state imaging element according to a first embodiment of the present invention.

Fig. 2 is a circuit diagram showing a configuration of a pixel circuit of the solid-state imaging device.

Fig. 3 is a flowchart showing an example of a reading method in the case of detecting X-rays by the solid-state imaging device.

Fig. 4 is a timing chart showing another example of the reading method in the case where the X-ray is detected by the solid-state imaging device.

Fig. 5 is a diagram illustrating 1/f noise reduction in the solid-state imaging device.

Fig. 6 is a graph showing the effect of reducing 1/f noise in the solid-state imaging element.

Fig. 7 is a circuit diagram showing a configuration of a pixel circuit of a solid-state imaging element according to a second embodiment of the present invention.

Fig. 8 is a circuit diagram showing a configuration of a pixel circuit of a solid-state imaging element according to a third embodiment of the present invention.

Fig. 9 is a circuit diagram showing a configuration of a pixel circuit of a solid-state imaging element according to a fourth embodiment of the present invention.

Fig. 10 is a cross-sectional view showing a solid-state imaging element according to a fifth embodiment of the present invention and showing a configuration example of a thin film transistor of a double gate.

Fig. 11 is a circuit diagram showing a configuration of a pixel circuit of the solid-state imaging element including the Amp transistor in which the thin film transistor is double-gated.

Detailed Description

[ first embodiment ]

An embodiment of the present invention will be described below with reference to fig. 1 to 6.

(outline of solid-state imaging element)

The structure of the solid-state imaging element 1A according to the present embodiment will be described with reference to fig. 1 and 2. Fig. 1 is a block diagram showing the configuration of a solid-state imaging element 1A. Fig. 2 is a circuit diagram showing the configuration of the pixel circuit 20A of the solid-state imaging element 1A. The solid-state imaging element 1A is an active pixel type solid-state imaging element, and can amplify an electric signal (charge) accumulated in a capacitor in a pixel.

As shown in fig. 1, the solid-state imaging element 1A includes an imaging sensor 10 and a control device (control unit) 30. The image sensor 10 includes an image sensor main body 11, a voltage generation section 12, a row selection section 13, and a reading section 14. Further, by connecting the display device 40 to the solid-state imaging element 1A, an imaging system capable of displaying an image output from the solid-state imaging element 1A on the display device 40 can be constructed.

The image sensor main body 11 includes a pixel array a including a plurality of pixels P arranged in a two-dimensional matrix, and a scintillator, not shown, covering the front surface of the array. In the present embodiment, the pixel array a is configured of 512 pixels P in the column direction and 512 pixels P in the row direction, for example. However, the number of pixels P in the column direction and the row direction in the pixel array a is not limited to this example. The scintillator has an X-ray light conversion function of receiving X-rays and converting the received X-rays into light.

The voltage generation unit 12 generates a voltage to be applied to the pixel P, and applies the generated voltage to each column. The row selection unit 13 selects rows to which the voltages generated by the voltage generation unit 12 are applied. The voltage generation section 12 applies a voltage to each column, and the row selection section 13 selects a row to which a voltage can be applied, thereby enabling voltage application in units of pixels P.

The reading section 14 reads an output from the pixel P and transmits the read output to the control device 30. The control device 30 controls the operation timing of the voltage generation section 12 and the row selection section 13. Then, the control device 30 outputs the information of the pixel P read by the reading unit 14 to the display device 40. The control device 30 can be constituted by, for example, an electric circuit.

(Pixel Circuit)

Next, a circuit configuration of the pixel P will be described with reference to fig. 2. Fig. 2 is a circuit diagram showing the configuration of the pixel circuit 20A. As shown in fig. 2, the pixel circuit 20A includes a reset switch RSTSW, a photodiode PD, an Amp transistor ATR, and a reed switch RSW.

The reset switch RSTSW is a switch for applying a reset voltage to the gate electrode G of the Amp transistor ATR. Here, the reset voltage is a voltage that resets the electric charge generated by the photodiode PD.

The output of the photodiode PD is connected to the gate electrode G of the Amp transistor ATR. Therefore, when the photodiode PD receives radiation and generates electric charges (electric signals), the voltage of the gate electrode G of the Amp transistor ATR connected to the photodiode PD changes.

The Amp transistor ATR is a transistor that amplifies the charge (electric signal) of the photodiode PD. Specifically, the Amp transistor ATR outputs a change in the voltage of the gate electrode G as a change in the current between the drain electrode D and the source electrode S. Since the power supply voltage Vdd is applied to the drain electrode D, the electric signal is amplified by the Amp transistor ATR. The Amp transistor ATR may be, for example, a Field Effect Transistor (FET).

The reed switch RSW is a switch for outputting a current between the source electrode S and the drain electrode D of the Amp transistor ATR to the outside of the pixel P, and is controlled by the reading unit 14 via the control device 30.

The current output from the pixel P is output to the reading unit 14, amplified by an afe (analog Front end) of the reading unit 14, and a/D-converted to be output to the control device 30.

(method of reading detection signal from photodiode: reference example)

An example of a reading method in the case of detecting X-rays in the pixel circuit 20A is described with reference to fig. 3. Fig. 3 is a flowchart showing an example of a method of reading a detection signal when detecting X-rays.

First, control device 30 sets a count value k equal to 0 as an initial setting (S1). Next, the control device 30 resets the photodiode PD using the reset switch RSTSW (S2). After the X-ray irradiation in this state, controller 30 opens reed switch RSW and outputs the drain voltage of Amp transistor ATR to reader 14 (S3), and performs an operation of adding 1 to count value k (k ═ k +1) (S3).

Next, control device 30 closes reed switch RSW to temporarily stop the output to reader 14, and resets Amp transistor ATR (S5). The reset at S5 is to switch the Amp transistor ATR in the read state (ON state) to the non-read state (OFF state).

After that, controller 30 opens reed switch RSW again, and outputs the drain voltage of Amp transistor ATR to reader 14 (S6). Then, after repeating S4, S5, and S6 n times (S7), controller 30 averages the read voltages read n times (S8).

Here, in the Amp transistor ATR, there is no correlation between noise before reset and noise after reset. Therefore, in the processing of S8, the noise having no correlation is added. Thus, the noise can be reduced by increasing the number of times of reading n. As a result, the influence of low-frequency noise can be further reduced.

(method of reducing 1/f noise)

Next, a method of reducing 1/f noise of Amp transistor ATR by changing the bias state of Amp transistor ATR using the reset function of Amp transistor ATR will be described with reference to fig. 4. Fig. 4 is a timing chart showing another example of the reading method in the case of detecting X-rays by the solid-state imaging element 1A. Fig. 4 shows the operation of the pixels P in N (N > 2) rows in the 512-row pixel array a.

Here, the 1/f noise of the Amp transistor ATR is the largest among the noises. The 1/f noise cannot be reduced even if the measurement time is extended. Therefore, in the present embodiment, 1/f noise reduction of the Amp transistor ATR is achieved as follows.

First, as shown in fig. 4 a, in a reset period t1 (before X-ray exposure), control device 30 resets photodiode PD using reset switch RSTSW. In the period t1, the control device 30 sequentially resets the photodiodes PD in the pixels P in the 1 st row (N ═ 1) to the 512 th row (N ═ 512).

Specifically, control device 30 resets photodiode PD by setting reset switch RSTSW to the on state (setting the reset signal to "H"). When the photodiode PD is reset, the reed switch RSW also turns on the reed signal at "H" as shown in fig. 4 (b). This is to take into account that when the transistor changes in operating state, control takes time for the characteristics to stabilize.

If the reed signal is not set to "H" in the period t1, the operating states of the Amp transistor ATR and the reed switch RSW change at the start time of the reading period. Therefore, the characteristics of the Amp transistor ATR and the reed switch RSW at the i-th reading time and the i + 1-th reading time are different. Thus, the difference between the i-th and i + 1-th readings also occurs.

On the other hand, as shown in fig. 4 (b), when the reed signal is set to "H" in the period t1, the Amp transistor ATR and the reed switch RSW continue to perform a constant operation cycle even at the reading start time, and thus the characteristics are stable. That is, by setting the reed signal to "H" for a sufficient period t1 until the characteristics are stabilized, it is possible to prevent a difference between the i-th reading result and the i + 1-th reading result due to the characteristic variation of the Amp transistor ATR and the reed switch RSW.

When the reset of the photodiodes PD in the 1 st row (N is 1) to the 512 th row (N is 512) is completed, the control device 30 controls the row selection unit 13 to scan the information held in each pixel P N times (N is an integer equal to or greater than 2). In fig. 4 (b), a period during which one scan is performed is shown as t 2. The scanning is performed in the following manner: the reed switch RSW is turned on in order from row 1 (N ═ 1) to row 512 (N ═ 512).

In this scan, when the N-th row reed switch RSW is turned ON (the reed signal is "H"), the source potential of the Amp transistor ATR of each pixel P in the N-th row changes, and the Amp transistor ATR is turned ON. Thus, the current (nth row electric signal) from each pixel P in the nth row is output to the AFE (not shown) via the reading unit 14. The AFE amplifies the current, performs a/D conversion, and outputs the current to the control device 30.

On the other hand, when the reed switch RSW of the nth row is turned on, the reed switches RSW other than the nth row are turned on (the reed signal is "L"). Thereby, the Amp transistor ATR of each pixel P other than the nth row is turned OFF.

That is, in each pixel P in the nth row, until the nth row reed switch RSW turns on in the period t2, the Amp transistor ATR turns OFF, and when the nth row reed switch RSW turns on, the source potential of the Amp transistor ATR changes, and the bias state of the Amp transistor ATR changes. When the N-th row reed switch RSW is again returned to the non-conductive state, the source potential of the Amp transistor ATR changes, and the bias state of the Amp transistor ATR changes.

When the scanning of the pixels P from the 1 st row to the 512 th row is completed in this way, the control device 30 performs the second scanning of the pixels P from the 1 st row to the 512 th row by the same control as described above. Here, in the period t2 in which one scan is performed, the period in which the row N reed switch RSW is in the conductive state is sufficiently shorter than the period in which the row N reed switch RSW is in the non-conductive state. Therefore, the Amp transistor ATR in each row of pixels P is biased to the OFF state for a sufficiently long time with respect to the reading period (period in which the state is turned ON). As a result, the temporal correlation between the 1/f noise included in the output current value when Amp transistor ATR in each row of pixels P is again biased to the ON state and the 1/f noise included in the output current value immediately before the Amp transistor ATR is biased to the ON state is reduced.

Then, control device 30 calculates an output value corresponding to the n-time reading result of the information held in each pixel P. For example, control device 30 may calculate an arithmetic average of output current values obtained by n scans as the output value. In this manner, since control device 30 performs calculation based on the results of a plurality of readings with low correlation of 1/f noise, it is possible to calculate an output value with reduced 1/f noise.

As described above, after the information (electric charge) held by each pixel P is read n times after reset, X-ray irradiation is performed (time t3 in fig. 4). Thereby, the information (electric charge) held by the pixel P is updated. After the X-ray irradiation, the control device 30 controls the row selecting unit 13 to perform n-time scanning of the information held in each pixel P. In fig. 4 (b), a period during which one scan is performed after the X-ray irradiation is represented by t 4.

The n scans after the X-ray irradiation are the same as the n scans before the irradiation. Since a plurality of reading results having low correlation with 1/f noise can be obtained by n scans after X-ray irradiation, the control device 30 calculates an output value corresponding to the reading result. Then, the control device 30 calculates a difference between output values before and after the X-ray irradiation and outputs the calculated value. The timing of calculating the average value is not particularly limited, and for example, the average value before X-ray irradiation and the average value after irradiation may be calculated at the end of 2n scans.

As described above, the solid-state imaging element 1A includes the pixel array a in which a plurality of columns of pixels P are arranged and the row selection section 13 that specifies the read row of the pixel array a. The control device 30 in the solid-state imaging element 1A controls the row selection unit 13 to scan the information held in each pixel P a plurality of times, and outputs an output value corresponding to a result of reading the information from each pixel P a plurality of times obtained by the scanning. Thus, the output value with reduced 1/f noise can be output by the control of the row selecting section 13 without adding a new circuit or control.

(correction of leakage)

Fig. 4 (c) shows a change in the output current of the nth row pixel P. When the photodiode PD has a current leak, the output current decreases with time during 2n times of reading as shown in the figure. More specifically, in one reading, a gate voltage change and an output current change are generated as a value obtained by dividing the charge obtained by integrating the leakage current at the reading interval by the capacitance of the photodiode PD.

Therefore, control device 30 may calculate the average value after correcting the leakage of the electric charge generated during the plurality of scans. For example, information indicating a pattern of variation in output current due to leakage may be used for the correction. As this information, for example, an approximate curve showing a pattern of fluctuation of the output current can be cited. Control device 30 performs correction to remove the amount of output change due to the leakage current from the output values calculated as described above using the approximate curve, and outputs an output value from which the influence of the leakage current is removed.

The correction may be performed based on a leakage amount measured in advance using the solid-state imaging element 1A. In this case, a change in the output current value due to the leakage current in the solid-state imaging element 1A is acquired and stored in a dark state or the like in advance. Then, based on the stored pattern of change in the output current value, control device 30 performs correction to remove the amount of change in output due to the leakage current from the output value calculated as described above. This can remove the influence of the leakage current on the output value with higher accuracy.

(Explanation of Effect)

The operation and effect of the solid-state imaging element 1A according to the present embodiment for reducing 1/f noise will be described based on fig. 5 (a) to (e) and fig. 6. Fig. 5 is a diagram illustrating reduction of 1/f noise in the solid-state imaging element 1A.

When the solid-state imaging element 1A is a CMOS Active Pixel Sensor (APS), the 1/f noise generated by the Amp transistor ATR is the largest among the generated noises. The 1/f noise cannot be reduced even if the measurement time is extended, and becomes an obstacle to noise reduction. When 1/f noise is dominant, for example, as shown in fig. 5 (a) and (b), the S/N ratio is not improved even if the time (the length of the period for turning ON the Amp transistor ATR) from the start to the stop thereof is extended. This is due to the influence of lower frequency and greater noise, i.e., 1/f noise. For the same reason, the 1/f noise cannot be reduced even if the number of measurements is increased.

As a method of reducing 1/f noise, a method of resetting the Amp transistor ATR, which is a main generation source of 1/f noise, is considered. This is because 1/f noise included in the output current value from the Amp transistor ATR has no correlation (or has a small correlation) before and after reset. That is, by calculating the average value of such a plurality of output current values having no correlation, it is possible to accumulate noise having no correlation and reduce the influence of low-frequency noise.

For example, as shown in fig. 5 (d), a configuration may be considered in which the operation of the Amp transistor ATR is reset a plurality of times during the reading period of one frame. However, since the read period is as short as about 100 μ sec, for example, it is assumed that it is physically difficult to reset the read period by the number of times that the 1/f noise can be sufficiently removed.

Further, it can be assumed that, when the solid-state imaging element 1A is applied to, for example, an imaging element using a TFT element on a glass panel, even if the bias state is cycled within the reading period of one frame as described above, the state inside the element does not sufficiently follow the cycle control. That is, it can be assumed that since the reading period is short, the next cycle of control is performed when the bias state of the Amp transistor ATR does not change completely, and as a result, it is difficult to obtain a sufficient 1/f noise removal effect.

Therefore, as shown in fig. 5 (e), the solid-state imaging element 1A is configured such that the Amp transistor ATR is reset during the non-reading period of one frame. Here, one frame is a period for reading all rows, and a period obtained by multiplying a time required for reading one row by the number of rows is, for example, about 50 msec.

As described above, the Amp transistor ATR included in each row of pixels P is turned ON when the row is to be read, and is otherwise turned OFF. That is, the Amp transistor ATR becomes the ON state once in one frame, and then transits to the OFF state to be reset. Therefore, by averaging the output current values read from 1 to N frames, the 1/f noise can be reduced, and the S/N ratio can be improved.

(results of experiments)

Fig. 6 is a graph (solid line) showing the effect of reducing 1/f noise in the solid-state imaging element 1A. In addition, fig. 6 also shows a straight line (broken line) having an inclination of 1/sqrt (n). In fig. 6, the abscissa indicates the number of repeated readings (n), and the ordinate indicates the magnitude of noise (1/f noise) included in the output, specifically, a value obtained by converting the noise into the number of electrons generated in the photodiode PD. As shown in the figure, the 1/f noise in the solid-state imaging element 1A is substantially proportional to 1/sqrt (n) when the number of repeated reading (n) is 10 or less. From the results, it is preferable to set the number of repeated reading to, for example, 8 to 30 times, because 1/f noise can be suppressed to a low level.

[ second embodiment ]

Another embodiment of the present invention will be described below with reference to fig. 7. The configuration other than the configuration described in the present embodiment is the same as that of the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanations thereof are omitted.

The pixel circuit 20B of the solid-state imaging element 1B according to the present embodiment differs from the pixel circuit 20A of the solid-state imaging element 1A according to the first embodiment in that an SD short-circuit transistor SDTR for turning on and off the connection between the drain electrode D and the source electrode S of the Amp transistor ATR is provided, and the offset state of the source potential of the Amp transistor ATR is changed by this configuration.

The configuration of the pixel circuit 20B of the solid-state imaging element 1B will be described with reference to fig. 7. Fig. 7 is a circuit diagram showing the configuration of the pixel circuit 20B of the solid-state imaging element 1B.

As shown in fig. 7, the pixel circuit 20B includes an SD short-circuit transistor SDTR that opens and closes a connection between the drain electrode D and the source electrode S of the Amp transistor ATR. As a result, in the solid-state imaging element 1B, the connection between the drain electrode D and the source electrode S can be made and broken by the transistors of the Amp transistor ATR and/or the SD short-circuit transistor SDTR.

In the pixel circuit 20B of the solid-state imaging element 1B, the SD short-circuit transistor SDTR is turned off during the reading period. As a result, during the reading period, the connection between the drain electrode D and the source electrode S is turned on by the Amp transistor ATR, and the source electrode S of the Amp transistor ATR is biased in the same manner as in the first embodiment. On the other hand, in the non-read period, the Amp transistor ATR is off, and the SD short-circuit transistor SDTR is on. Thereby, the potential difference between the drain electrode D and the source electrode S of the Amp transistor ATR becomes 0, and the bias state of the Amp transistor ATR in the non-reading period becomes a state different from the reading period. Therefore, as in the first embodiment, the bias state of the source electrode S of the Amp transistor ATR can be changed to reduce 1/f noise.

[ third embodiment ]

Another embodiment of the present invention will be described below with reference to fig. 8. The configuration other than the configuration described in the present embodiment is the same as that of the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanations thereof are omitted.

The pixel circuit 20C of the solid-state imaging element 1C according to the present embodiment differs from the pixel circuit 20A of the solid-state imaging element 1A according to the first embodiment in that a switching unit 21 for switching the drain voltage of the Amp transistor ATR is provided to change the bias state of the drain potential.

The configuration of the pixel circuit 20C of the solid-state imaging device 1C will be described with reference to fig. 8. Fig. 8 is a circuit diagram showing the configuration of the pixel circuit 20C of the solid-state imaging element 1C.

As shown in fig. 8, the switching section 21 includes a first transistor 21a and a second transistor 21 b. The first transistor 21a is a TFT having one end connected to the drain electrode D of the Amp transistor ATR and the other end connected to the power supply voltage Vdd. The second transistor 21b is a TFT having one end connected to the drain electrode D of the Amp transistor ATR and the other end grounded.

In the pixel circuit 20C of the solid-state imaging element 1C, the Amp transistor ATR is biased in the same manner as in the first embodiment during the reading period. On the other hand, in the non-reading period, the Amp transistor ATR is in a different bias state from the Amp transistor ATR in the pixel circuit 20A of the solid-state imaging element 1A.

Specifically, in the reading period, control device 30 turns ON first transistor 21a and turns OFF second transistor 21b in switching unit 21. Thus, the power supply voltage Vdd is applied to the drain electrode D in the Amp transistor ATR, and the read current amplified in accordance with the received light voltage of the photodiode PD flows between the drain electrode D and the source electrode S and is output to the reading unit 14.

On the other hand, in the non-Read period, control device 30 controls switching unit 21 to release the Read signal (Read) and the inverted signal (XRead) of the Read signal, and thereby connects Amp transistor ATR to the ground potential by releasing it from power supply voltage Vdd. That is, control device 30 sets first transistor 21a to the ON state and sets second transistor 21b to the OFF state. Thereby, the potential of the drain electrode D of the Amp transistor ATR becomes 0, and the bias state of the Amp transistor ATR becomes a state different from the read period.

As described above, in the solid-state imaging element 1C according to the present embodiment, when a pixel P is in a non-read state, the drain potential of the Amp transistor ATR included in the pixel P changes, and the bias state of the Amp transistor ATR changes. With such a circuit configuration and control, the bias state of the Amp transistor ATR can be changed between the read period and the non-read period. Therefore, by performing scanning a plurality of times in the same manner as in the first embodiment, an output value corresponding to the result of reading a plurality of times is output, and 1/f noise can be reduced.

[ fourth embodiment ]

Another embodiment of the present invention is described below with reference to fig. 9. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanations thereof are omitted.

The pixel circuit 20D of the solid-state imaging element 1D according to the present embodiment differs from the solid-state imaging element 1A according to the first embodiment in that a capacitance C is added between the signal terminal Ctrl and the gate electrode G of the Amp transistor ATR, and the bias state of the gate potential is changed.

The configuration of the pixel circuit 20D of the solid-state imaging device 1D will be described with reference to fig. 9. Fig. 9 is a circuit diagram showing the configuration of the pixel circuit 20D of the solid-state imaging element 1D in the present embodiment. In the pixel circuit 20D, the bias state of the Amp transistor ATR in the non-reading period is different from that in the first embodiment. In the reading period, the offset is the same as that in the first embodiment.

Specifically, control device 30 sets the voltage value applied to signal terminal Ctrl to a value different from the value during the read period in the non-read period. This enables the voltage of the gate electrode G to be changed between the read period and the non-read period. For example, when the capacitance value of the additional capacitance C is Cctrl, the capacitance of the gate electrode G is Cg, and the voltage of the signal terminal Ctrl is changed by Vctrl, the change V in the voltage of the gate electrode G can be calculated as follows.

V＝Vctrl×(Cctrl/(Cctrl+Cg))

In this manner, in the solid-state imaging element 1D according to the present embodiment, when a pixel P is in a non-read state, the control device 30 changes the potential of the gate electrode G of the Amp transistor ATR included in the pixel P. Thus, the bias state of the Amp transistor ATR can be changed to a larger extent because the bias state changes due to a change in the potential of the gate electrode G in addition to a change in the bias state due to a change in the source voltage caused by turning off the reed switch RSW. Therefore, by performing scanning a plurality of times and outputting an output value corresponding to the result of reading a plurality of times as in the first embodiment, 1/f noise can be further reduced.

[ fifth embodiment ]

Still another embodiment of the present invention will be described below with reference to fig. 10 and 11. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanations thereof are omitted.

In the pixel circuit 20D of the solid-state imaging element 1D according to the fourth embodiment, the capacitance C is connected to the gate electrode G to change the gate potential, but the gate potential may be changed by a method different from that of the pixel circuit 20D. For example, the gate potential may be changed by using a different kind of Amp transistor ATR.

As the Amp transistor ATR, for example, a double-gate thin film transistor can be used. Fig. 10 is a cross-sectional view showing an example of the configuration of the double-gate thin film transistor 50.

As shown in fig. 10, the dual-gate thin film transistor 50 includes a glass 51, a bottom gate BG made of molybdenum or the like, a first oxide film 52 made of silicon nitride or the like, a channel 53 made of InGaZnO or the like, a drain 54 made of molybdenum or the like, a source 55 made of molybdenum or the like, a second oxide film 56 made of silicon oxide or the like, and a top gate TG made of molybdenum or the like. As a result, the double-gate thin film transistor 50 is a thin film transistor in which a top gate TG is arranged on the upper layer of the channel 53 in addition to the bottom gate BG on the lower layer of the channel 53.

The pixel circuit 20F of the solid-state imaging element 1F according to the present embodiment includes the Amp transistor ATR using the double-gate thin film transistor 50. The configuration of the pixel circuit 20F of the solid-state imaging device 1F will be described with reference to fig. 11. Fig. 11 is a circuit diagram showing the configuration of a pixel circuit 20F of a solid-state imaging element 1F including an Amp transistor using a double-gate thin film transistor 50.

When the double-gate thin film transistor 50 is used as the Amp transistor ATR, the bottom gate BG is connected to the photodiode PD as shown in fig. 11. On the other hand, different voltages are applied to the top gate TG during the reading period and the non-reading period. This enables the bias state in the gate potential of the Amp transistor ATR to be changed more greatly.

[ modified example ]

In the above embodiments, the solid-state imaging devices 1A to 1F for imaging an X-ray image are exemplified for description, but the application object of the solid-state imaging device of the present invention is not limited to this example.

[ conclusion ]

A solid-state imaging element according to a first aspect of the present invention includes: a pixel array in which a plurality of rows of pixels are arranged; a row selecting section that designates a read row of the pixel array; and a control unit that controls the row selection unit to scan the information held by each pixel a plurality of times and output an output value corresponding to a result of reading the information from each pixel a plurality of times, the result being obtained by the scanning.

According to the above configuration, the information held by each pixel is scanned a plurality of times by controlling the row selection section, but in this scanning, when a pixel of a row that is not a reading target becomes a reading target, the bias state of the transistor included in the pixel changes. Thereby, a plurality of reading results having no correlation with respect to 1/f noise can be obtained by a plurality of scans. Further, according to the above configuration, since the output value corresponding to the result of the multiple reading is output, the output value with reduced 1/f noise can be output by the function of the normal solid-state imaging element such as row selection control.

In the solid-state imaging device according to the second aspect of the present invention, the control unit may output an average value of the reading results obtained by the plurality of scans as the output value. Thus, the output value with reduced 1/f noise can be output by a simple calculation.

In the solid-state imaging device according to the third aspect of the present invention, the control unit may correct leakage of electric charges generated during the plurality of scanning periods and then calculate the average value. Thereby enabling an accurate output value to be output.

In the solid-state imaging device according to the fourth aspect of the present invention, the control unit may perform the correction based on a leakage amount measured in advance using the solid-state imaging device. This enables highly accurate correction.

In the solid-state imaging device according to the fifth aspect of the present invention, when the pixel is in the non-read state, the source potential of the transistor included in the pixel may change, and the bias state of the transistor may change. Thus, the bias state of the transistor can be changed without adding a new circuit or control, and an output value with reduced 1/f noise can be output.

In the solid-state imaging device according to the sixth aspect of the present invention, when the pixel is in the non-read state, the bias state of the transistor may be changed by changing the drain potential of the transistor included in the pixel. Even with such a configuration, the bias state of the transistor can be changed every time scanning is performed, and thus an output value with reduced 1/f noise can be output.

In the solid-state imaging device according to the seventh aspect of the present invention, the control unit may change a potential of a gate electrode of a transistor included in the pixel when the pixel is in a non-read state. Thereby enabling to enhance the variation of the bias state of the transistor in the read state and the non-read state. This can further reduce 1/f noise.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention. Further, it is possible to form new technical features by combining the technical means disclosed in the respective embodiments.

Description of the reference numerals

1A to 1F: solid-state image pickup device

13: line selection section

30: control device (control part)

A: pixel array

ATR: amp transistor (transistor)

P: pixel

Claims

1. A solid-state imaging element, comprising:

a pixel array in which a plurality of rows of pixels are arranged;

a row selecting section that designates a read row of the pixel array; and

and a control unit that controls the row selection unit to scan the information held by each pixel a plurality of times and output an output value corresponding to a result of reading the information from each pixel a plurality of times, the result being obtained by the scanning.

2. The solid-state imaging element according to claim 1,

the control section outputs an average value of the reading results obtained by the plurality of scans as the output value.

3. The solid-state imaging element according to claim 2,

the control unit calculates the average value after correcting leakage of electric charge generated during a plurality of times of the scanning.

4. The solid-state imaging element according to claim 3,

the control unit performs the correction based on a leakage amount measured in advance using the solid-state imaging element.

5. The solid-state imaging element according to claim 1,

when the pixel is in a non-read state, the source potential of the transistor included in the pixel changes, and the bias state of the transistor changes.

6. The solid-state imaging element according to claim 1,

when the pixel is in a non-read state, the drain potential of the transistor included in the pixel changes, and the bias state of the transistor changes.

7. The solid-state imaging element according to claim 1,

the control unit changes the potential of the gate electrode of the transistor included in the pixel when the pixel is in a non-read state.