CN111384016A - Wafer bump and method for manufacturing wafer bump - Google Patents
Wafer bump and method for manufacturing wafer bump Download PDFInfo
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- CN111384016A CN111384016A CN201811629014.4A CN201811629014A CN111384016A CN 111384016 A CN111384016 A CN 111384016A CN 201811629014 A CN201811629014 A CN 201811629014A CN 111384016 A CN111384016 A CN 111384016A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
Abstract
The invention provides a wafer bump and a manufacturing method thereof, wherein the wafer bump comprises a semiconductor substrate positioned at the bottom, a circuit layer positioned on the semiconductor substrate, a first metal layer and a second metal layer positioned above the circuit layer, the first metal layer is positioned between the second metal layer and the circuit layer, the wafer bump further comprises a first photoresist arranged around the side surface of the first metal layer, and an isolation layer positioned between the first metal layer and the circuit layer, and the height of the first photoresist is not lower than that of the first metal layer. The wafer bump of the invention can prevent the first metal layer from being oxidized. The manufacturing method of the wafer bump is simple in process, and the manufactured wafer bump is high in oxidation resistance and capable of resisting the galvanic effect caused by the potential difference between two metals.
Description
Technical Field
The invention relates to a wafer bump and a manufacturing method thereof, which aim to solve the problems that a metal layer on the wafer bump is easy to oxidize and a galvanic effect is generated due to the existence of different metals.
Background
The existing wafer bump metal is exposed and easily oxidized, thereby affecting the product characteristics. In addition, different metal layers are arranged on the wafer bump, and due to the potential difference, different metals generate current through the medium, so that electrochemical reaction is generated, partial metals are oxidized, namely, a galvanic effect is generated, and the use reliability of the product is influenced.
Accordingly, there is a need for an improved wafer bump and a method for manufacturing the same to solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a wafer bump and a manufacturing method of the wafer bump, so as to solve the problem that metal on the conventional wafer bump is easily oxidized.
In order to achieve the above object, the present invention provides a wafer bump, where the wafer bump includes a semiconductor substrate located at the bottom, a circuit layer located on the semiconductor substrate, and a first metal layer and a second metal layer located above the circuit layer, the first metal layer is located between the second metal layer and the circuit layer, the wafer bump further includes a first photoresist disposed around a side surface of the first metal layer, and an isolation layer located between the first metal layer and the circuit layer, and a height of the first photoresist is not lower than a height of the first metal layer.
As a further improvement of the present invention, the wafer bump further includes a protection layer, the protection layer is higher than the circuit layer, and the circuit layer is embedded in the protection layer and exposed from the protection layer.
As a further improvement of the present invention, the first metal layer includes a first portion and a second portion connected to each other, the first portion is located below the second portion, a bottom surface of the first portion is in contact with the wiring layer, a side surface of the first portion is in contact with the protective layer, a cross-sectional area of the second portion is larger than a cross-sectional area of the first portion, a bottom surface of the second portion is connected to the first portion and in contact with the protective layer, and a side surface of the second portion is in contact with the first photoresist.
As a further improvement of the present invention, the wafer bump further includes an isolation layer located between the first metal layer and the protection layer and between the first metal layer and the first photoresist.
As a further improvement of the invention, the material of the isolation layer is titanium tungsten copper or titanium copper.
As a further improvement of the present invention, the material of the first metal layer is copper.
As a further improvement of the present invention, the second metal layer includes a nickel layer located below and a gold layer located above, and the thicknesses of the nickel layer and the gold layer are both smaller than that of the first metal layer.
The invention also provides a manufacturing method of the wafer bump, which comprises the following steps:
s1: providing a wafer substrate, wherein the wafer substrate comprises a semiconductor base material, a circuit layer and a protective layer, the circuit layer is positioned on the semiconductor base material, the height of the protective layer is higher than that of the circuit layer, and the circuit layer is embedded in the protective layer and is exposed from the protective layer;
s2: uniformly coating a first photoresist on the protective layer, and exposing and developing to at least partially expose the circuit layer exposed from the protective layer;
s3: sputtering an isolation layer to cover the first photoresist, the protection layer and the circuit layer;
s4: uniformly coating a second photoresist above the first photoresist, and exposing and developing to expose the protective layer exposed by the first photoresist;
s5: electroplating a first metal layer and a second metal layer upwards from the circuit layer, so that the height of the first metal layer is lower than that of the first photoresist;
s6: the second photoresist and the exposed barrier layer are etched away.
As a further improvement of the present invention, the first metal layer is a copper layer, the second metal layer includes a nickel layer located below and a gold layer located above, and the thicknesses of the nickel layer and the gold layer are both smaller than the thickness of the copper layer.
As a further improvement of the invention, the material of the isolation layer is titanium tungsten copper or titanium copper.
The invention has the beneficial effects that: according to the wafer bump, the first photoresist is arranged, so that the first metal layer can be prevented from being oxidized, and the galvanic effect caused by arrangement of different metals can also be prevented; through setting up the isolation layer, made things convenient for first metal layer of electroplating and second metal layer promptly, can isolate metal migration in addition. The manufacturing method of the wafer bump has simple process, and the manufactured wafer bump has high oxidation resistance.
Drawings
Fig. 1 is a cross-sectional view of the wafer bump manufacturing method after step S1 is completed;
fig. 2 is a cross-sectional view of the wafer bump manufacturing method after step S2 is completed;
fig. 3 is a cross-sectional view of the wafer bump manufacturing method after step S3 is completed;
fig. 4 is a cross-sectional view of the wafer bump manufacturing method after step S4 is completed;
fig. 5 is a cross-sectional view of the wafer bump manufacturing method after step S5 is completed;
fig. 6 is a cross-sectional view of the structure after step S6 is completed in the method for manufacturing wafer bumps according to the present invention, and is also a cross-sectional view of the wafer bumps according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 6, the wafer bump 100 of the present invention includes a semiconductor substrate 1 at the bottom, a protection layer 7 on the semiconductor substrate 1, a circuit layer 2 embedded in the protection layer 7 and exposed from the protection layer 7, a first metal layer 3 and a second metal layer 4 on the circuit layer 2, a first photoresist 5 surrounding the side of the first metal layer 3, and an isolation layer 6.
The material of the semiconductor substrate 1 may be silicon or gallium arsenide or the like.
The height of the protective layer 7 is higher than that of the circuit layer 2, an exposed space is formed in the middle of the protective layer 7, and the circuit layer 2 is exposed from the exposed space.
The first metal layer 3 is located between the second metal layer 4 and the circuit layer 2, and the height of the first photoresist 5 is not lower than that of the first metal layer 3.
The first metal layer 3 includes a first portion 32 and a second portion 31 connected to each other, the first portion 32 is located below the second portion 31, a bottom surface of the first portion 32 abuts against the circuit layer 2, a side surface of the first portion 32 abuts against the protective layer 7, a cross-sectional area of the second portion 31 is larger than a cross-sectional area of the first portion 32, a bottom surface of the second portion 31 is connected to the first portion 32 and abuts against the protective layer 7, and a side surface of the second portion 31 abuts against the first photoresist 5.
The first photoresist 5 is an organic colloid, and the first photoresist 5 is disposed on the side surface of the first metal layer 3, so that the effect of preventing the first metal layer 3 from being oxidized is achieved.
The material of the first metal layer 3 is copper. The second metal layer 4 comprises a nickel layer 41 positioned below and a gold layer 42 positioned above, and the thicknesses of the nickel layer 41 and the gold layer 42 are both smaller than that of the first metal layer 3. Since copper is easily oxidized, the present invention provides the first photoresist 5 to prevent oxidation.
The isolation layer 6 is located between the first metal layer 3 and the protection layer 7, between the first metal layer 3 and the first photoresist 5, and between the first metal layer 3 and the circuit layer 2. The material of the isolation layer 6 is titanium tungsten copper or titanium copper. The isolation layer 6 is provided to perform a conductive function, so that the first metal layer 3 and the second metal layer 4 can be electroplated, and the isolation layer 6 can also perform an effect of isolating metal migration.
The manufacturing method of the wafer bump comprises the following steps:
s1: providing a wafer substrate, wherein the wafer substrate comprises a semiconductor substrate 1, a circuit layer 2 and a protective layer 7, the circuit layer 2 is located on the semiconductor substrate 1, the height of the protective layer 7 is higher than that of the circuit layer 2, the circuit layer 2 is embedded in the protective layer 7 and is exposed from the protective layer 7, as shown in fig. 1;
s2: uniformly coating a first photoresist 5 on the protective layer 7, and exposing and developing to expose at least a portion, in this embodiment, completely expose the circuit layer 2 exposed from the protective layer 7, as shown in fig. 2;
s3: sputtering an isolation layer 6 to cover the first photoresist 5, the protection layer 7 and the circuit layer 2, wherein the isolation layer 6 is made of titanium tungsten copper or titanium copper, as shown in fig. 3;
s4: uniformly coating a second photoresist 8 on the first photoresist 5, and exposing and developing to expose the protective layer 7 exposed from the first photoresist 5, as shown in fig. 4;
s5: electroplating a first metal layer 3 and a second metal layer 4 upwards from the circuit layer 2, so that the height of the first metal layer 3 is lower than that of the first photoresist 5, the first metal layer 3 is a copper layer, the second metal layer 4 comprises a nickel layer 41 positioned below and a gold layer 42 positioned above, and the thicknesses of the nickel layer 41 and the gold layer 42 are both smaller than that of the copper layer, as shown in fig. 5;
s6: the second photoresist 8 and the exposed isolation layer 6 are etched away to form the wafer bump 100, as shown in fig. 6. The etching solution is used for etching, and the etching solution only reacts with the second photoresist 8 and the isolation layer 6.
According to the wafer bump 100, the first photoresist 5 is arranged, so that the first metal layer 3 can be prevented from being oxidized, and the galvanic effect caused by arrangement of different metals can also be prevented; by providing the barrier layer 6, it is convenient to electroplate the first metal layer 3 and the second metal layer 4, and it is also possible to isolate metal migration. The manufacturing method of the wafer bump has simple process, and the manufactured wafer bump 100 has high oxidation resistance.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
Claims (10)
1. A kind of wafer bump, characterized by: the wafer bump comprises a semiconductor substrate located at the bottom, a circuit layer located on the semiconductor substrate, a first metal layer and a second metal layer, wherein the first metal layer is located above the circuit layer, the second metal layer is located between the circuit layer, the wafer bump further comprises a first photoresist surrounding the side face of the first metal layer, an isolation layer located between the first metal layer and the circuit layer, and the height of the first photoresist is not lower than that of the first metal layer.
2. The wafer bump as recited in claim 1, wherein: the wafer bump further comprises a protective layer, the height of the protective layer is higher than that of the circuit layer, and the circuit layer is embedded in the protective layer and exposed from the protective layer.
3. The wafer bump as recited in claim 2, wherein: the first metal layer comprises a first part and a second part which are connected, the first part is located below the second part, the bottom surface of the first part is abutted with the circuit layer, the side surface of the first part is abutted with the protective layer, the cross-sectional area of the second part is larger than that of the first part, the bottom surface of the second part is connected with the first part and abutted with the protective layer, and the side surface of the second part is abutted with the first photoresist.
4. The wafer bump as recited in claim 3, wherein: the wafer bump further comprises an isolation layer positioned between the first metal layer and the protection layer and between the first metal layer and the first photoresist.
5. The wafer bump as recited in claim 4, wherein: the isolation layer is made of titanium-tungsten-copper or titanium-copper.
6. The wafer bump as recited in claim 1, wherein: the first metal layer is made of copper.
7. The wafer bump as recited in claim 6, wherein: the second metal layer comprises a nickel layer positioned below and a gold layer positioned above, and the thicknesses of the nickel layer and the gold layer are both smaller than that of the first metal layer.
8. A method for manufacturing wafer bumps is characterized in that: the manufacturing method of the wafer bump comprises the following steps:
s1: providing a wafer substrate, wherein the wafer substrate comprises a semiconductor base material, a circuit layer and a protective layer, the circuit layer is positioned on the semiconductor base material, the height of the protective layer is higher than that of the circuit layer, and the circuit layer is embedded in the protective layer and is exposed from the protective layer;
s2: uniformly coating a first photoresist on the protective layer, and exposing and developing to at least partially expose the circuit layer exposed from the protective layer;
s3: sputtering an isolation layer to cover the first photoresist, the protection layer and the circuit layer;
s4: uniformly coating a second photoresist above the first photoresist, and exposing and developing to expose the protective layer exposed by the first photoresist;
s5: electroplating a first metal layer and a second metal layer upwards from the circuit layer, so that the height of the first metal layer is lower than that of the first photoresist;
s6: the second photoresist and the exposed barrier layer are etched away.
9. The method for manufacturing wafer bumps as claimed in claim 8, wherein: the first metal layer is a copper layer, the second metal layer comprises a nickel layer located below and a gold layer located above, and the thicknesses of the nickel layer and the gold layer are both smaller than those of the copper layer.
10. The method for manufacturing wafer bumps as claimed in claim 8, wherein: the isolation layer is made of titanium-tungsten-copper or titanium-copper.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811629014.4A CN111384016A (en) | 2018-12-28 | 2018-12-28 | Wafer bump and method for manufacturing wafer bump |
| PCT/CN2019/119122 WO2020134700A1 (en) | 2018-12-28 | 2019-11-18 | Wafer bumping and wafer bumping manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811629014.4A CN111384016A (en) | 2018-12-28 | 2018-12-28 | Wafer bump and method for manufacturing wafer bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111384016A true CN111384016A (en) | 2020-07-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811629014.4A Withdrawn CN111384016A (en) | 2018-12-28 | 2018-12-28 | Wafer bump and method for manufacturing wafer bump |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111384016A (en) |
| WO (1) | WO2020134700A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764113A (en) * | 2008-12-25 | 2010-06-30 | 俞宛伶 | Metal protruding block structure on connecting pad of circuit surface of semiconductor element and forming method |
| CN102315188A (en) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | Forming method for semiconductor pipe core and conductive pillar |
| CN102456653A (en) * | 2010-10-18 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Under-bump metallization (ubm) structure and method of forming the same |
| CN102543895A (en) * | 2010-12-21 | 2012-07-04 | 南茂科技股份有限公司 | Bump structure and manufacturing method thereof |
| CN105632953A (en) * | 2010-05-12 | 2016-06-01 | 台湾积体电路制造股份有限公司 | Method of fabricating bump structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8232193B2 (en) * | 2010-07-08 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming Cu pillar capped by barrier layer |
-
2018
- 2018-12-28 CN CN201811629014.4A patent/CN111384016A/en not_active Withdrawn
-
2019
- 2019-11-18 WO PCT/CN2019/119122 patent/WO2020134700A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764113A (en) * | 2008-12-25 | 2010-06-30 | 俞宛伶 | Metal protruding block structure on connecting pad of circuit surface of semiconductor element and forming method |
| CN105632953A (en) * | 2010-05-12 | 2016-06-01 | 台湾积体电路制造股份有限公司 | Method of fabricating bump structure |
| CN102315188A (en) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | Forming method for semiconductor pipe core and conductive pillar |
| CN102456653A (en) * | 2010-10-18 | 2012-05-16 | 台湾积体电路制造股份有限公司 | Under-bump metallization (ubm) structure and method of forming the same |
| CN102543895A (en) * | 2010-12-21 | 2012-07-04 | 南茂科技股份有限公司 | Bump structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020134700A1 (en) | 2020-07-02 |
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Application publication date: 20200707 |
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