CN111383685A

CN111383685A - Variable resistive memory device and method for performing memory operations

Info

Publication number: CN111383685A
Application number: CN201811609321.6A
Authority: CN
Inventors: 黄科颕
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2020-07-07
Anticipated expiration: 2038-12-27
Also published as: CN111383685B

Abstract

The present invention provides a variable resistive memory device, comprising: the variable resistive memory device includes a variable resistive memory array, a sense amplifier, and a boost circuit. The sense amplifier is coupled to the variable resistive memory array and configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cells of the variable resistance memory array and configured to boost a reset voltage in a boosting period of a reset period according to a resistance value of the memory cells. The boosting period starts at the start of the reset period, and the memory cell is biased by the reset voltage during the reset period to perform the reset operation. In addition, a reset operation method for the variable resistive memory is provided.

Description

Variable resistive memory device and method for performing memory operations

Technical Field

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a variable resistive memory device and method for performing a memory operation.

Background

Nonvolatile semiconductor memory (RRMA) devices are used in various electronic devices, such as RRAM devices for computers, digital cameras, smart phones, and the like. The RRAM device includes a plurality of RRAM cells configured to store information according to resistance values of the RRAM cells. For example, the low resistance state of the RRAM cell corresponds to a logic value of "1" and the high resistance state of the RRAM cell corresponds to a logic value of "0". To change the resistance state of a particular RRAM cell from a low resistance state to a high resistance state, the RRAM device performs a reset (reset) operation on the particular RRAM cell via application of a reset voltage across a resistance element of the particular RRAM cell.

However, when the resistance value of a particular RRAM cell is too small, the reset voltage may not be large enough to trigger a reset operation. As a result, the reset operation cannot be performed, and the performance and reliability of the RRAM device are degraded.

With the popularization of RRAM devices, it is desirable to have RRAM devices and operating methods capable of solving the above-mentioned problems and improving the performance and reliability of RRAM devices.

Disclosure of Invention

The present invention provides a method for a reset operation of a variable resistive memory device and a variable resistive memory device to improve performance and reliability of an RRAM device.

The method comprises the following steps: sensing a resistance value of a memory cell of the variable resistance memory; boosting the reset voltage according to the resistance value of the memory unit in the boosting period of the reset period to generate a boosted reset voltage, wherein the boosting period is started from the reset period; and biasing the memory cell with the boosted reset voltage during the reset period to perform a reset operation.

The variable resistive memory device includes a variable resistive memory array, a sense amplifier, and a boost circuit. The sense amplifier is coupled to the variable resistive memory array and configured to sense a resistance value of the memory cell. The boosting circuit is coupled to the memory cells of the variable resistive memory array and configured to boost a reset voltage according to a resistance value of the memory cells during a boosting period during a reset period. Wherein the boosting period is started from a reset period, and the memory cell is biased by a reset voltage during the reset period to perform a reset operation.

In an embodiment of the present invention, a reset voltage applied to a memory cell for performing a reset operation is boosted according to a resistance value of the memory cell. In this way, even if the resistance of the memory cell is small, the reset voltage is raised enough to trigger the reset operation of the memory cell.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Drawings

FIG. 1 illustrates a schematic diagram of a RRAM device in accordance with embodiments of the invention;

fig. 2 illustrates a schematic diagram of a boost circuit of a RRAM device according to an embodiment of the present invention;

FIG. 3A illustrates a schematic diagram of a wordline boost circuit of a RRAM device according to an embodiment of the invention;

FIG. 3B illustrates an exemplary waveform diagram of signals of the wordline boost circuit as shown in FIG. 3A, in accordance with embodiments of the present invention;

fig. 4A illustrates an exemplary schematic diagram of a source line boost circuit of a RRAM device in accordance with an embodiment of the present invention;

FIG. 4B illustrates an exemplary waveform diagram of signals of the source line boost circuit shown in FIG. 4A, in accordance with embodiments of the present invention;

fig. 5A to 5D show exemplary waveform diagrams of a reset voltage signal and related signals in different embodiments of the present invention;

FIG. 6 illustrates a flow chart of a method for a reset operation on a variable resistive memory device in accordance with an embodiment of the present invention.

The reference numbers illustrate:

100: RRAM device

110: driving circuit

112: voltage booster circuit

120: RRAM array

130: sense amplifier

140: controller

212: voltage booster circuit

2121: word line boosting circuit

2122: source line boosting circuit

2123: bit line booster circuit

BL: bit line

BUFF1, BUFF 2: buffers C1, C2: capacitor with a capacitor element

D1, D2: diode with a high-voltage source

MC: RRAM cell

N1, N2: connection node

R: resistance element

S1, S2: control signal

S610 to S630: step (ii) of

SL: source line

SW1, SW 2: switch with a switch body

T: transistor with a metal gate electrode

tx1, tx2, ty1, ty2, ts, te, t1, t2, t 3: point in time

V _ A1, V _ A2, V _ B1, V _ B2, V _ B3: boosted voltage

V _ BL: outputting a bit line voltage

V _ BL 1: input bit line voltage

VR1_ H, VR1_ L, VR2, VR3, VR 4: reset voltage

V _ SL: outputting source line voltage

V _ SL 1: input source line voltage

V _ WL: outputting a word line voltage

V _ WL 1: inputting word line voltage

WL: word line

Detailed Description

It is to be understood that other embodiments and alternative constructions may be employed without departing from the scope of the invention. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless limited otherwise, the terms "connected," "coupled," and "disposed" and variations thereof herein are to be construed broadly and encompass direct and indirect connections, couplings, and arrangements.

Referring to fig. 1, the RRAM device 100 includes a driving circuit 110, a RRAM array 120, a sense amplifier 130, and a controller 140. The RRAM array 120 includes a plurality of RRAM cells MC configured to store data based on resistance values of the RRAM cells MC. Each RRAM cell MC is coupled to one bit line BL, one word line WL, and one source line SL, and a memory operation performed on the RRAM cell MC is controlled by the bit line BL, the word line WL, and the source line SL. In the embodiment of the present invention, each RRAM cell MC may include a transistor T and a resistance element R, but the present invention does not limit the structure of the RRAM cell.

The sense amplifier 130 is coupled to the RRAM array 120 and is configured to sense a logic state (e.g., logic state "1" or logic state "0") stored in the RRAM cell MC. For example, the sense amplifier 130 may sense a resistance value stored in each RRAM cell MC to determine the logic state of the RRAM cell.

The driving circuit 110 is configured to drive the RRAM cells MC of the RRAM array 120. To drive the selected RRAM cell, the driving circuit 110 may provide a bitline voltage, a wordline voltage, and a source line voltage to the selected RRAM cell. The values of the bit line voltage, the word line voltage, and the source line voltage depend on the operation performed on the selected RRAM cell. The driving circuit 110 may include a boosting circuit 112 configured to adjust at least one of a word line voltage, a bit line voltage, and a source line voltage applied to the RRAM cell. For example, in a reset operation of the selected RRAM cell, the boosting circuit 112 may boost the reset voltage applied to the selected RRAM cell by adjusting at least one of a word line voltage, a bit line voltage, and a source line voltage applied to the selected RRAM cell.

As shown in fig. 1, the boosting circuit 112 is included in the driving circuit 110, but the present invention is not limited thereto. The boost circuit 112 may be disposed outside the drive circuit 110 and coupled to the drive circuit 110. The boosting circuit 112 may receive a word line voltage, a bit line voltage, and a source line voltage from the driving circuit 110, and adjust the received word line voltage, bit line voltage, and source line voltage.

Fig. 1 shows only one driving circuit 110 and one boosting circuit 112, but the present invention does not limit the number of driving circuits 110 and boosting circuits 112. In an embodiment, RRAM device 100 may include a plurality of driver circuits 110, wherein each driver circuit 110 includes at least one boost circuit 112. Each boost circuit 112 is configured to simultaneously control at least one RRAM cell. In this way, the plurality of RRAM cells can be driven simultaneously by the boosted reset voltage according to the resistance value of each of the plurality of RRAM cells.

The controller 140 is coupled to the driving circuit 110 and the sense amplifier 130, and is configured to control a memory operation applied to the RRAM cell MC. For example, the controller 140 may control the driving circuit 110 to provide at least one of a word line voltage, a bit line voltage, and a source line voltage to the RRAM cells of the RRAM array 120. The controller 140 may be a programmable hardware processor, microprocessor, or the like.

Referring to fig. 2, the boost circuit 212 may include a Word Line (WL) boost circuit 2121, a Source Line (SL) boost circuit 2122, and a Bit Line (BL) boost circuit 2123. The wordline boost circuit 2121 is configured to adjust a wordline voltage of at least one RRAM cell connected to the wordline boost circuit 2121. Specifically, the word line voltage boost circuit 2121 regulates the word line voltage according to the input word line voltage V _ WL1 and the input boost voltage V _ B1 to output an output word line voltage V _ WL. The output word line voltage V _ WL is supplied to a word line of at least one RRAM cell.

The source line boost circuit 2122 is configured to adjust a source line voltage of at least one RRAM cell connected to the source line boost circuit 2122. The source line boosting circuit adjusts the source line voltage according to the input source line voltage V _ SL1 and the input boosted voltage V _ B2 to output the source line voltage V _ SL. The output source line voltage V _ SL is supplied to the source line of the at least one RRAM cell.

The bitline boost circuit 2123 is configured to adjust a bitline voltage of at least one RRAM cell connected to the bitline boost circuit 2123. The bit line boost circuit 2123 adjusts the bit line voltage according to the input bit line voltage V _ BL1 and the input boost voltage V _ B3 to output the bit line voltage V _ BL. The output bitline voltage V _ BL is provided to the bitline of the at least one RRAM cell.

In an embodiment of the present invention, the wordline boost circuit 2121 is configured to adjust a wordline voltage applied to the selected RRAM cell depending on a resistance value of the selected RRAM cell. The source line boost circuit 2122 is configured to adjust a source line voltage applied to the selected RRAM cell in accordance with a resistance value of the selected RRAM cell. The bitline boost circuit 2123 is configured to adjust a bitline voltage applied to the selected RRAM cell in accordance with a resistance value of the selected RRAM cell. For example, at least one of a word line voltage, a source line voltage, and a bit line voltage of the selected RRAM cell is adjusted so as to boost a reset voltage of the selected RRAM cell according to a resistance value of the RRAM cell.

Referring to fig. 3A, the wordline voltage boost circuit 2121 may include a diode D1, a buffer BUFF1, a capacitor C1, and a switch SW 1. The diode D1 has an anode terminal configured to receive the input word line voltage V _ WL1 and a cathode terminal coupled to a connection node N1 among the diode D1, the capacitor C1 and the switch SW 1. In an embodiment of the present invention, the diode D1 may be replaced by a circuit with similar function or a component such as a N-type metal-oxide-semiconductor (NMOS) transistor, wherein the NMOS may have a negative threshold voltage.

Buffer BUFF1 has an input terminal and an output terminal. An input terminal of the buffer BUFF1 receives the boosted voltage V _ B1, and an output terminal of the buffer BUFF1 is coupled to one terminal of the capacitor C1. The capacitor C1 is coupled between the connection node N1 and the buffer BUFF 1. The switch SW1 is coupled between the connection node N1 and the wordline of the at least one RRAM cell, and the switch SW1 is controlled to be turned on or off according to the control signal S1. The control signal S1 may be provided by the controller 140 shown in fig. 1.

The buffer BUFF1 provides a voltage V _ a1 to charge the capacitor C1, and the capacitor C1 may discharge the energy stored in the capacitor C1 to boost the wordline voltage. In this way, the word line voltage boost circuit 2121 can boost the voltage level of the word line voltage according to the input word line voltage V _ WL1 and the boost voltage V _ B1. The switch SW1 can be turned on or off according to the control signal S1 to provide the boosted wordline voltage V _ WL to the wordline of the at least one RRAM cell.

Referring to fig. 3A and 3B, waveforms of the output word line voltage V _ WL and the voltages V _ B1, V _ a1 of the word line voltage boost circuit 2121 in fig. 3A are shown. Before time tx1, the voltages V _ B1 and V _ a1 are at a low voltage level, and the word line voltage has not yet been boosted (the output word line voltage V _ WL is the same as the input word line voltage V _ WL 1). During the time interval from tx1 to tx2, the voltages V _ B1 and V _ a1 rise to a high voltage level and the word line voltage is boosted to a higher voltage level. The level of the boosted wordline voltage and the length of the boosting period may be determined according to the resistance value of the RRAM cell connected to the wordline booster circuit 2121. After the time point tx2, the voltage level of the word line voltage decreases and returns to the level of the input word line voltage V _ WL 1.

Referring to fig. 4A, the source line boost circuit 2122 may include a diode D2, a buffer BUFF2, a capacitor C2, and a switch SW 2. The diode D2, the buffer BUFF2, the capacitor C2, the switch SW2, the connection node N2, and the control signal S2 are substantially the same as the diode D1, the buffer BUFF1, the capacitor C1, the switch SW1, the connection node N1, and the control signal S1 in fig. 3A. Therefore, detailed descriptions about the diode D2, the buffer BUFF2, the capacitor C2, the switch SW2, the connection node N2, and the control signal S2 will be omitted hereinafter.

Referring to fig. 4A and 4B, waveforms of the output source line voltage V _ SL and the voltages V _ B2 and V _ a2 in the source line boost circuit 2122 of fig. 4A are shown. Before the time point ty1, the voltages V _ B2 and V _ a2 are at a low voltage level and the source line voltage has not yet been boosted (the output source line voltage V _ SL is the same as the input source line voltage V _ SL 1). During the time interval from ty1 to ty2, the voltages V _ B2 and V _ a2 rise to a high voltage level and the source line voltage is boosted to a higher voltage level. The level of the boosted source line voltage and the length of the boosting period may be determined according to the resistance value of the RRAM cell connected to the source line boosting circuit 2122. After the time point ty2, the voltage level of the source line voltage decreases and returns to the level of the input source line voltage V _ SL 1.

The structure of the bit line boost circuit 2123 can be analogized, and a detailed description of the bit line boost circuit 2123 will be omitted below.

Referring to FIG. 5A, the waveforms of the signals during reset of the RRAM cell are shown. During the reset period (from ts to te), the voltage levels of the word line voltage, the source line voltage, and the bit line voltage are kept constant. If the resistance value of the RRAM cell is large enough (e.g., the resistance value of the RRAM cell is greater than a threshold), the reset voltage VR1_ H increases at the end of the reset period and nearly reaches the voltage level of the source line. Thus, the reset operation is successfully performed on the RRAM cell. However, if the resistance of the RRAM cell is too small (e.g., the resistance of the RRAM cell is less than a threshold), most of the reset voltage VR1_ L falls on the resistive element of the RRAM cell, and thus the remaining reset voltage VR1_ L is insufficient to successfully perform the reset operation.

For example, referring to fig. 1 and 5A, the current IR flowing through the RRAM cell is calculated according to equation (1), and the reset voltage VR applied to the terminal of the resistive element is calculated according to equation (2). As shown in equations (1) and (2), if the resistance value R (RRAM) of the RRAM cell is too small (e.g., very low R (RRAM)), most of the voltage will drop on the transistor T due to high R (1T), and the reset voltage VR is too small to successfully trigger the reset operation.

However, the RRAM cell having a relatively large resistance value does not suffer from the above-described problem. Therefore, in the embodiment of the present invention, the resistance of the RRAM cell is first sensed. If the resistance value of the RRAM cell is greater than the threshold value, the word line voltage, the source line voltage, and the bit line voltage as shown in FIG. 5A may be applied to perform a reset operation on the RRAM cell. If the resistance value of the RRAM cell is too small (e.g., less than a threshold), at least one of the wordline voltage, the source line voltage, or the bitline voltage is adjusted to raise the reset voltage sufficiently large to successfully trigger the reset operation.

Referring to fig. 5B, the reset voltage applied to the RRAM cell is raised by raising the word line voltage applied to the RRAM cell. In the boosting period (ts to t1) of the reset period (ts to te), the word line voltage is raised to a higher level, thereby boosting the reset voltage VR2 applied to the RRAM cell. The length of the boosting period (from ts to t1) may be shorter than the length of the non-boosting period (t1 to te) of the reset period. The start point of the boosting period is the same as the start point of the reset period, but the present invention is not limited thereto.

Referring to fig. 5C, the reset voltage applied to the RRAM cell is raised by raising the source line voltage applied to the RRAM cell. In a boosting period (from ts to t2) of a reset period (from ts to te), the source line voltage is raised to a higher level, thereby boosting the reset voltage VR3 applied to the RRAM cell. The length of the boosting period (from ts to t2) may be shorter than the length of the non-boosting period (t2 to te) of the reset period. The start point of the boosting period is the same as the start point of the reset period, but the present invention is not limited thereto.

Referring to fig. 5D, the reset voltage applied to the RRAM cell is raised by adjusting the bit line voltage applied to the RRAM cell. During the boosting period (ts to t3) of the reset period (ts to te), the bit line voltage is adjusted to a lower level, thereby boosting the reset voltage VR4 applied to the RRAM cell. The length of the boosting period (from ts to t3) may be shorter than the length of the non-boosting period (t3 to te) of the reset period. The start point of the boosting period is the same as the start point of the reset period, but the present invention is not limited thereto.

At least one of a word line voltage, a source line voltage and a bit line voltage is over-boosted to boost a reset voltage applied to the RRAM cell. As shown in fig. 2 and 3A, the word line voltage may be boosted by increasing at least one of the level of the word line voltage and the length of the boosting period using the word line boosting circuit. As shown in fig. 2 and 4A, the source line voltage may be boosted by increasing at least one of the level of the source line voltage and the length of the boosting period using the word line boosting circuit. And the bit line voltage may be adjusted by adjusting at least one of a level of the bit line voltage and a length of the boosting period.

Fig. 6 illustrates a method for a reset operation on a memory cell of an RRAM device in accordance with an embodiment of the present invention. In step S610, the resistance value of the memory cell is sensed. In step S620, a reset voltage is raised during a boosting period of a reset period according to a resistance value of the memory cell to generate a boosted reset voltage, wherein the boosting period starts at a start point of the reset period. In step S630, the memory cell is biased with the boosted reset voltage during the reset to perform the reset operation.

To summarize, embodiments of the present invention introduce RRAM devices and methods for performing a memory operation on memory cells of RRAM devices. The resistance value of the memory cell is sensed, and a reset voltage of a reset operation applied to the memory cell is boosted according to the resistance value of the memory cell. At least one of a word line voltage, a source line voltage and a bit line voltage applied to the memory cell may be adjusted according to a resistance value of the memory to boost the reset voltage. In this manner, the reset voltage may be raised sufficiently large to successfully trigger the reset operation, thus improving the performance and reliability of the RRAM device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or spirit of the invention. It is intended that all modifications and variations of the present invention that fall within the scope of the following claims and their equivalents be covered thereby.

Claims

1. A reset operation method of a variable resistive memory device including a memory cell, comprising:

sensing a resistance value of the memory cell;

during a boosting period in a reset period, boosting a reset voltage according to the resistance value of the memory cell to generate a boosted reset voltage, wherein the boosting period starts at a start point of the reset period; and

biasing the memory cell with the boosted reset voltage during a reset to perform a reset operation.

2. The method of claim 1, wherein the length of the boosting period and the level of the boosted reset voltage are determined according to the resistance value of the memory cell.

3. The method of resetting operation of a variable resistive memory device including a memory cell according to claim 2, wherein at least one of the length during the boosting and the level of the boosted reset voltage increases as the resistance value of the memory cell decreases.

4. The method of resetting operation of a variable resistive memory device including a memory cell according to claim 1, wherein the boosting period during the reset is smaller than a non-boosting period during the reset.

5. The method of claim 1, wherein the step of boosting the reset voltage according to the resistance value of the memory cell during the boosting period of the reset period comprises:

boosting a wordline voltage coupled to a wordline of the memory cell during the boosting during the reset, wherein the reset voltage increases as the wordline voltage increases.

6. The method of claim 1, wherein the step of boosting the reset voltage according to the resistance value of the memory cell during the boosting period of the reset period comprises:

boosting a source line voltage coupled to a source line of the memory cell during the boosting during the reset, wherein the reset voltage increases as the source line voltage increases.

7. The method of claim 1, wherein the step of boosting the reset voltage according to the resistance value of the memory cell during the boosting period of the reset period comprises:

during the boosting during the reset, a bit line voltage of a bit line coupled to a memory cell is decreased, wherein the reset voltage increases as the bit line voltage decreases.

8. The method of claim 1, wherein the method comprises a step of resetting the variable resistive memory device

A plurality of memory cells of the variable resistive memory device are simultaneously subjected to the reset operation;

the first reset voltage applied to a first memory cell of the plurality of memory cells is different from the second reset voltage applied to a second memory cell of the plurality of memory cells.

9. A variable resistive memory device, comprising:

a variable resistive memory array including memory cells;

a sense amplifier coupled to the variable resistive memory array and configured to sense a resistance value of the memory cell;

a boosting circuit coupled to the memory cell and configured to boost a reset voltage according to the resistance value of the memory cell during a boosting period of a reset period to generate a boosted reset voltage, wherein the boosting period starts at a start point of the reset period, and the memory cell is biased by the reset voltage during the reset period to perform a reset operation.

10. The variable resistive memory device of claim 9, wherein a length of the boosting period and a level of the boosted reset voltage are determined according to the resistance value of the memory cell.

11. The variable resistive memory device of claim 10, wherein at least one of the length during the boosting and the level of the boosted reset voltage increases as the resistance value of the memory cell decreases.

12. The variable resistive memory device of claim 9, wherein the boosting period during the reset is less than a non-boosting period during the reset.

13. The variable resistive memory device of claim 9, wherein the boost circuit includes at least one among a word line boost circuit, a source line boost circuit, and a bit line boost circuit, wherein each of the word line boost circuit, the source line boost circuit, and the bit line bias boost circuit includes:

a diode having an anode terminal and a cathode terminal, wherein the anode terminal receives a first bias voltage;

a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled to the cathode terminal of the diode via a connection node;

a switch coupled between the memory cell and a connection node between the first terminal of the capacitor and the cathode terminal of the diode.

14. The variable resistive memory device of claim 13, wherein each of the word line boost circuit, the source line boost circuit, and the bit line bias boost circuit further comprises:

a buffer coupled to the second terminal of the capacitance configured to receive a boosted voltage and output a voltage to charge the capacitance.

15. The variable resistive memory device of claim 9, further comprising:

a write driving circuit configured to simultaneously drive a plurality of memory cells of the variable resistance memory array, wherein a first reset voltage applied to a first memory cell of the plurality of memory cells is different from a second reset voltage applied to a second memory cell of the plurality of memory cells, wherein the boosting circuit is included within the write driving circuit.