CN111381876B - move instruction decoding method, data moving method, decoder and data access device - Google Patents
move instruction decoding method, data moving method, decoder and data access device Download PDFInfo
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- CN111381876B CN111381876B CN201811623225.7A CN201811623225A CN111381876B CN 111381876 B CN111381876 B CN 111381876B CN 201811623225 A CN201811623225 A CN 201811623225A CN 111381876 B CN111381876 B CN 111381876B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
Abstract
The application relates to a move instruction decoding method, which expands an instruction set and a hardware structure of a decoder by analyzing a move instruction, improves a decoding function of the decoder and perfects the operation of the move instruction.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a move instruction decoding method, a data moving method, a decoder, and a data access apparatus.
Background
With the continuous development of data processing technology, people have higher and higher requirements on data processing compatibility, and more data are processed, so that more and more data processing methods and data processing devices are provided to solve the problem of data bit number.
The conventional data movement instruction is to directly move data, and a method for processing data in a specific format is relatively lacked, and a method for analyzing the data is also lacked.
Disclosure of Invention
In view of the above, it is desirable to provide a move instruction decoding method, a data moving method, a decoder, and a data access apparatus capable of supporting data processing in a specific format.
A method of move instruction decoding, the method comprising:
the method comprises the steps of obtaining source data and preset parameters of a data head in a move instruction, and configuring a first operation of the move instruction according to the source data of the data head and the preset parameters to obtain a first operand of the first operation, wherein the first operation is used for reading a target data head and a target data body in compressed data according to the first operand, the compressed data comprises a plurality of data heads and a plurality of data bodies, the data heads store corresponding start addresses and data lengths of the data bodies, the data bodies contain compressed encoding values of the compressed data, and the first operand comprises an immediate number or a register number;
and acquiring destination data of a data header in the move instruction, and configuring a second operation of the move instruction according to the destination data of the data header, the target data header and a target data body to obtain a second operand of the second operation, wherein the second operation is used for writing out the acquired compressed data according to the second operand, and the second operand comprises an immediate number or a register number.
In one embodiment, the acquired instruction is analyzed, and the instruction is determined to be a move instruction according to the instruction type and the instruction type in the instruction.
In one embodiment, if the first operand is an immediate, the first operation is configured to read a target data header in compressed data from a first storage device according to the first operand, and then obtain a target data volume corresponding to the target data header according to a start address and a data length in the target data header, where the first storage device is an off-chip storage device;
and if the first operand is a register number, the first operation is used for reading a target data head in compressed data from a second storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a start address and a data length in the target data head, wherein the second storage device is a chip memory storage device.
In one embodiment, the original address of the target data header in the first operand is obtained according to the source address and the source address offset of the data header in the move instruction;
and configuring a first operation of the move instruction according to the original address and the preset parameters to obtain a first operand of the first operation, wherein the preset parameters comprise the number of the target data heads.
In one embodiment, a first operation of the move instruction is configured according to the number of rows of data heads in the move instruction, a source line feed distance, the number of single-row data heads and preset parameters, so as to obtain a first operand of the first operation, where the preset parameters include the number of rows of target data heads and the number of single-row target data heads.
In one embodiment, the original address and the number of the target data body in the first operand are obtained according to the original address and the number of the target data head in the first operand;
and configuring the first operation of the move instruction by using the original address and the number of the target data body.
In one embodiment, a destination address and a destination address offset of the target data header in the second operand are obtained according to a destination address and a destination address offset of a data header in the move instruction;
and configuring the second operation of the move instruction according to the destination address and the destination address offset of the target data head to obtain a second operand of the second operation.
A method of data movement, the method comprising:
obtaining a move instruction, and analyzing the move instruction to obtain a first operand and a second operand of the move instruction;
reading a target data header and a target data body in compressed data from a storage device pointed by the first operand, wherein the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed and encoded values of the compressed data, and the first operand comprises an immediate number or a register number;
and writing the target data head and the target data body in the read compressed data into a storage device pointed by the second operand, wherein the second operand comprises an immediate number or a register number.
In one embodiment, if the first operand is an immediate, reading a target data header in the compressed data from a first storage device according to the first operand, and then acquiring a target data body corresponding to the target data header according to a start address and a data length in the target data header, where the first storage device is an off-chip storage device;
and if the first operand is a register number, reading a target data head in the compressed data from a second storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a starting address and a data length in the target data head, wherein the second storage device is an on-chip memory device.
In one embodiment, a target data header in the compressed data is read according to an original address of the data header in the first operand and a preset parameter, wherein the preset parameter includes the number of the target data header.
In one embodiment, the target data head in the compressed data is read according to the number of rows of data heads in the first operand, the source line feed distance, the number of data heads in a single row, and the number of rows of target data heads and the number of target data heads in a single row in the preset parameters.
In one embodiment, the read target data header in the compressed data is written into the storage device pointed to by the second operand according to the destination address and the destination address offset of the target data header in the second operand, and then the target data body is correspondingly written into the storage device pointed to by the second operand according to the relative positions of the target data header and the target data body in the storage device pointed to by the first operand.
A decoder, the decoder comprising: the device comprises a first configuration unit and a second configuration unit, wherein the first configuration unit is connected with the second configuration unit;
the first configuration unit is configured to acquire source data and preset parameters of a data header in a move instruction, and configure a first operation of the move instruction according to the source data of the data header and the preset parameters to obtain a first operand of the first operation, where the first operation is configured to read a target data header and a target data body in compressed data according to the first operand, the compressed data includes multiple data headers and multiple data bodies, the data headers store start addresses and data lengths of the corresponding data bodies, the data bodies include compressed encoding values of the compressed data, and the first operand includes an immediate number or a register number;
the second configuration unit is configured to acquire destination data of a data header in the move instruction, and configure a second operation of the move instruction according to the destination data of the data header, the target data header, and a target data body to obtain a second operand of the second operation, where the second operation is used to write out the acquired compressed data according to the second operand, and the second operand includes an immediate number or a register number.
A data access device, the device comprising: the device comprises a configuration unit, a data read-write unit and a direct memory access unit, wherein the configuration unit is connected with the direct memory access unit through the data read-write unit;
the data reading and writing unit receives a first operand and a second operand sent by the configuration unit and sends the first operand and the second operand to the direct memory access unit;
the direct memory access unit is used for finishing the reading operation of a target data head and a target data body in the compressed data and the writing-out operation of the acquired compressed data according to the first operand and the second operand.
According to the move instruction decoding method, the data moving method, the decoder and the data access device, the move instruction is analyzed, the first operation of the move instruction is configured according to the source data of the data head and the preset parameters to obtain the first operand of the first operation, the second operation of the move instruction is configured according to the destination data of the data head, the target data head and the target data body to obtain the second operand of the second operation, the first operation and the second operation are completed according to the first operand and the second operand, the analysis of the move instruction is achieved, and the compressed data can be moved. The method for processing the data in the compressed format is realized.
Drawings
FIG. 1 is a block diagram of a decoder in one embodiment;
FIG. 2 is a block diagram of a processor in one embodiment;
FIG. 3 is a block diagram of a data access device in one embodiment;
FIG. 4 is a flowchart illustrating a method for decoding move instructions according to one embodiment;
FIG. 5 is a schematic flow chart diagram illustrating a first operation under different conditions in one embodiment;
FIG. 6 is a flow diagram illustrating the configuration of a first operation in one embodiment;
FIG. 7 is a flowchart illustrating a configuration of a second operation in one embodiment;
FIG. 8 is a flow diagram illustrating a method for data movement according to one embodiment;
fig. 9 is a flowchart illustrating step S700.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The move instruction decoding method provided by the present application can be applied to the decoder 1000 shown in fig. 1. The first configuration unit 101 is connected to the second configuration unit 102. The move instruction can realize access movement of compressed data, the compressed data can be data in a specific format, the compressed data can comprise a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, and the data bodies contain compressed coding values of the compressed data. The move command can access and move the data head, and then access and move the data body.
Specifically, the first configuration unit 101 is configured to configure a first operation of the move instruction, and obtain a first operand of the first operation. The second configuration unit 102 is configured to configure a second operation of the move instruction to obtain a second operand of the second operation.
Optionally, the first configuration unit 101 obtains a first operand of the first operation by configuration, where the first operation is represented by reading a target data header and a target data body in the compressed data according to the first operand. The compressed data comprises a plurality of data heads and a plurality of data bodies, wherein the data heads store the start addresses and the data lengths of the corresponding data bodies, and the data bodies contain compressed encoding values of the compressed data.
The second configuration unit 102 obtains a second operand of a second operation through configuration, where the second operation is represented by writing out the obtained compressed data, that is, writing out the obtained target data header and the target data volume, according to the second operand.
The first operand may be represented as an original address of a target data header when the target data header in the compressed data is read, and optionally, the first operand may be an immediate or a register number. The second operand may represent a destination address of a destination data header when the destination data header is written back in the compressed data, and may alternatively be an immediate or register number.
Alternatively, referring to fig. 2, the controller unit 11 in the processor 2000 may be used as the decoder 1000, wherein the controller unit 11 is connected to the operation unit 12, and the operation unit 12 includes: a master processing circuit and a plurality of slave processing circuits;
a controller unit 11 for acquiring input data and a calculation instruction; in an alternative, the input data obtaining and instruction calculating manner may be obtained through a data input/output unit, and the data input/output unit may be one or more data I/O interfaces or I/O pins.
The above calculation instructions include, but are not limited to: a forward operation instruction or a backward training instruction, or other neural network operation instructions, etc., such as a convolution operation instruction.
The controller unit 11 is further configured to analyze the calculation instruction to obtain a plurality of operation instructions, and send the plurality of operation instructions and the input data to the main processing circuit;
a master processing circuit 121 configured to perform a preamble process on the input data and transmit data and an operation instruction with the plurality of slave processing circuits;
a plurality of slave processing circuits 122, configured to perform an intermediate operation in parallel according to the data and the operation instruction transmitted from the master processing circuit to obtain a plurality of intermediate results, and transmit the plurality of intermediate results to the master processing circuit;
and the main processing circuit 121 is configured to perform subsequent processing on the plurality of intermediate results to obtain a calculation result of the calculation instruction.
Alternatively, the controller unit 11 may include: instruction cache unit 110, instruction processing unit 111, and store queue unit 113.
The instruction cache unit 110 is configured to store a calculation instruction associated with an artificial neural network operation.
The instruction processing unit 111 is configured to analyze the calculation instruction to obtain a plurality of operation instructions.
A store queue unit 113 for storing an instruction queue, the instruction queue comprising: and a plurality of operation instructions or calculation instructions to be executed according to the front and back sequence of the queue.
Alternatively, the first configuration unit 101 and the second configuration unit 102 may be disposed in the instruction processing unit 111, and the instruction processing unit 111 obtains an instruction from the instruction cache unit 110, parses the obtained instruction, and configures the first operation and the second operation through the first configuration unit 101 and the second configuration unit 102.
Optionally, the controller unit 11 may further include:
the dependency processing unit 112 is configured to determine whether a first operation instruction is associated with a zeroth operation instruction before the first operation instruction when there are multiple operation instructions, if so, cache the first operation instruction in the instruction storage unit, and after the zeroth operation instruction is executed, extract the first operation instruction from the instruction storage unit and transmit the first operation instruction to the operation unit;
the determining whether the first operation instruction has an association relationship with a zeroth operation instruction before the first operation instruction comprises:
extracting a first storage address interval of required data (such as a matrix) in the first operation instruction according to the first operation instruction, extracting a zeroth storage address interval of the required matrix in the zeroth operation instruction according to the zeroth operation instruction, if the first storage address interval and the zeroth storage address interval have an overlapped area, determining that the first operation instruction and the zeroth operation instruction have an association relationship, and if the first storage address interval and the zeroth storage address interval do not have an overlapped area, determining that the first operation instruction and the zeroth operation instruction do not have an association relationship.
For example, in an alternative embodiment, the main operation processing circuit may also include a controller unit, and the controller unit may include a main instruction processing unit, specifically configured to decode instructions into microinstructions. Of course, in another alternative, the slave arithmetic processing circuit may also include another controller unit that includes a slave instruction processing unit, specifically for receiving and processing microinstructions. The micro instruction may be a next-stage instruction of the instruction, and the micro instruction may be obtained by splitting or decoding the instruction, and may be further decoded into control signals of each component, each unit, or each processing circuit.
In an alternative, the instruction may be a move instruction, and the instruction format of the instruction may be as shown in the following table:
the instruction type Name is used to determine the type of the instruction (the type of the instruction may include a COMP type instruction and other instructions, where the COMP type is 16), that is, the instruction type is used to determine whether the operation instruction is a COMP type instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is implemented by the instruction, for example, when the instruction Type is 3, the instruction is a move instruction. The header destination address Head dst addr and the header destination address offset Head dst offset are used to indicate the destination address of the destination header to be written back. The instruction fields are used for indicating the original address of a target data Head to be read.
Further, the instruction format of the instruction may further include flag bits of each instruction field, for example: the flag bit Head dstr addr regen is used for identifying whether the address Head dstr addr of the data header order is an immediate number or a register number, and specifically, when the address Head dstr addr regen is 1, the address Head dstr addr of the data header order is a register number, namely, the address Head dstr addr of the data header order comes from a register, and when the address Head dstr addr regen is 0, the address Head dst addr of the data header order is an immediate number.
Further, a flag bit Head dst offset regen for identifying whether the address offset Head dst offset of the data header destination is an immediate number or a register number, and specifically, when the address offset Head dst offset regen is 1, the address offset Head dst offset indicating the data header destination is a register number, that is, when the address offset Head dst offset indicating the data header destination is from the register, and when the address offset Head dst offset regen is 0, the address offset Head dst offset indicating the data header destination is an immediate number.
And a flag bit Head src addr regen for identifying whether the Head source address Head src addr is an immediate number or a register number, specifically, when the Head src addr regen is 1, the flag bit indicates that the Head source address Head src addr is the register number, that is, the Head source address Head src addr comes from the register, and when the Head src addr regen is 0, the flag bit Head src addr regen indicates that the Head source address Head src addr is the immediate number.
Similarly, there are also a flag bit Head src stride regen for identifying whether the Head source line change distance Head src stride is an immediate number or a register number, a flag bit Head src offset regen for identifying whether the Head source address offset Head src offset is an immediate number or a register number, a flag bit segnum regen for identifying whether the Head line number segnum is an immediate number or a register number, and a flag bit Head num regen for identifying whether the single-line data Head number Head num is an immediate number or a register number. Specifically, when the flag bits are 1, the register number indicates that each instruction field is a register number, and when the flag bits are 0, the immediate number indicates that each instruction field is an immediate number.
Referring to fig. 3, the present application also provides a device for applying move commands, i.e. a data access device 3000, which may include a configuration unit 100, a data read/write unit 200, and a dma unit 300. The configuration unit 100 is connected to the data read/write unit 200, and the configuration unit 100 is connected to the direct memory access unit 300 through the data read/write unit 200.
Alternatively, the first configuration unit 101 and the second configuration unit 102 may be packaged as one configuration unit 100.
The configuration unit 100 obtains a first operand by configuring the first operation and obtains a second operand by configuring the second operation, and sends the first operand and the second operand to the data read/write unit 200. After receiving the first operand and the second operand sent by the configuration unit 100, the data read-write unit 200 sends the first operand and the second operand to the direct memory access unit 300. The dma unit 300 completes the read operation of the target data header and the target data body in the compressed data and the write operation of the acquired compressed data according to the first operand and the second operand. Namely, according to the first operand, the target data head and the target data body in the compressed data are read from the storage device pointed to by the first operand. And writing the target data head and the target data body in the read compressed data into the storage device pointed by the second operand according to the second operand.
Optionally, the storage device may include the first storage device 13, and may also include the second storage device 201. The first memory means 13 may be a memory means arranged outside the processor. The second storage means 201 may be a buffer and/or a register arranged inside the processor 1000. The first storage device 13 and the second storage device 201 may also be a non-volatile memory or a volatile memory, and are not limited herein. The data read/write unit 200 may be an I/O circuit.
In one embodiment, as shown in fig. 4, a move instruction decoding method is provided, which is described by taking the decoder in fig. 1 as an example, and includes the following steps:
s200, acquiring source data and preset parameters of a data head in the move instruction, and configuring first operation of the move instruction according to the source data and the preset parameters of the data head to obtain a first operand of the first operation.
The source data of the data head represents the original address of the target data head, and the preset parameter comprises the number of the target data heads to be acquired. The first operation is to read a target data header and a target data body in the compressed data. The compressed data comprises a plurality of data heads and a plurality of data bodies, the data heads and the data bodies have a certain corresponding relation, the data heads store the initial addresses and the data lengths of the corresponding data bodies, and the data bodies contain compressed coding values of the compressed data. The first operand may be an immediate or a register number.
Specifically, the first configuration unit 101 obtains source data and a preset parameter of a data header in the move instruction, and configures a first operation of the move instruction according to the obtained source data and the preset parameter of the data header, to obtain a first operand of the first operation, that is, to obtain an original address of the target data header.
S300, acquiring the target data of the data head in the move instruction, and configuring the second operation of the move instruction according to the target data of the data head, the target data head and the target data body to obtain a second operand of the second operation.
The destination data of the data header represents a destination address of the destination data header, that is, the acquired destination data header is written back to a position corresponding to the destination address. The second operation is for writing out the acquired compressed data. The second operand includes an immediate or register number.
Specifically, the second configuration unit 102 obtains destination data of a data header in the move instruction, and configures a second operation of the move instruction according to the destination data of the data header, the target data header, and the target data volume to obtain a second operand of the second operation, that is, to obtain a target address of the target data header.
In the move instruction decoding method, the first operand of the first operation is obtained by configuring the first operation, the first operation represents a read operation for compressing data according to the first operand, and the second operand of the second operation is obtained by configuring the second operation, and the second operation represents a write-back operation for compressing data according to the second operand. The move instruction is analyzed to obtain corresponding operation, so that the analysis of the move instruction is realized, and the instruction supports the operation of moving compressed data.
In one embodiment, referring to fig. 4, the method may further include the following steps:
and S100, analyzing the obtained instruction, and determining the instruction to be a move instruction according to the instruction type and the instruction type in the instruction.
As shown in the above table, the instruction class Name is used to determine a class of the instruction (the class of the instruction may include a COMP-class instruction and other instructions, where the COMP-class is 16), that is, the instruction class is used to determine whether the operation instruction is a COMP-class instruction. The instruction Type is used for determining the Type of the COMP Type instruction, and the Type of the COMP Type instruction is used for indicating what function is implemented by the instruction, for example, when the instruction Type is 3, the instruction is a move instruction.
Specifically, the instruction processing unit 111 analyzes the acquired instruction, distinguishes between the instruction Type Name and the instruction Type, and indicates that the instruction is a move instruction when the instruction Type is 3.
Alternatively, the instruction processing unit 111 may obtain the instruction through the instruction cache unit 110, and then the first configuration unit 101 and the second configuration unit 102 in the instruction processing unit 111 perform configuration.
In one embodiment, referring to fig. 5, the first operand may include an immediate or a register number, and whether the first operand is an immediate is determined, and when the first operand is determined to be an immediate, step S400 is executed, where the first operation is used to read a target data header in the compressed data from the first storage device according to the first operand, and then obtain a target data body corresponding to the target data header according to a start address and a data length in the target data header.
Wherein the first storage means 13 may be an off-chip storage means.
Specifically, when the first operand is an immediate, the first operation is used to read a target data header in the compressed data from a corresponding location in the first storage device 13 to which the first operand points, and then obtain a target data volume corresponding to the target data header according to the obtained start address and data length in the target data header.
When the first operand is determined to be the register number, step S500 is executed, where the first operation is used to read a target data header in the compressed data from the second storage device according to the first operand, and then obtain a target data body corresponding to the target data header according to a start address and a data length in the target data header.
Wherein the second storage 201 may be an on-chip storage.
Specifically, when the first operand is a register number, the first operation is used to read a target data header in the compressed data from a corresponding location in the second storage device 201 to which the first operand points, and then obtain a target data volume corresponding to the target data header according to the obtained start address and data length in the target data header.
The method of the embodiment adapts to the requirements of the instructions under different application scenes by reading the compressed data from the off-chip address and the on-chip address, and enhances the completeness of the instruction application.
In one embodiment, referring to fig. 6, the process of configuring the first operation may include the following steps:
s210, according to the source address and the source address offset of the data head in the move instruction, the original address of the target data head in the first operand is obtained.
Specifically, the first configuration unit 101 obtains a source address and a source address offset of a data header in the move instruction, and then obtains an original address of a target data header in the first operand according to the source address and the source address offset of the data header. And obtaining an original address of the target data head by obtaining the source address and the source address offset of the data head, wherein the original address is used for storing the target data head.
S220, configuring the first operation of the move instruction according to the original address and the preset parameters to obtain a first operand of the first operation.
The preset parameters comprise the number of target data heads to be read.
Specifically, after obtaining the original address of the target data header, the first configuration unit 101 configures the first operation of the move instruction according to the original address and the preset parameter, so as to obtain a first operand of the first operation. The original address is used for storing the target data head, the preset parameter comprises the number of the target data heads, the configuration is carried out according to the storage address and the number of the target data heads to obtain a first operand, and the target data heads can be read according to the first operand.
And S230, configuring the first operation of the move instruction according to the line number of the data heads in the move instruction, the source line feed distance, the number of the data heads in a single line and preset parameters to obtain a first operand of the first operation.
The preset parameters comprise the line number of the target data head and the number of the single-line target data heads.
Specifically, after acquiring the number of rows of the data head, the source line feed distance, and the number of single-row data heads in the move instruction, the first configuration unit 101 configures according to the number of rows of the data head, the source line feed distance, the number of single-row data heads, and a preset parameter, to obtain a first operand. The first operand is used to determine the original address, the number of rows, and the number of single rows of the target data header to be read.
S240, according to the original address and the number in the target data head of the first operand, the original address and the number of the target data body of the first operand are obtained.
Specifically, the first operand includes an original address of a target data header and a number of the target data header, and the data header has a certain correspondence with a data body, the data header stores a start address and a data length of the corresponding data body, and the first configuration unit 101 obtains the original address and the number of the target data body according to the original address and the number of the target data header.
And S250, configuring the first operation of the move instruction by using the original address and the number of the target data body.
Specifically, the first configuration unit 101 obtains the original address and the number of the target data volume, and then configures a first operation of the move instruction according to the original address and the number of the target data volume, where the first operation is used to read the target data volume according to the original address and the number of the target data volume.
In this embodiment, the number and the number of rows of the data header in the first operation are configured, so that the position of the target data header to be read is more accurate.
In one embodiment, referring to fig. 7, the process of configuring the second operation may include the following steps:
s310, according to the destination address and the destination address offset of the data head in the move instruction, the destination address and the destination address offset of the target data head in the second operand are obtained.
Specifically, the second configuration unit 102 acquires a destination address and a destination address offset of a data header in the move instruction, and then obtains a destination address and a destination address offset of a target data header according to the destination address and the destination address offset of the data header. The destination address and the destination address offset of the target data header are used to indicate the target address to which the target data header is to be written back, i.e., the destination address and the destination address offset of the target data header are used to store the written-back target data header.
S320, configuring the second operation of the move instruction according to the destination address of the target data head and the destination address offset to obtain a second operand of the second operation.
Specifically, after obtaining the destination address and the destination address offset of the target data header, the second configuration unit 102 configures the second operation of the move instruction according to the destination address and the destination address offset of the target data header, to obtain a second operand of the second operation, where the second operand is used to indicate the destination address and the destination address offset of the target data header, that is, the second operand is used to indicate the target address to be written back by the target data header, that is, the destination address and the destination address offset of the target data header are used to store the written-back target data header.
The method of the implementation configures the destination address and the destination address offset of the target data head, so that the address of the target data head written back is more accurate.
Referring to fig. 8, the present application further provides a data moving method, which is applied to the access device of fig. 3 as an example, and includes the following steps:
s600, obtaining the move instruction, and analyzing the move instruction to obtain a first operand and a second operand of the move instruction.
Wherein the first operand may comprise an immediate or register number and the second operand may comprise an immediate or register number
Specifically, the configuration unit 100 acquires the move instruction, analyzes the move instruction, and acquires a first operand and a second operand of the move instruction.
S700, reading a target data head and a target data body in the compressed data from the storage device pointed by the first operand.
The storage device may be the first storage device 13 or the second storage device 201. The compressed data comprises a plurality of data heads and a plurality of data bodies, wherein the data heads store the start addresses and the data lengths of the corresponding data bodies, and the data bodies contain compressed coding values of the compressed data.
Specifically, after obtaining the first operand and the second operand, the configuration unit 100 sends the first operand and the second operand to the data read/write unit 200, and after receiving the first operand, the data read/write unit 200 sends the first operand to the direct memory access unit 300, and then the direct memory access unit 300 reads the target data header and the target data body in the compressed data from the storage device to which the first operand points according to the first operand.
And S800, writing the target data head and the target data body in the read compressed data into the storage device pointed by the second operand.
The storage device may be the first storage device 13 or the second storage device 201.
Specifically, after obtaining the first operand and the second operand, the configuration unit 100 sends the first operand and the second operand to the data read/write unit 200, and after receiving the first operand, the data read/write unit 200 sends the first operand to the direct memory access unit 300, and then the direct memory access unit 300 writes the target data header and the target data body in the read compressed data into the storage device to which the second operand points, according to the second operand.
According to the method, the compressed data is accessed and moved according to the first operand and the second operand obtained through analysis, the data in the compressed format is supported to be moved, the instruction function is improved, and the device functionality is improved.
In one embodiment, referring to fig. 9, the step S700 may include the following steps:
judging whether the first operand is an immediate number, if so, executing step S710, reading a target data header in the compressed data from the first storage device according to the first operand, and then obtaining a target data body corresponding to the target data header according to a start address and a data length in the target data header.
The first storage device 13 is an off-chip storage device.
Specifically, when the first operand is an immediate, the dma unit 300 reads a target data header in the compressed data according to the first operand and the position pointed by the first operand in the first storage device 13, and then obtains a target data body corresponding to the target data header according to the corresponding relationship between the data header and the data body, and the start address and the data length in the read target data header.
When the first operand is determined to be the register number, step S720 is executed to read the target data header in the compressed data from the second storage device according to the first operand, and then obtain the target data body corresponding to the target data header according to the start address and the data length in the target data header.
The second storage device 201 is an on-chip storage device.
Specifically, when the first operand is a register number, the dma unit 300 reads a target data header in the compressed data according to the first operand and the position pointed by the first operand in the second storage device 201, and then obtains a target data body corresponding to the target data header according to the corresponding relationship between the data header and the data body, and the start address and the data length in the read target data header.
The method of the embodiment adapts to the requirements on the instruction in different application scenes by reading the compressed data from the off-chip address and the on-chip address, thereby enhancing the completeness of the instruction application.
In one embodiment, the dma unit 300 may read a target header in the compressed data from a location pointed to by the first operand according to an original address of the header in the first operand and a preset parameter. The preset parameter may include the number of target data headers.
In one embodiment, the dma unit 300 reads the target data header in the compressed data from the position pointed by the first operand according to the number of rows of data headers in the first operand, the source line feed distance, the number of data headers in a single row, and the number of rows of the target data header and the number of target data headers in a single row in preset parameters.
The number and the position of the target data heads to be read can be accurately determined according to the number, the number of rows and the number of single lines of the target data heads.
In one embodiment, the dma unit 300 writes the target data header of the read compressed data into the storage device pointed to by the second operand according to the destination address and the destination address offset of the target data header of the second operand, and then writes the target data body into the storage device pointed to by the second operand according to the relative positions of the target data header and the target data body in the storage device pointed to by the first operand.
The position to be written back by the acquired target data head can be accurately determined according to the target address and the target address offset of the target data head.
It should be understood that although the various steps in the flowcharts of fig. 4-9 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 4-9 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, a computer device is provided that includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a move instruction decoding method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on a shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
the method comprises the steps of obtaining source data and preset parameters of a data head in a move instruction, and configuring first operation of the move instruction according to the source data and the preset parameters of the data head to obtain a first operand of the first operation. Specifically, the first configuration unit 101 obtains source data and a preset parameter of a data header in the move instruction, and configures a first operation of the move instruction according to the obtained source data and the preset parameter of the data header, to obtain a first operand of the first operation, that is, to obtain an original address of the target data header.
And acquiring the destination data of the data head in the move instruction, and configuring the second operation of the move instruction according to the destination data of the data head, the target data head and the target data body to obtain a second operand of the second operation. Specifically, the second configuration unit 102 obtains destination data of a data header in the move instruction, and configures a second operation of the move instruction according to the destination data of the data header, the target data header, and the target data volume to obtain a second operand of the second operation, that is, to obtain a target address of the target data header.
It should be clear that, the steps implemented when the computer program in the embodiment of the present application is executed by the processor are consistent with the execution process of each step of the method in the above embodiments, and specific reference may be made to the above description, and no further description is given here.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (12)
1. A method for decoding move instructions, the method comprising:
obtaining an original address of a target data head in a first operand according to a source address and source address offset of the data head in the move instruction;
configuring a first operation of the move instruction according to the original address and a preset parameter to obtain a first operand of the first operation, wherein the preset parameter comprises the number of target data heads to be acquired; the first operation is used for reading the target data header and a target data body in compressed data according to the first operand, the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed encoding values of the compressed data, and the first operand comprises an immediate number or a register number;
obtaining a destination address and a destination address offset of the target data head in a second operand according to the destination address and the destination address offset of the data head in the move instruction;
and configuring a second operation of the move instruction according to a destination address and a destination address offset of the target data header to obtain a second operand of the second operation, wherein the second operation is used for writing out the obtained compressed data according to the second operand, and the second operand comprises an immediate number or a register number.
2. The method of claim 1, wherein prior to the step of deriving the original address of the target header in the first operand from the source address and the source address offset of the header in the move instruction, the method further comprises:
analyzing the obtained instruction, and determining that the instruction is a move instruction according to the type and type of the instruction in the instruction.
3. The method of claim 1, further comprising:
if the first operand is an immediate, the first operation is used for reading a target data head in compressed data from a first storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a start address and a data length in the target data head, wherein the first storage device is an off-chip storage device;
and if the first operand is a register number, the first operation is used for reading a target data head in compressed data from a second storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a start address and a data length in the target data head, wherein the second storage device is a chip memory storage device.
4. The method of claim 1, further comprising:
configuring a first operation of the move instruction according to the number of lines of a data head in the move instruction, a source line feed distance, the number of single-line data heads and preset parameters to obtain a first operand of the first operation, wherein the preset parameters comprise the number of lines of a target data head and the number of single-line target data heads.
5. The method according to any one of claims 1-4, further comprising:
obtaining the original address and the number of a target data body in the first operand according to the original address and the number of the target data head in the first operand;
and configuring the first operation of the move instruction by using the original address and the number of the target data body.
6. A method of data movement, the method comprising:
obtaining a move instruction, and analyzing the move instruction to obtain a first operand and a second operand of the move instruction;
reading a target data header and a target data body in compressed data from a storage device pointed by the first operand, wherein the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed encoding values of the compressed data, and the first operand comprises an immediate number or a register number;
writing a target data header and a target data body in the read compressed data into a storage device pointed to by the second operand, wherein the second operand comprises an immediate or a register number, wherein,
the obtaining a move instruction and analyzing the move instruction to obtain a first operand and a second operand of the move instruction includes:
obtaining an original address of a target data head in the first operand according to a source address and a source address offset of the data head in the move instruction;
configuring a first operation of the move instruction according to the original address and preset parameters to obtain a first operand of the first operation, wherein the preset parameters comprise the number of target data heads to be acquired;
obtaining a destination address and a destination address offset of the target data head in the second operand according to the destination address and the destination address offset of the data head in the move instruction;
and configuring the second operation of the move instruction according to the destination address and the destination address offset of the target data head to obtain a second operand of the second operation.
7. The method of claim 6, wherein the step of reading the target data header and the target data volume in the compressed data from the storage device pointed to by the first operand comprises:
if the first operand is an immediate, reading a target data head in the compressed data from a first storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a starting address and a data length in the target data head, wherein the first storage device is an off-chip storage device;
and if the first operand is a register number, reading a target data head in the compressed data from a second storage device according to the first operand, and then acquiring a target data body corresponding to the target data head according to a starting address and a data length in the target data head, wherein the second storage device is an on-chip memory device.
8. The method of claim 6, wherein the step of reading the target data header and the target data volume in the compressed data from the storage device pointed to by the first operand comprises:
and reading a target data head in the compressed data according to the original address of the data head in the first operand and preset parameters.
9. The method of claim 6, wherein the step of reading the target header and the target body of data in the compressed data from the storage device pointed to by the first operand further comprises:
and reading the target data head in the compressed data according to the line number of the data head in the first operand, the source line feed distance, the number of the single-line data heads, the line number of the target data head in the preset parameter and the number of the single-line target data head.
10. The method according to claim 6, wherein the step of writing the target data header and the target data body in the read compressed data into the storage device pointed to by the second operand comprises:
and writing the target data head in the read compressed data into a storage device pointed by the second operand according to the destination address and the destination address offset of the target data head in the second operand, and then correspondingly writing the target data body into the storage device pointed by the second operand according to the relative positions of the target data head and the target data body in the storage device pointed by the first operand.
11. A decoder, characterized in that the decoder comprises: the device comprises a first configuration unit and a second configuration unit, wherein the first configuration unit is connected with the second configuration unit;
the first configuration unit is used for obtaining an original address of a target data head in the first operand according to a source address and a source address offset of the data head in the move instruction; configuring a first operation of the move instruction according to the original address and preset parameters to obtain a first operand of the first operation, wherein the preset parameters comprise the number of target data heads to be acquired; the first operation is used for reading the target data header and a target data body in compressed data according to the first operand, the compressed data comprises a plurality of data headers and a plurality of data bodies, the data headers store the start addresses and the data lengths of the corresponding data bodies, the data bodies contain compressed coding values of the compressed data, and the first operand comprises an immediate number or a register number;
the second configuration unit is configured to obtain a destination address and a destination address offset of the target data header in a second operand according to a destination address and a destination address offset of a data header in the move instruction; and configuring a second operation of the move instruction according to a destination address and a destination address offset of the target data header to obtain a second operand of the second operation, wherein the second operation is used for writing out the acquired compressed data according to the second operand, and the second operand comprises an immediate number or a register number.
12. A data access device, the device comprising: the device comprises a configuration unit, a data read-write unit and a direct memory access unit, wherein the configuration unit is connected with the direct memory access unit through the data read-write unit;
the first configuration unit is used for obtaining an original address of a target data head in the first operand according to a source address and a source address offset of the data head in the move instruction; configuring a first operation of the move instruction according to the original address and preset parameters to obtain a first operand of the first operation; the preset parameters comprise the number of target data heads to be acquired;
the second configuration unit is configured to obtain a destination address and a destination address offset of the target data header in a second operand according to the destination address and the destination address offset of the data header in the move instruction; configuring a second operation of the move instruction according to a destination address and a destination address offset of the target data head to obtain a second operand of the second operation;
the data reading and writing unit receives a first operand and a second operand sent by the configuration unit and sends the first operand and the second operand to the direct memory access unit;
the direct memory access unit is used for reading a target data head and a target data body in compressed data from a storage device pointed by the first operand according to the first operand;
and the direct memory access unit is further used for writing the target data head and the target data body in the read compressed data into the storage device pointed by the second operand according to the second operand.
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| CN201811623225.7A CN111381876B (en) | 2018-12-28 | 2018-12-28 | move instruction decoding method, data moving method, decoder and data access device |
| PCT/CN2019/121056 WO2020114283A1 (en) | 2018-12-07 | 2019-11-26 | Data processing method and device |
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