CN111371473A - Debugging method of radio frequency circuit - Google Patents
Debugging method of radio frequency circuit Download PDFInfo
- Publication number
- CN111371473A CN111371473A CN202010161091.2A CN202010161091A CN111371473A CN 111371473 A CN111371473 A CN 111371473A CN 202010161091 A CN202010161091 A CN 202010161091A CN 111371473 A CN111371473 A CN 111371473A
- Authority
- CN
- China
- Prior art keywords
- frequency
- frequency dividing
- impedance
- debugging
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/28—Impedance matching networks
- H03H11/30—Automatic matching of source impedance to load impedance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Abstract
The application discloses a debugging method of a radio frequency circuit. The radio frequency circuit comprises a frequency divider, wherein the frequency divider comprises a common terminal and a plurality of frequency dividing terminals; the method comprises the following steps: debugging the load impedance at the common end to a preset optimal impedance; respectively taking each frequency dividing end in the plurality of frequency dividing ends as a first frequency dividing end, and selecting a load connected with preset optimal impedance at a second frequency dividing end; the second frequency dividing end is the other frequency dividing end except the first frequency dividing end in the plurality of frequency dividing ends; and debugging the load impedance from the first frequency dividing end to the common end into the preset optimal impedance so as to ensure that the insertion loss from each frequency dividing end to the common end is minimum and improve the performance of the radio frequency circuit.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method for debugging a radio frequency circuit.
Background
In the radio frequency circuit, a frequency divider is often connected to an antenna to divide the frequency of signals of different frequency bands received by the antenna, for example, a GPS, WIFI2.4G, WIFI 5G frequency divider. If the matching and debugging of the frequency divider are not good, the isolation between the frequency divider ports cannot meet the requirements of the radio frequency circuit, the insertion loss from each frequency dividing end to a common end (namely an antenna port) is large, and the attenuation to radio frequency signals is large.
Therefore, in the process of debugging the radio frequency circuit, the load impedance from each frequency dividing end to the common end needs to be debugged to be the optimal impedance so as to ensure that the insertion loss from each frequency dividing end to the common end is minimum. However, since the frequency divider has the characteristic of impedance pulling, the impedance characteristic from each frequency dividing end to the common end is affected by the impedance of other frequency dividing ends, that is, the debugging of the impedance matching of one frequency dividing end affects the impedance matching of the previously debugged frequency dividing end, so that the impedance matching of the previously debugged frequency dividing end deviates from the optimal impedance, the minimum insertion loss from each frequency dividing end to the common end cannot be ensured, and the performance of the radio frequency circuit is reduced.
Disclosure of Invention
The embodiment of the application provides a debugging method of a radio frequency circuit, which can ensure that the insertion loss from each frequency dividing end to a public end is minimum, and improve the performance of the radio frequency circuit.
The embodiment of the application provides a debugging method of a radio frequency circuit, wherein the radio frequency circuit comprises a frequency divider, and the frequency divider comprises a public end and a plurality of frequency dividing ends; the method comprises the following steps:
debugging the load impedance at the common end to a preset optimal impedance;
respectively taking each frequency dividing end in the plurality of frequency dividing ends as a first frequency dividing end, and selecting a load connected with preset optimal impedance at a second frequency dividing end; the second frequency dividing end is the other frequency dividing end except the first frequency dividing end in the plurality of frequency dividing ends;
and debugging the load impedance from the first frequency dividing end to the common end to the preset optimal impedance.
In some embodiments of the present application, the adjusting the load impedance at the common end to a preset optimal impedance specifically includes:
selecting a first matching circuit to be switched in at the common end;
and debugging the first matching circuit to enable the load impedance at the common end to be the preset optimal impedance.
In some embodiments of the present application, the selecting, at the second frequency-dividing terminal, a load connected to a preset optimal impedance specifically includes:
and selecting a resistor connected with preset optimal impedance to the ground at the second frequency dividing end.
In some embodiments of the present application, the tuning the load impedance from the first frequency-dividing end to the common end to the preset optimal impedance specifically includes:
selecting a second matching circuit to be accessed at the first frequency division end;
and debugging the second matching circuit to enable the load impedance from the first frequency division end to the common end to be the preset optimal impedance.
In some embodiments of the present application, the method further comprises:
and after the radio frequency circuit is debugged, measuring the isolation between any two frequency dividing ends in the plurality of frequency dividing ends.
In some embodiments of the present application, the measuring the isolation between any two of the plurality of crossover ends specifically includes:
taking any two frequency dividing ends of the plurality of frequency dividing ends as two third frequency dividing ends respectively, and selecting loads with preset optimal impedance at the common end and the fourth frequency dividing ends; the fourth frequency division end is the other frequency division end except the two third frequency division ends in the plurality of frequency division ends;
and measuring the isolation between the two third frequency dividing ends.
In some embodiments of the present application, the method further comprises:
after the radio frequency circuit is debugged, the debugged first matching circuit is accessed at the public end, and the corresponding debugged second matching circuit is accessed at each frequency dividing end.
In some embodiments of the present application, the radio frequency circuit further includes an antenna and a crossover path in one-to-one correspondence with the plurality of crossover ports;
the method further comprises the following steps:
and connecting the debugged first matching circuit between the antenna and the public end, and connecting each debugged second matching circuit between the corresponding frequency division end and the frequency division path.
In some embodiments of the present application, when the load with the preset optimal impedance is selected to be connected to the second frequency-dividing terminal, the load with the preset optimal impedance is placed close to the second frequency-dividing terminal.
In some embodiments of the present application, the preset optimal impedance is 50 ohms.
The application provides a debugging method of a radio frequency circuit, load impedance at a common end of a frequency divider can be debugged to preset optimal impedance, each frequency dividing end of a plurality of frequency dividing ends of the frequency divider is used as a first frequency dividing end, loads with the preset optimal impedance are selected to be accessed at second frequency dividing ends except the first frequency dividing ends of the frequency dividing ends, the load impedance from the first frequency dividing ends to the common end is debugged to the preset optimal impedance, namely when the impedance of each frequency dividing end is debugged to be matched, the load impedance of other ports is fixed to the preset optimal impedance, impedance traction is avoided, thus the optimal debugging of the radio frequency circuit is ensured, the insertion loss performance from each frequency dividing end to the common end is ensured to be minimum, and the performance of the radio frequency circuit is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart of a debugging method of a radio frequency circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a debugging system of a radio frequency circuit according to an embodiment of the present application;
fig. 3 is another schematic structural diagram of a debugging system of a radio frequency circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, fig. 1 is a schematic flowchart of a debugging method of a radio frequency circuit provided in an embodiment of the present application. The radio frequency circuit comprises a frequency divider 1, wherein the frequency divider 1 comprises a public end ANT and a plurality of frequency dividing ends PIN1, PIN2, … and PINn, and n is larger than or equal to 2. The radio frequency circuit may further comprise an antenna 2, and the antenna 2 may be connected to the common terminal ANT of the frequency divider 1, and configured to transmit signals of multiple frequency bands to the common terminal ANT of the frequency divider 1. The rf circuit may further include a plurality of frequency dividing paths 3, the plurality of frequency dividing paths 3 may be connected to the plurality of frequency dividing terminals PIN1, PIN2, …, PINn in a one-to-one correspondence manner, and after the frequency divider 1 divides the frequency of the plurality of frequency bands input by the common terminal ANT, the signals of the plurality of frequency bands are respectively transmitted to the plurality of frequency dividing paths 3 through the plurality of frequency dividing terminals PIN, as shown in fig. 2.
As shown in fig. 1, the debugging method of the radio frequency circuit may include the following steps:
101. and debugging the load impedance at the common end to a preset optimal impedance.
In the embodiment of the present application, the load impedance at the common terminal ANT of the frequency divider 1 refers to an impedance between the common terminal ANT and the antenna 2, and the preset optimal impedance may be 50 ohms. The tuning of the load impedance at the common terminal ANT to the preset optimal impedance means that the impedance between the common terminal ANT and the antenna 2 is 50 ohm.
In the debugging process of the radio frequency circuit, a common pad compatible bit can be designed at the common terminal ANT and each frequency dividing terminal PINi of the frequency divider 1, that is, a load 11 and a first matching circuit 12 with preset optimal impedance are arranged at the common terminal ANT, the load 11 or the first matching circuit 12 with preset optimal impedance can be selected to be connected to the common terminal ANT, the load 11 and a second matching circuit 13 with preset optimal impedance are arranged at each frequency dividing terminal PINi (i is more than or equal to 1 and less than or equal to n), and the load 11 or the second matching circuit 13 with preset optimal impedance can be selected to be connected to each frequency dividing terminal PINi.
When the load impedance at the common terminal ANT is adjusted, the first matching circuit 12 may be selectively connected to the common terminal ANT. Specifically, the debugging the load impedance at the common end to the preset optimal impedance in step 101 includes:
selecting a first matching circuit to be switched in at the common end;
and debugging the first matching circuit to enable the load impedance at the common end to be the preset optimal impedance.
It should be noted that, after the first matching circuit 12 is selectively connected to the common terminal ANT, the first matching circuit 12 is connected between the common terminal ANT and the antenna 2, and meanwhile, the load 11 with the preset optimal impedance may be selectively connected to each frequency dividing terminal PINi, and then the load impedance at the common terminal ANT is debugged, so as to ensure that the load impedance at the debugged common terminal ANT is not affected by the impedance matching of the subsequent frequency dividing terminals PINs, that is, impedance pulling is avoided.
Since the first matching circuit 12 is connected between the common terminal ANT and the antenna 2, the load impedance at the common terminal ANT can be tuned to a preset optimum impedance by tuning the first matching circuit 12. As shown in fig. 3, the first matching circuit 12 may include a first element R32, a second element R33, and a third element R34, the first element R32 and the third element R34 being connected in series between the common terminal ANT of the frequency divider 1 and the antenna 2, one end of the second element R32 being connected to a connection point between the first element R32 and the third element R34, the other end of the second element R32 being grounded. The first, second, and third elements R32, R33, R34, respectively, may be resistors, capacitors, or inductors.
In the debugging process, a network analyzer may be used to detect a load impedance at the common terminal ANT, connect one end of the network analyzer to the common terminal ANT, and connect the other end of the network analyzer to a connection point between the third element R34 and the antenna 2, and simultaneously disconnect the antenna 2, and debug the types and the values of the first element R32, the second element R33, and the third element R34, so that an impedance curve detected on the network analyzer converges around a preset optimal impedance (50 ohms), thereby debugging the load impedance at the common terminal ANT to the preset optimal impedance.
102. Respectively taking each frequency dividing end in the plurality of frequency dividing ends as a first frequency dividing end, and selecting a load connected with preset optimal impedance at a second frequency dividing end; the second frequency dividing terminal is the other frequency dividing terminals except the first frequency dividing terminal in the plurality of frequency dividing terminals.
In the embodiment of the application, the load impedance from each frequency dividing end PINi to the common end ANT is debugged in sequence, when one frequency dividing end is selected for debugging, the frequency dividing end is used as a first frequency dividing end, and other unselected frequency dividing ends are used as second frequency dividing ends. For example, the frequency divider has two frequency dividing terminals PIN1 and PIN2, and when debugging the load impedance from the frequency dividing terminal PIN1 to the common terminal ANT, the frequency dividing terminal PIN1 is used as the first frequency dividing terminal, and the frequency dividing terminal PIN2 is used as the second frequency dividing terminal, and similarly, when debugging the load impedance from the frequency dividing terminal PIN2 to the common terminal ANT, the frequency dividing terminal PIN2 is used as the first frequency dividing terminal, and the frequency dividing terminal PIN1 is used as the second frequency dividing terminal.
Since each frequency dividing end is designed with a common pad compatible bit, the load 11 with the preset optimal impedance is selected to be connected to the second frequency dividing end, and the second matching circuit 13 is disconnected, that is, the load impedance at the second frequency dividing end is fixed to the preset optimal impedance, so as to avoid impedance pulling.
Specifically, the selecting and connecting a load with a preset optimal impedance at the second frequency-dividing end includes:
and selecting a resistor connected with preset optimal impedance to the ground at the second frequency dividing end.
It should be noted that the load 11 with the preset optimal impedance may be a resistor, and the resistance value of the resistor is the preset optimal impedance, when the resistor is connected to the second frequency dividing terminal, one end of the resistor is connected to the second frequency dividing terminal, and the other end of the resistor is grounded. As shown in fig. 3, at the divider PIN1, the load 11 with the preset optimal impedance is a resistor R11, and at the divider PIN2, the load 11 with the preset optimal impedance is a resistor R21.
103. And debugging the load impedance from the first frequency dividing end to the common end to the preset optimal impedance.
In the embodiment of the present application, the load impedance at the common end ANT has been debugged to be the preset optimal impedance, and the load impedance at the second frequency dividing end has been fixed to be the preset optimal impedance, so that the load impedance from the first frequency dividing end to the common end ANT has been debugged to be the preset optimal impedance, and the impedance matching of other frequency dividing ends is not affected, and the impedance traction is avoided.
Specifically, the adjusting the load impedance from the first frequency dividing end to the common end to the preset optimal impedance in step 103 includes:
selecting a second matching circuit to be accessed at the first frequency division end;
and debugging the second matching circuit to enable the load impedance from the first frequency division end to the common end to be the preset optimal impedance.
It should be noted that the public terminal ANT may be connected to the first tuned matching circuit 12, so that the load impedance at the public terminal ANT is a preset optimal impedance, the second frequency-dividing terminal selects to connect to a load with the preset optimal impedance, the load impedance at the second frequency-dividing terminal is fixed to the preset optimal impedance, the first frequency-dividing terminal selects to connect to the second matching circuit 13, the second matching circuit 13 is connected between the first frequency-dividing terminal and the frequency-dividing path 3 corresponding thereto, and the second matching circuit 13 includes at least one element selected from a resistor, a capacitor, and an inductor.
In the debugging process, a network analyzer can be used to detect the load impedance from a first frequency dividing end to a common end ANT, one end of the network analyzer is connected to a connection point between a second matching circuit 13 and a frequency dividing path 3 corresponding to the first frequency dividing end, the connection of the frequency dividing path 3 is disconnected at the same time, the other end of the network analyzer is connected to a connection point between a first matching circuit 12 and an antenna 2, the connection of the antenna 2 is disconnected at the same time, the element types and the numerical values of each element in the second matching circuit 13 corresponding to the first frequency dividing end are debugged, so that an impedance curve detected on the network analyzer converges around a preset optimal impedance (50 ohms), and thus the load impedance from the first frequency dividing end to the common end ANT is debugged to be the preset optimal impedance.
For example, as shown in fig. 3, when the dividing terminal PIN1 is the first dividing terminal and the dividing terminal PIN2 is the second dividing terminal, the dividing terminal PIN2 is disconnected from the second matching circuit 13, the resistor R21 is selected to be connected, that is, one terminal of the resistor R21 is connected to the dividing terminal PIN2, the other terminal of the resistor R21 is grounded, and the dividing terminal PIN1 is disconnected from the resistor R11 to be connected to the second matching circuit 13. The second matching circuit 13 corresponding to the frequency dividing terminal PIN1 includes a fourth element R12, a fifth element R13 and a sixth element R14, the fourth element R12 and the sixth element R14 are connected in series between the frequency dividing terminal PIN1 and the corresponding frequency dividing path 3, one end of the fifth element R13 is connected to a connection point between the fourth element R12 and the sixth element R14, and the other end of the fifth element R13 is grounded. The fourth element R12, the fifth element R13 and the sixth element R14 may be a resistor, a capacitor or an inductor, respectively.
In the debugging process, one end of a network analyzer is connected to a connection point between the sixth element R14 and the corresponding frequency division path 3, the connection of the corresponding frequency division path 3 is disconnected at the same time, the other end of the network analyzer is connected to a connection point between the third element R34 and the antenna 2, the connection of the antenna 2 is disconnected at the same time, the element types and the numerical values of the fourth element R12, the fifth element R13 and the sixth element R14 are debugged, so that an impedance curve detected on the network analyzer converges around a preset optimal impedance (50ohm), and the load impedance from the frequency division end PIN1 to the common end ANT is debugged to be the preset optimal impedance.
Similarly, as shown in fig. 3, when the frequency dividing terminal PIN1 is the second frequency dividing terminal and the frequency dividing terminal PIN2 is the first frequency dividing terminal, the frequency dividing terminal PIN1 disconnects the second matching circuit 13, the resistor R11 is selected to be connected, that is, one end of the resistor R11 is connected to the frequency dividing terminal PIN1, the other end of the resistor R11 is grounded, and the frequency dividing terminal PIN2 disconnects the resistor R21 and is selected to be connected to the second matching circuit 13. The second matching circuit 13 corresponding to the frequency dividing terminal PIN2 includes a seventh element R22, an eighth element R23, and a ninth element R24, the seventh element R22 and the ninth element R24 are connected in series between the frequency dividing terminal PIN1 and the corresponding frequency dividing path 3, one end of the eighth element R23 is connected to a connection point between the seventh element R22 and the ninth element R24, and the other end of the eighth element R23 is grounded. The seventh element R22, the eighth element R23, and the ninth element R24 may be resistors, capacitors, or inductors, respectively.
In the debugging process, one end of the network analyzer is connected to a connection point between the ninth element R24 and the corresponding frequency dividing path 3, the connection of the corresponding frequency dividing path 3 is simultaneously disconnected, the other end of the network analyzer is connected to a connection point between the third element R34 and the antenna 2, the connection of the antenna 2 is simultaneously disconnected, the element types and the numerical values of the seventh element R22, the eighth element R23 and the ninth element R24 are debugged, so that an impedance curve detected on the network analyzer converges around a preset optimal impedance (50ohm), and thus the load impedance from the frequency dividing end PIN2 to the common end ANT is debugged to be the preset optimal impedance.
Since good isolation is a key of the radio frequency index, after the load impedance from each frequency dividing end PINi to the common end ANT is debugged to be the preset optimal impedance, that is, after the second matching circuit 13 corresponding to each frequency dividing end PINi is debugged, the isolation of the frequency dividing end can be measured.
Specifically, the method further comprises:
and after the radio frequency circuit is debugged, measuring the isolation between any two frequency dividing ends in the plurality of frequency dividing ends.
It should be noted that, any two frequency dividing ends in the multiple frequency dividing ends are selected to measure the isolation, and whether the isolation meets the isolation requirement of the frequency divider is detected, if yes, the debugged radio frequency circuit can be applied to the mobile terminal, and if not, the reason is checked, or the radio frequency circuit is debugged continuously until the isolation of the frequency divider meets the requirement.
Specifically, the measuring the isolation between any two of the plurality of crossover ends specifically includes:
taking any two frequency dividing ends of the plurality of frequency dividing ends as two third frequency dividing ends, and selecting loads with preset optimal impedance at the common end and the fourth frequency dividing ends; the fourth frequency division end is the other frequency division end except the two third frequency division ends in the plurality of frequency division ends;
and measuring the isolation between the two third frequency dividing ends.
In the embodiment of the present application, if the plurality of frequency dividing ends are two frequency dividing ends, the two frequency dividing ends are used as third frequency dividing ends, a load 11 with a preset optimal impedance is selectively connected to a common end ANT, the first matching circuit 12 is disconnected, the load impedance at the common end ANT is a fixed preset optimal impedance, a second matching circuit 13 after debugging is selectively connected to each third frequency dividing end, the load 11 with the preset optimal impedance is disconnected, and a network analyzer is used to measure the isolation between the two third frequency dividing ends. As shown in fig. 3, when the load with the preset optimal impedance is selected to be connected to the common terminal ANT, one end of the resistor R31 is connected to the common terminal ANT, and the other end of the resistor R31 is grounded.
If the plurality of frequency dividing ends are at least three frequency dividing ends, two frequency dividing ends are arbitrarily selected as third frequency dividing ends, the other unselected frequency dividing ends are fourth frequency dividing ends, a load 11 with preset optimal impedance is selected to be connected to the common end ANT, the first matching circuit 12 is disconnected, the load impedance at the common end ANT is made to be fixed preset optimal impedance, the load 11 with the preset optimal impedance is selected to be connected to the fourth frequency dividing end, the second matching circuit 13 is disconnected, the load impedance at the fourth frequency dividing end is made to be fixed preset optimal impedance, the second matching circuit 13 after debugging is selected to be connected to each third frequency dividing end, the load 11 with the preset optimal impedance is disconnected, and the isolation degree between the two third frequency dividing ends is measured by adopting a network analyzer.
It should be noted that, during debugging and measuring isolation, if a load with a preset optimal impedance is selected to be connected to the common terminal ANT, the load (such as the resistor R31) is placed close to the common terminal ANT of the frequency divider 1; if the first matching circuit 12 is selected to be connected to the common terminal ANT, the element (e.g., the first element R32) connected to the common terminal ANT in the first matching circuit 12 is placed close to the common terminal ANT of the frequency divider 1. If the load with the preset optimal impedance is selected to be connected to the frequency dividing end PINi, the load (such as a resistor R11 or a resistor R21) is placed close to the frequency dividing end PINi of the frequency divider 1; if the second matching circuit 13 is selected to be connected to the frequency dividing end PINi, the element (e.g., the fourth element R12 or the seventh element R22) connected to the frequency dividing end PINi in the second matching circuit 13 is placed close to the frequency dividing end PINi of the frequency divider 1. This embodiment can conveniently debug the minimum with the insertion loss performance of each frequency division end to the public end through the mode of placing of hugging closely, further improves the debugging effect.
And after the isolation degree of the frequency divider meets the isolation requirement of the frequency divider, the debugging result can be applied to the radio frequency circuit. Specifically, the method further comprises:
after the radio frequency circuit is debugged, the debugged first matching circuit is accessed at the public end, and the corresponding debugged second matching circuit is accessed at each frequency dividing end.
Further, the method further comprises:
and connecting the debugged first matching circuit between the antenna and the public end, and connecting each debugged second matching circuit between the corresponding frequency division end and the frequency division path.
It should be noted that after the debugging and the isolation measurement are completed, the load with the preset optimal impedance at each port is removed, and only the first matching circuit 12 is reserved at the common terminal ANT, so that the first matching circuit 12 is connected between the antenna 2 and the common terminal ANT, only the second matching circuit 13 is reserved at each frequency dividing terminal PINi, so that the second matching circuit 13 is connected between the corresponding frequency dividing terminal PINi and the frequency dividing path 3, thereby forming the radio frequency circuit. The radio frequency circuit can be applied to a mobile terminal, and the mobile terminal can comprise mobile equipment such as a mobile phone and a tablet personal computer.
As can be seen from the above, the method for debugging a radio frequency circuit provided in the present application can debug the load impedance at the common end of the frequency divider to the preset optimal impedance, and further use each of the multiple frequency dividing ends of the frequency divider as the first frequency dividing end, select the load connected to the preset optimal impedance at the second frequency dividing end except the first frequency dividing end among the multiple frequency dividing ends, and debug the load impedance from the first frequency dividing end to the common end to the preset optimal impedance, that is, when the impedances of each frequency dividing end are debugged to be matched, fix the load impedances of other ports to the preset optimal impedance, and avoid impedance pulling, thereby ensuring optimal debugging of the radio frequency circuit, ensuring that the insertion loss performance from each frequency dividing end to the common end is minimum, and improving the performance of the radio frequency circuit.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. The debugging method of a radio frequency circuit is characterized in that the radio frequency circuit comprises a frequency divider, wherein the frequency divider comprises a public end and a plurality of frequency dividing ends; the method comprises the following steps:
debugging the load impedance at the common end to a preset optimal impedance;
respectively taking each frequency dividing end in the plurality of frequency dividing ends as a first frequency dividing end, and selecting a load connected with preset optimal impedance at a second frequency dividing end; the second frequency dividing end is the other frequency dividing end except the first frequency dividing end in the plurality of frequency dividing ends;
and debugging the load impedance from the first frequency dividing end to the common end to the preset optimal impedance.
2. The method for debugging a radio frequency circuit according to claim 1, wherein the debugging a load impedance at the common terminal to a preset optimal impedance specifically comprises:
selecting a first matching circuit to be switched in at the common end;
and debugging the first matching circuit to enable the load impedance at the common end to be the preset optimal impedance.
3. The method for debugging a radio frequency circuit according to claim 1, wherein the selecting a load connected to a preset optimal impedance at the second frequency-dividing terminal specifically comprises:
and selecting a resistor connected with preset optimal impedance to the ground at the second frequency dividing end.
4. The method for tuning a radio frequency circuit according to claim 2, wherein tuning the load impedance from the first frequency-dividing terminal to the common terminal to the preset optimal impedance specifically includes:
selecting a second matching circuit to be accessed at the first frequency division end;
and debugging the second matching circuit to enable the load impedance from the first frequency division end to the common end to be the preset optimal impedance.
5. The method of debugging a radio frequency circuit of claim 1, further comprising:
and after the radio frequency circuit is debugged, measuring the isolation between any two frequency dividing ends in the plurality of frequency dividing ends.
6. The method for debugging a radio frequency circuit according to claim 5, wherein the measuring the isolation between any two of the plurality of divided ends specifically comprises:
taking any two frequency dividing ends of the plurality of frequency dividing ends as two third frequency dividing ends respectively, and selecting loads with preset optimal impedance at the common end and the fourth frequency dividing ends; the fourth frequency division end is the other frequency division end except the two third frequency division ends in the plurality of frequency division ends;
and measuring the isolation between the two third frequency dividing ends.
7. The method of debugging a radio frequency circuit of claim 4, further comprising:
after the radio frequency circuit is debugged, the debugged first matching circuit is accessed at the public end, and the corresponding debugged second matching circuit is accessed at each frequency dividing end.
8. The method for debugging a radio frequency circuit according to claim 7, wherein the radio frequency circuit further comprises an antenna and frequency division paths in one-to-one correspondence with the plurality of frequency division ends;
the method further comprises the following steps:
and connecting the debugged first matching circuit between the antenna and the public end, and connecting each debugged second matching circuit between the corresponding frequency division end and the frequency division path.
9. The method for debugging a radio frequency circuit according to claim 1, wherein when the load with the preset optimal impedance is selected to be connected to the second frequency-dividing terminal, the load with the preset optimal impedance is placed in close proximity to the second frequency-dividing terminal.
10. The method of claim 1, wherein the predetermined optimal impedance is 50 ohm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010161091.2A CN111371473B (en) | 2020-03-10 | 2020-03-10 | Debugging method of radio frequency circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010161091.2A CN111371473B (en) | 2020-03-10 | 2020-03-10 | Debugging method of radio frequency circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111371473A true CN111371473A (en) | 2020-07-03 |
| CN111371473B CN111371473B (en) | 2021-09-28 |
Family
ID=71211699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010161091.2A Active CN111371473B (en) | 2020-03-10 | 2020-03-10 | Debugging method of radio frequency circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111371473B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037397A (en) * | 2021-03-02 | 2021-06-25 | 苏州天希电子科技有限公司 | 5G antenna interface board port isolation measurement system |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221881A (en) * | 2007-01-12 | 2008-07-16 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Impedance matching method and device |
| CN101459476A (en) * | 2007-12-13 | 2009-06-17 | 启碁科技股份有限公司 | Method for tuning wireless radio frequency circuit by impedance load characteristic |
| CN201663237U (en) * | 2010-03-17 | 2010-12-01 | 宇龙计算机通信科技(深圳)有限公司 | Antenna and mobile terminal |
| US20160006422A1 (en) * | 2014-07-02 | 2016-01-07 | Qualcomm Incorporated | Low power frequency divider using dynamic modulated-load latch |
| CN106099370A (en) * | 2015-04-29 | 2016-11-09 | 联发科技股份有限公司 | Antenna system, harmonics restraint element and radio-frequency unit |
| CN108923867A (en) * | 2018-07-18 | 2018-11-30 | Oppo广东移动通信有限公司 | Radio circuit adjustment method and relevant apparatus |
| CN108964801A (en) * | 2018-07-18 | 2018-12-07 | Oppo广东移动通信有限公司 | Radio circuit adjustment method and relevant apparatus |
| CN109150326A (en) * | 2018-11-05 | 2019-01-04 | Oppo（重庆）智能科技有限公司 | Antenna impedance adjustment method, electronic device and computer readable storage medium |
| CN110473764A (en) * | 2019-09-06 | 2019-11-19 | 深圳市百世达半导体设备有限公司 | A kind of impedance adjusting method and radio-frequency power system based on radio-frequency power supply |
-
2020
- 2020-03-10 CN CN202010161091.2A patent/CN111371473B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221881A (en) * | 2007-01-12 | 2008-07-16 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Impedance matching method and device |
| CN101459476A (en) * | 2007-12-13 | 2009-06-17 | 启碁科技股份有限公司 | Method for tuning wireless radio frequency circuit by impedance load characteristic |
| CN201663237U (en) * | 2010-03-17 | 2010-12-01 | 宇龙计算机通信科技(深圳)有限公司 | Antenna and mobile terminal |
| US20160006422A1 (en) * | 2014-07-02 | 2016-01-07 | Qualcomm Incorporated | Low power frequency divider using dynamic modulated-load latch |
| CN106099370A (en) * | 2015-04-29 | 2016-11-09 | 联发科技股份有限公司 | Antenna system, harmonics restraint element and radio-frequency unit |
| CN108923867A (en) * | 2018-07-18 | 2018-11-30 | Oppo广东移动通信有限公司 | Radio circuit adjustment method and relevant apparatus |
| CN108964801A (en) * | 2018-07-18 | 2018-12-07 | Oppo广东移动通信有限公司 | Radio circuit adjustment method and relevant apparatus |
| CN109150326A (en) * | 2018-11-05 | 2019-01-04 | Oppo（重庆）智能科技有限公司 | Antenna impedance adjustment method, electronic device and computer readable storage medium |
| CN110473764A (en) * | 2019-09-06 | 2019-11-19 | 深圳市百世达半导体设备有限公司 | A kind of impedance adjusting method and radio-frequency power system based on radio-frequency power supply |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113037397A (en) * | 2021-03-02 | 2021-06-25 | 苏州天希电子科技有限公司 | 5G antenna interface board port isolation measurement system |
| CN113037397B (en) * | 2021-03-02 | 2022-05-13 | 苏州天希电子科技有限公司 | 5G antenna interface board port isolation measurement system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111371473B (en) | 2021-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9954564B2 (en) | Electromagnetic couplers with multi-band filtering | |
| US8773216B2 (en) | Selectivity of a dual coupler | |
| CN105428772A (en) | System and Method for a Directional Coupler Module | |
| US20100244981A1 (en) | Radio frequency power divider and combiner circuit | |
| CN110286347B (en) | Electronic calibration piece, calibration system, method, device and storage medium | |
| KR20170093208A (en) | Adjustable rf coupler | |
| US8384494B2 (en) | Multiband coupling circuit | |
| CN108964695B (en) | Radio frequency circuit debugging method and related device | |
| US9647742B2 (en) | Antenna architecture and operational method for RF test connector reduction | |
| EP3716396A1 (en) | Antenna, and communication device | |
| CN111371473B (en) | Debugging method of radio frequency circuit | |
| US9899734B2 (en) | Front end circuit and wireless communication device | |
| AU594984B2 (en) | Improvements to pin diode attenuators | |
| US20220359971A1 (en) | Coupler with switchable decoupled components | |
| US9240766B2 (en) | Wide-band coupler | |
| TWI676352B (en) | Combiner/splitter and method of operating thereof | |
| CN108900260B (en) | Radio frequency circuit debugging method and related device | |
| CN108964801B (en) | Radio frequency circuit debugging method and related device | |
| US9654150B2 (en) | Module with duplexers coupled to diplexer | |
| US8810333B2 (en) | Multiband coupling architecture | |
| CN110176966B (en) | Radio frequency circuit debugging method and device and computer readable storage medium | |
| CN108964816B (en) | Radio frequency circuit debugging method and related device | |
| CN108923868B (en) | Radio frequency circuit debugging method and related device | |
| CN105738738A (en) | Radio frequency test device and system | |
| CN111384908A (en) | Power divider circuit, power divider and design method of power divider circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |