CN111370335A - Wafer level system packaging method - Google Patents

Wafer level system packaging method Download PDF

Info

Publication number
CN111370335A
CN111370335A CN201811608042.8A CN201811608042A CN111370335A CN 111370335 A CN111370335 A CN 111370335A CN 201811608042 A CN201811608042 A CN 201811608042A CN 111370335 A CN111370335 A CN 111370335A
Authority
CN
China
Prior art keywords
chip
device wafer
plastic package
layer
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201811608042.8A
Other languages
Chinese (zh)
Other versions
CN111370335B (en
Inventor
秦晓珊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Core Integrated Circuit Ningbo Co Ltd
Original Assignee
China Core Integrated Circuit Ningbo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Core Integrated Circuit Ningbo Co Ltd filed Critical China Core Integrated Circuit Ningbo Co Ltd
Priority to CN201811608042.8A priority Critical patent/CN111370335B/en
Publication of CN111370335A publication Critical patent/CN111370335A/en
Application granted granted Critical
Publication of CN111370335B publication Critical patent/CN111370335B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention provides a wafer level system packaging method, which comprises the following steps: forming a bonding structure, the bonding structure comprising: the device comprises a device wafer and a plurality of chips bonded to the device wafer, wherein the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; a plastic package area is enclosed between the adjacent chips and the device wafer; carrying out selective spraying treatment, spraying a plastic packaging material to the plastic packaging area, and carrying out curing treatment on the plastic packaging material to form a plastic packaging layer covering the device wafer and the side wall of the chip; forming a groove surrounding each first chip in the plastic packaging layer; forming a conductive material in the trench and over the first chip; the conductive material in the groove is a conductive side wall, and the conductive material above the first chip is a conductive layer and is used for being connected with the conductive side wall to form a shielding shell. The invention improves the packaging yield.

Description

Wafer level system packaging method
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a wafer level system packaging method and a wafer level system packaging structure.
Background
With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like.
At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts Wafer Level Package System In Package (WLPSiP), and compared with the conventional System packaging, the Wafer Level System packaging completes a packaging integration process on a Wafer, so that the Wafer Level System packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.
The integrated circuit is easily influenced by an external magnetic field in the use process, so that the problem of unstable performance is caused. The prior art reduces the interference of an external magnetic field by arranging a shielding structure in an integrated circuit, however, the integrated circuit with the shielding function has the problems of large volume and thickness.
Disclosure of Invention
The invention provides a wafer level system packaging method, which improves the packaging yield.
In order to solve the technical problem, the invention provides a wafer level system packaging method, which comprises the following steps: forming a bonding structure, the bonding structure comprising: the device comprises a device wafer and a plurality of chips bonded to the device wafer, wherein the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; a plastic packaging area is enclosed between the adjacent chips and the device wafer; carrying out selective spraying treatment, spraying a plastic packaging material to the plastic packaging area, and carrying out curing treatment on the plastic packaging material to form a plastic packaging layer covering the device wafer and the side wall of the chip; forming a groove surrounding each first chip in the plastic packaging layer; forming a conductive material in the trench and over the first chip; the conductive material in the groove is a conductive side wall, and the conductive material above the first chip is a conductive layer and is used for being connected with the conductive side wall to form a shielding shell.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, the plastic packaging layer is formed by spraying the plastic packaging material to the plastic packaging area, and the plastic packaging layer covering the side wall of the chip is formed, so that the problem that the chip in the existing plastic packaging layer is subjected to injection molding pressure is avoided, and the chip is prevented from deforming or cracking; therefore, the system-in-package method provided by the invention can improve the packaging yield.
Drawings
FIG. 1 is a schematic diagram of a wafer level system package structure;
fig. 2 to 10 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level system packaging method according to the present invention.
Detailed Description
As can be seen from the background art, the performance of the package structure manufactured by the conventional wafer level packaging method needs to be improved.
Referring to fig. 1, a wafer level system package structure includes: the semiconductor device includes a device wafer 10 and a plurality of chips 20 bonded to the device wafer 10, wherein a chip to be shielded in the plurality of chips 20 is a first chip 13; a molding layer 12 covering the plurality of chips 20; the conductive sidewalls 151 located in the molding compound layer 12 and surrounding each of the first chips 13, and the conductive material located on the surface of the molding compound layer 12 above the first chip 13 is a conductive layer 152 for forming a shielding shell 15 with the conductive sidewalls 151.
The process of forming the molding layer 12 is generally an injection molding process (molding), and specifically, includes the steps of: firstly, placing a device wafer 10 and a chip 20 (including a first chip 13 to be shielded) in a lower die cavity, and injecting a liquid plastic package material into the lower die cavity; closing the upper die, pushing the upper die by using an injector, simultaneously heating the whole die, and wrapping the chip 20 by the plastic package material in the die cavity of the lower die; the molding compound is solidified and molded after being cooled, and is combined with the chip 20 to form the molding layer 12, so as to protect the chip 20.
However, in the above injection molding process, the chip 20 is subjected to a large injection molding pressure, and the injection molding pressure makes the chip 20 susceptible to deformation and even fracture, thereby causing package structural performance failure and package failure. Moreover, the molding compound layer 12 formed by the injection molding process generally wraps the chip 20 in a full-covering manner, that is, the packaging layer 12 covers the surface of the device wafer 10, the side wall of the chip 20, and the surface of the chip 20 facing away from the device wafer 10, so that the inside of the packaging layer 12 has a large internal stress (stress), which may also cause the chip 20 to deform or even break, resulting in package failure.
In order to solve the technical problem, the invention provides a wafer level system packaging method, which comprises the following steps: forming a bonding structure, the bonding structure comprising: the device comprises a device wafer and a plurality of chips bonded to the device wafer, wherein the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; a plastic packaging area is enclosed between the adjacent chips and the device wafer; carrying out selective spraying treatment, spraying a plastic packaging material to the plastic packaging area, and carrying out curing treatment on the plastic packaging material to form a plastic packaging layer covering the device wafer and the side wall of the chip; forming a groove surrounding each first chip in the plastic packaging layer; forming a conductive material in the trench and over the first chip; the conductive material in the groove is a conductive side wall, and the conductive material above the first chip is a conductive layer and is used for being connected with the conductive side wall to form a shielding shell.
The embodiment of the invention forms the plastic packaging layer by spraying the plastic packaging material to the plastic packaging area, and forms the plastic packaging layer covering the side wall of the chip, thereby avoiding the problem that the chip in the existing plastic packaging layer is subjected to injection molding pressure, preventing the chip from deforming or cracking, and forming the plastic packaging layer only covering the side wall of the chip by adopting a selective spraying treatment mode, so that the internal stress of the plastic packaging layer is small, the interface performance between the corresponding plastic packaging layer and the chip is good, the adhesion between the two layers is strong, and the plastic packaging layer is ensured to have good sealing effect on the chip; therefore, the system-in-package method provided by the invention can improve the packaging yield.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 10 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level system packaging method according to the present invention. The wafer level system packaging method of the embodiment comprises the following steps:
as shown in fig. 2 and 3, fig. 3 is a cross-sectional view taken along a-a direction in fig. 2, and a bonding structure is formed, the bonding structure including: the device comprises a device wafer 10 and a plurality of chips 20 bonded to the device wafer 10, wherein the chips to be shielded in the plurality of chips 20 are first chips 13, and the number of the first chips 13 is one or more; a plastic package area I is defined between the adjacent chip 20 and the device wafer 10. It should be noted that the present embodiment takes one first chip 13 as an example for description.
The device wafer 10 is a wafer to be packaged for completing device fabrication. In this embodiment, the semiconductor substrate of the device wafer 10 is a silicon substrate. In other embodiments, the material of the semiconductor substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the semiconductor substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration. The device wafer 10 has a thickness of 10 to 100 microns, depending on the actual process requirements.
A plurality of second chips 11 are formed in the device wafer 10. Specifically, the device wafer 10 with the second chips 11 is a wafer front side 101, a surface facing away from the wafer front side 101 is a wafer back side 102, and the plurality of chips 20 are bonded to the wafer front side 101 of the device wafer 10.
A plurality of chips 20 bonded on the device wafer 10 are used as chips to be integrated in a wafer level system package. The wafer level system packaging method of the present embodiment is used for implementing heterogeneous integration, and accordingly, the plurality of chips 20 may be chips made of silicon wafers or chips made of other materials.
The number of the chips 20 is at least one, and when the number of the chips 20 is plural, the functions of the chips 20 are different. The chip 20 may be made by using integrated circuit fabrication technology, and may be a memory chip, a communication chip, a processor or a logic chip. The die 20 typically includes devices such as NMOS devices or PMOS devices formed on a semiconductor substrate.
Specifically, the bonding of the chip 20 and the device wafer 10 may be achieved by fusion bonding, adhesive bonding, or glass dielectric bonding.
Among the plurality of chips 20, the first chip 13 is relatively susceptible to the influence of an external magnetic field, and is a chip to be shielded, and a lead Pad (Pad)130 is formed in the first chip 13 for electrically connecting the first chip 13. The surface of the first chip 13 close to the lead bonding pad 130 is a chip front surface 131, and the surface opposite to the chip front surface 131 is a chip back surface 132. In this embodiment, the chip front side 131 of the first chip 13 is bonded to the wafer front side 101 of the device wafer 10.
The plastic package area is an area where a plastic package layer is to be formed. Specifically, a plastic package region I is defined between the adjacent chips 20 and the device wafer 10.
In this embodiment, as shown in fig. 3, the chips 20 are distributed on the device wafer 10 in an array along the X direction and the Y direction, and a plurality of rows of plastic package regions and a plurality of columns of plastic package regions are defined between the chips 20 distributed in the array and the device wafer 10.
As shown in fig. 4, a selective spraying process is performed, a plastic package material is sprayed to the plastic package region I, and the plastic package material is cured to form a plastic package layer 12 covering the device wafer 10 and the side walls of the chips 20 (including the side walls of the first chips 13).
Currently, an injection molding process is usually adopted to form a plastic package layer, and the embodiment adopts a selective spraying treatment mode to avoid the problem that the chip 20 is subjected to injection molding pressure in the existing plastic package layer 12, so that the chip 20 is prevented from deforming or cracking; in addition, the plastic package layer 12 only covering the side wall of the chip 20 can be formed by adopting a selective spraying treatment mode, so that the internal stress of the plastic package layer 12 is small, the corresponding interface performance between the plastic package layer 12 and the chip 20 is good, the adhesion between the two is strong, and the plastic package layer 12 is ensured to have a good sealing effect on the chip 20. Therefore, the system-in-package method provided by the invention can improve the performance of the formed package structure so as to improve the package yield.
In addition, the plastic package layer 12 is formed by adopting a selective spraying treatment mode, the process flexibility is high, the thickness of the formed plastic package layer 12 is controlled by reasonably controlling the amount of the plastic package material sprayed by the selective spraying treatment according to different requirements of the packaging process, and the plastic package layer 12 is easy to cover the side wall of the chip 20.
The molding compound layer 12 can perform the functions of insulation, sealing and moisture protection, and can reduce the probability that the chip 20 is damaged, contaminated or oxidized, thereby facilitating the optimization of the performance of the obtained wafer level system packaging structure.
In this embodiment, the molding compound layer 12 also serves to insulate the subsequently formed shielding shell from the first chip 13.
It should be noted that, in this embodiment, the indication that the molding compound layer 12 covers the side wall of the chip 20 is that the molding compound layer 12 covers the entire side wall of the chip 20 or covers a part of the side wall of the chip 20, and in both cases, the quality and the performance of the package structure can be guaranteed.
The plastic package material is a plastic package adhesive with fluidity. In this embodiment, the Molding Compound is an Epoxy Molding Compound (EMC) and includes a matrix resin, a curing agent, a coupling agent, and a filler, where the matrix resin is an Epoxy resin, the curing agent is a phenolic resin, and the coupling agent may be a silica powder or a silica powder. In other embodiments, other suitable molding compounds may be used.
The selective spray coating process includes: providing a movable spray head and a bearing platform; and placing the device wafer 10 on the bearing table, enabling the spray head to move above the device wafer 10, and spraying plastic package materials to the plastic package area I by the spray head when the spray head moves to the position above the plastic package area I.
Specifically, a spraying device is provided, and the spraying device is provided with a movable spray head; the device wafer 10 is placed on a carrier table (chuck) and the selective spray process is completed using a spray device.
In order to improve the thickness uniformity of the plastic package layer 12, in the selective spraying process, the spray head moves over the same plastic package region I at least twice to form the plastic package layer 12. For the same plastic package region I, the plastic package layer 12 is formed by spraying the plastic package material at least twice, and before spraying the plastic package material for the next time, the plastic package material sprayed for the previous time flows on the plastic package region I within a certain time and space, so that when spraying the plastic package material for the next time, the thickness uniformity of the plastic package material sprayed for the previous time is improved, and the thickness uniformity of the finally formed plastic package layer 12 is improved.
In this embodiment, in the selective spraying process, a moving path of the nozzle when the nozzle moves above the plastic package region I for the previous time is a first direction, a path of the nozzle when the nozzle moves above the same plastic package region I for the subsequent time is a second direction, and the second direction is different from the first direction.
The advantages of such an arrangement are: since the thickness distribution of the plastic package materials sprayed to the same plastic package region I by the nozzles from different moving paths has differences, when the nozzles having different moving paths are used for spraying the plastic package materials to the same plastic package region I, the thickness distributions with differences compensate each other, thereby further improving the thickness uniformity of the finally formed plastic package layer 12.
In this embodiment, the chips 20 are distributed on the device wafer 10 in an array manner along the X direction and the Y direction, and a plurality of rows of plastic package regions and a plurality of columns of plastic package regions are defined between the chips 20 distributed in the array manner and the device wafer 10, wherein the plastic package regions along the X direction form the plurality of rows of plastic package regions, and the plastic package regions along the Y direction form the plurality of columns of plastic package regions. Accordingly, the path of travel of the showerhead over the device wafer 10 has directions including: one or more of + X direction, -X direction, + Y direction, and-Y direction.
Specifically, the selective spray coating process includes: at least one X-direction spraying step, wherein the X-direction spraying step comprises the following steps: the spray head moves along the + X direction or the-X direction and passes through the plastic package area I along the X direction until the spray head moves through the plastic package areas I in all the X directions; at least one Y-direction spraying step, wherein the Y-direction spraying step comprises the following steps: the spray head moves along the + Y direction or the-Y direction and passes through the plastic package area I along the Y direction until the spray head moves through the plastic package area I in all the Y directions.
In order to improve the thickness uniformity of the plastic package layer 12 and improve the performance such as the density of the plastic package layer 12, the X-direction spraying step and the Y-direction spraying step may be performed alternately until the plastic package layer 12 with a desired thickness is formed. When the spraying step in the X direction is changed to the spraying step in the Y direction, the spraying may be performed by moving the nozzle, or by rotating the device wafer 10 by 90 ° using the susceptor.
In other embodiments, the step of selectively spraying may further include: at least two X-direction spraying steps, wherein each X-direction spraying step comprises the following steps: the spray head moves along the + X direction and passes through the upper parts of all the plastic packaging areas I in the + X direction; then, the spray head moves along the-X direction and passes above all the plastic package areas I in the-X direction; and the spray head alternately moves along the + X direction and the-X direction until the thickness of the plastic packaging layer meets the process requirement.
It should be further noted that, in the scheme of performing the selective spraying treatment by using the X-direction spraying step of spraying at least twice, for the region outside the plastic package region I and not provided with the chip, the nozzle may spray the plastic package material to the region; if the area is cut and removed in the subsequent cutting treatment process, the plastic package material is not sprayed on the area.
Correspondingly, in other embodiments, the selective spraying treatment may further include at least two Y-direction spraying steps, and the spray head may alternately move in the + Y direction and the-Y direction until the thickness of the molding layer meets the process requirement. In other embodiments, the direction of the moving path of the spray head may further include: an oblique direction at 45 degrees to the X direction or an oblique direction at 45 degrees to the Y direction.
Before the selective spraying treatment, position information of a plastic package area I on the device wafer 10 is acquired; and performing the selective spraying treatment based on the acquired position information.
In this embodiment, the step of obtaining the position information of the plastic package area I includes: the chip 20 is placed on the device wafer 10 based on the preset position information, which is used as the position information of the plastic package region I. In other embodiments, in order to improve the accuracy of the position information and avoid the influence caused by process deviation, the method for obtaining the position information of the plastic package region I may further include: after the chip is placed on the device wafer, the surface of the device wafer is irradiated by light, and the light information reflected by the surface of the device wafer is collected to obtain the position information of the plastic package area I. Since the material of the plastic package region I is different from the material of the chip 20, the position information of the plastic package region I can be obtained by collecting different light information due to different light information reflected by different materials, for example, the position information of the plastic package region I can be obtained by receiving the reflected light information by a camera and generating an image based on the light information by the camera.
Specifically, the method of performing selective spray processing based on the acquired position information includes: the method comprises the steps that when a nozzle moves above a device wafer 10, the real-time position of the nozzle on the device wafer 10 is obtained in real time; and controlling the spray head to spray the plastic package material to the plastic package area I in the process of moving on the device wafer 10 based on the real-time position and the acquired position information. The real-time position may be directly obtained, or may be obtained by converting the initial position of the nozzle, the moving speed of the nozzle, and the moving time of the nozzle.
The plastic package area I is provided with a first boundary and a second boundary which are opposite, the direction of the first boundary pointing to the second boundary is consistent with the moving direction of the spray head, and when the spray head moves through the first boundary and is away from the first boundary by a first distance, the spray head starts to spray plastic package materials; and when the spray head moves to a second distance away from the second boundary and does not exceed the second boundary, the spray head finishes spraying the plastic package material.
The first distance should not be too large. If the first distance is too large, the effective spraying area of the spray head passing through the upper part of the same plastic package area I once is too small, so that the efficiency of selective spraying treatment is reduced. For this reason, in the present embodiment, the first distance ranges from 0 to 30mm, for example, 5mm, 10mm, 15mm, 25 mm.
The second distance should not be too small, nor too large. If the second distance is too small, the plastic packaging material is easily sprayed to an area where spraying is not expected by the spray head; if the second distance is too large, the effective spraying area of the spray head passing through the upper part of the same plastic package area I once is too small, so that the efficiency of selective spraying treatment is reduced. For this purpose, in this embodiment, the second distance ranges from 5nm to 30mm, for example 10mm, 18mm, 23mm, 28 mm.
During the selective spray process, the vertical distance between the showerhead and the device wafer 10 should not be too small or too large. The closer the vertical distance is, the smaller the area of the area sprayed by the spray head in unit time is, and the thicker the thickness of the film layer formed by spraying the plastic package material on the plastic package area I in unit time is, the smaller the thickness uniformity of the formed film layer is, which is not beneficial to improving the thickness uniformity of the plastic package layer 12; the farther the vertical distance is, the more difficult the position accuracy of the spray head spraying the plastic package material is to control, and the loss of the plastic package material is easily caused. For this purpose, in the present embodiment, the vertical distance between the showerhead and the device wafer 10 is 5mm to 30mm, for example, 10mm, 15mm, 20mm, 28 mm.
In the selective spraying process, for the same plastic package area I, as the amount of the plastic package material in the plastic package area I gradually increases, the vertical distance between the nozzle and the device wafer 10 gradually decreases, that is, the vertical distance between the nozzle and the device wafer 10 when the nozzle passes through a certain plastic package area I next time is a first vertical distance, the vertical distance between the nozzle and the device wafer 10 when the nozzle passes through the same plastic package area I last time is a second vertical distance, and the first vertical distance is smaller than the second vertical distance.
In the selective spraying process, the moving speed of the spray head is not too small or too fast. If the moving speed is too low, under the condition that the flow rate of the plastic package material sprayed by the spray head is certain, the amount of the plastic package material sprayed by the spray head in the process of moving through the plastic package area I at a single time is larger, the thickness of a film layer formed in the plastic package area I at a single time is thicker, the uniformity of the thickness of the film layer is relatively poorer, and the improvement of the uniformity of the thickness of the finally formed plastic package layer 12 is not facilitated; if the speed of the head movement is too high, the spraying efficiency of the selective spraying treatment is low, and the packaging efficiency is affected. For this reason, in the present embodiment, the velocity at which the head moves during the selective spray treatment is 0.01m/s to 0.1m/s, for example, 0.03m/s, 0.05m/s, 0.07m/s, 0.9 m/s.
In the selective spraying process, the flow rate of the plastic packaging material sprayed by the spray head is not too small or too large. If the flow is too small, the spraying efficiency of the selective spraying treatment is correspondingly low, and the packaging efficiency is influenced; if the flow is too large, the amount of the plastic packaging material sprayed in the process that the spray head moves through the plastic packaging area I at a single time is large, the thickness of the film layer formed at the plastic packaging area I at a single time is thick, the thickness uniformity of the film layer is relatively poor, and the improvement of the thickness uniformity of the plastic packaging layer 12 is not facilitated. For this reason, in this embodiment, the flow rate of the plastic molding compound sprayed by the nozzle during the selective spraying process is 1ml/s to 10ml/s, such as 2ml/s, 4ml/s, 6ml/s, and 9 ml/s.
It should be noted that, in the present embodiment, a movable spray head is provided to implement the selective spray coating process as an example. In other embodiments, the selective spray coating process may further include: providing a nozzle and a movable carrying platform; and placing the device wafer on a movable carrying platform, moving the device wafer below a spray head, and spraying plastic packaging material to the plastic packaging area I by the spray head when the plastic packaging area I moves to the position below the spray head.
In this embodiment, after the selective spraying treatment is finished, the plastic package material is cured. The curing process is used to cure and shape the molding compound, and during the curing process, a cross-linking reaction occurs inside the molding compound to form the molding layer 12 with bending resistance, moisture resistance and heat resistance. In particular, the curing treatmentThe method comprises the following steps: under vacuum, N2Or baking the plastic package material in an inert gas environment.
In this embodiment, the process temperature used for the curing process should not be too low or too high. If the process temperature is too low, the cross-linking reaction in the plastic packaging material is incomplete in the curing process, so that the plastic packaging effect of the plastic packaging layer 12 is affected; if the process temperature is too high, the performance of the chip 20 is easily affected, and the process temperature is too high, the internal stress of the plastic package layer 12 is relatively large, so that the adhesion between the plastic package layer 12 and the chip 20 is easily reduced, and the plastic package effect of the plastic package layer 12 is easily affected.
For this reason, in this embodiment, the curing process is performed at a temperature of 120 ℃ to 160 ℃, for example, 130 ℃, 140 ℃, 150 ℃. Curing within the process temperature range to ensure that the internal crosslinking reaction of the plastic packaging material in the plastic packaging area I is gradually completed and the number of reaction groups and reaction active points in the molecules is gradually reduced, so that the plastic packaging layer 12 with a stable three-dimensional net structure is formed, the plastic packaging layer 12 has high strength and high hardness, and the plastic packaging layer 12 is ensured to have high bending resistance, moisture resistance and heat resistance; and the internal stress of the molding layer 12 is moderate, so that the adhesion between the molding layer 12 and the chip 20 is strong, and the adhesion between the molding layer 12 and the device wafer 10 is strong.
In this embodiment, before the curing process, the method further includes: and in the process of carrying out selective spraying treatment, heating the plastic packaging material positioned in the plastic packaging area I, wherein the process temperature of the heating treatment is lower than that of the curing treatment.
In the process of heating treatment, the flowability of the plastic packaging material in the plastic packaging area I is improved, which is beneficial to improving the thickness uniformity of the formed plastic packaging layer 12; moreover, solvent molecules which hinder the cross-linking reaction exist in the plastic package material, and the heating treatment is beneficial to volatilizing the solvent from the plastic package material, so that the cross-linking reaction degree in the subsequent curing treatment process is improved, and the strength and the hardness of the formed plastic package layer 12 are improved.
The process temperature of the heating treatment is not suitable to be too low or too high. If the process temperature is too low, the flowability of the plastic packaging material is relatively poor, and the volatilization degree of a solvent which can influence the crosslinking reaction in the plastic packaging material is low; if the process temperature is too high, the plastic package material in the plastic package area I is easily hardened too early, and the plastic package layer 12 is easily layered.
For this reason, in this embodiment, the process temperature of the heat treatment is 20 ℃ to 120 ℃, for example, 40 ℃, 60 ℃, 80 ℃, 100 ℃. The process temperature adopted by the heating treatment is moderate, so that the plastic package material in the plastic package area I is ensured to have proper fluidity, the solvent in the plastic package material is volatilized as much as possible, and meanwhile, the problem of delamination of the plastic package layer 12 caused by overhigh process temperature of the heating treatment can be avoided. The method of the heat treatment may be: the heating treatment is completed by heating the susceptor.
In other embodiments, the curing process may be performed during the selective spraying process.
As shown in fig. 5 and 6, a trench 14 surrounding each of the first chips 13 is formed in the molding layer 12.
The trench 14 is used for filling a conductive material in a subsequent step to form a conductive sidewall, and the conductive sidewall is used for protecting the first chip 13 and reducing interference of an external magnetic field on the first chip 13.
Specifically, the trench 14 is formed around each first chip 13, so that the trench 14 is filled with a shielding material to form a shielding layer around each first chip 13.
The width d of the trench 14 is used to define the thickness of the conductive sidewalls. If the width d of the groove 14 is too large, the thickness of the conductive side wall is too large, and the thickness and the volume of the whole packaging structure are easily increased; if the width d of the trench 14 is small, the thickness of the conductive sidewall is too small, which easily affects the shielding effect of the conductive sidewall, and accordingly, the width d of the trench 14 is within a range of 10 to 50 micrometers.
As shown in fig. 6, the projection of the first chip 13 on the device wafer 10 is generally rectangular. In this embodiment, a projection of the trench 14 in the molding compound layer 12 on the device wafer 10 is rectangular, that is, a shape of the trench 14 matches a shape of the first chip 13, so that the formed shielding structure occupies a small volume and has a good shielding effect on the first chip 13.
The side wall of the trench 14 close to the first chip 13 is an inner side wall, a distance between the inner side wall and the first chip 13 is D (that is, a distance between the first chip 13 and the opposite side surface of the inner side wall and the inner side surface), the distance D is used for defining a distance between the first chip 13 and a subsequently formed conductive side wall, and the distance D is also used for defining a thickness of a molding layer between the first chip 13 and the conductive side wall.
If the distance D is too large, the distance between the trench 14 and the other chips 20 adjacent to the first chip 13 is short, which easily affects the performance of the other chips, and the shielding effect on the first chip 13 is reduced due to the large distance between the conductive sidewall and the first chip 13; if the distance D is too small, the thickness of the molding compound layer between the conductive sidewall and the first chip 13 is small, so that the insulation effect between the conductive sidewall and the first chip 13 is easily affected. Therefore, the distance D between the inner side wall and the opposite side wall of the first chip 13 is in the range of 5-100 micrometers.
As shown in fig. 5, the wafer level system packaging method of the present embodiment includes: a trench 14 exposing the device wafer 10 is formed in the molding compound layer 12, so that the conductive sidewall formed in the trench 14 can contact the device wafer 10, and the conductive sidewall can shield the first chip 13 to a large extent.
In this embodiment, a mask pattern exposing the trench 14 region is formed on the molding compound layer 12 and the first chip 13, and the molding compound layer 12 is etched by using the mask pattern to form the trench 14.
Specifically, the molding layer 12 may be etched by a laser etching process to form the trench 14. The laser etching process has high precision, and the forming position of the groove 14 and the size of the groove 14 can be determined more accurately.
And in the step of etching the plastic package layer 12, the device wafer 10 is used as an etching stop layer, and the etching is stopped when the groove 14 exposes the device wafer 10.
It should be noted that, in other embodiments, the molding layer 12 is etched, so that the bottom of the formed trench 14 is located in the molding layer 12, that is, the trench 14 does not penetrate through the molding layer 12, that is, the trench 14 does not expose the device wafer 10, but a certain thickness of molding layer material is present between the device wafer 10 and the trench 14. When the trench 14 is filled with a conductive material, the formed conductive sidewall does not contact the device wafer 10, but extends with a certain thickness in a direction perpendicular to the device wafer 10, so that the conductive sidewall can still serve as a shield for the first chip 13.
With combined reference to fig. 7 and 10, a conductive material is formed in the trench 14 (as shown in fig. 5 and 6) and over the first chip 13; the conductive material in the trench 14 is a conductive sidewall 151; the conductive material above the first chip 13 is a conductive layer 152 for forming a shielding shell 15 with the conductive sidewall 151.
As shown in fig. 7, a conductive material is filled into the trench 14 to form a conductive sidewall 151. The conductive sidewall 151 is used to reduce interference of an external magnetic field on the first chip 13, thereby improving the performance stability and reliability of the integrated circuit.
The conductive sidewall 151 is used for shielding from the side of the first chip 13, and forms a shielding shell with a conductive layer formed later. In this embodiment, the shielding case is an electrostatic shielding structure, and is configured to terminate an external electric field on a surface of the shielding case and transmit charges to a ground. Accordingly, the package structure formed in this embodiment connects the shielding shell to the ground terminal during use.
It should be noted that, in other embodiments, the shielding shell may also be an electromagnetic shielding structure, and is configured to reduce the influence of the high-frequency electromagnetic field, so that the interference field forms an eddy current in the shielding shell, thereby weakening the field strength of the interference field at the integrated circuit position, and achieving the shielding effect.
In this embodiment, in order to achieve the shielding effect, the conductive material may be metal, for example: the conductive sidewall 151 is made of one or more metals such as silver, copper, tin, aluminum, zinc, tungsten, and the like. In other embodiments, the conductive material may be an alloy, such as: the conductive material is an alloy such as stainless steel.
In practice, the conductive sidewalls 151 are formed by an electroplating process. The conductive sidewalls 151 may be formed by physical vapor deposition or sputtering in other embodiments.
In this embodiment, the conductive sidewall 151 is formed by a conductive material filled in the trench 14, so that the thickness of the conductive sidewall 151 is the same as the width of the trench 14 (as shown in fig. 6), and the distance between the conductive sidewall 151 and the first chip 13 is the same as the distance between the trench 14 (as shown in fig. 6) and the first chip 13. Accordingly, the thickness h of the conductive sidewall 151 is in the range of 10 to 50 micrometers. The distance H between the inner side wall of the conductive side wall 151 and the first chip 13 is within the range of 5-100 micrometers.
As shown in fig. 8, a conductive material is formed over the first chips 13, wherein the conductive material over each of the first chips 13 is a conductive layer 152 for forming a shielding shell 15 with the conductive sidewalls 151.
The conductive layer 152 is connected to the conductive sidewall 151, forming a closed shielding shell over the first chip 13. The molding compound layer 12 located between the first chip 13 and the conductive layer 152 functions as an insulation layer, so as to prevent the shielding shell 15 from affecting the normal operation of the first chip 13.
In this embodiment, the molding compound layer 12 covers the sidewall of the first chip 13 or the molding compound layer 12 covers a part of the sidewall of the first chip 13, exposing the top surface of the first chip 13, and correspondingly, a part of the bottom of the conductive layer 152 is located on the first chip 12 and connected to the conductive sidewall.
It should be noted that if the thickness P of the conductive material above the first chip 13 is too large, the volume and thickness of the shielding shell are easily increased; if the thickness P of the conductive material above the first chip 13 is too small, the shielding effect of the shielding shell 15 is affected, and optionally, the thickness P of the conductive material above the first chip 13 is in the range of 5 to 50 micrometers.
It should be noted that, the shielding case of the present embodiment is an electrostatic shielding structure, and the conductive layer 152 on the plastic package layer 12 is also used as a ground terminal of the shielding case, and is connected to the ground terminal in the use process of the subsequent package structure.
The wafer level system packaging method of the embodiment further comprises the following steps: after the conductive layer 152 is formed, wafer thinning is performed through the wafer backside 102 of the device wafer 10; and forming a through-silicon via interconnection structure in the thinned device wafer 10, which will not be described in detail herein.
In the wafer level system packaging method of the present embodiment, the influence of the external magnetic field on the first chip 13 is reduced by locally shielding the first chip 13, and the wafer level system packaging method of the present embodiment selectively shields the first chip 13, so that the thickness and the volume of the shielding shell are reduced.
Referring to fig. 9 and 10, a schematic diagram of another embodiment of the wafer level system packaging method of the present invention is further illustrated. The same points of the wafer level system packaging method of the present embodiment and the previous embodiment are not repeated, and the wafer level system packaging method of the present embodiment is different from the previous embodiment in that the packaging method of the present embodiment further includes:
after the molding layer 32 is covered with the conductive material 350, a portion of the conductive material 350 is removed and the conductive material 350 above each first chip 33 is remained, and the remained conductive material 350 is a conductive layer 352.
In this embodiment, the conductive material of the first chip 33 that is not used for forming the shielding shell is removed, so that the problem of coupling capacitance caused by the redundant conductive material is reduced, and the performance of the package structure is optimized.
As shown in fig. 9, a surface of the conductive sidewall 351 facing away from the first chip 33 is an outer side 353; the step of removing a portion of the conductive material 350 to leave the conductive material 350 over the first chip 33 includes:
a masking layer 36 is formed on the conductive material 350 above the first chip 33, the masking layer 36 masks the conductive layer above the first chip 33, and the sidewall of the masking layer 36 is aligned with the outer side 353.
It should be noted that, the side wall of the mask layer 36 is aligned with the outer side 353, so that in the step of removing a part of the conductive material, the conductive material 350 on the first chip 33 and in contact with the conductive side wall 351 can be remained as much as possible while removing the excess conductive material 350, thereby improving the shielding effect of the shielding shell.
Specifically, the mask layer 36 is photoresist.
As shown in fig. 10, using the mask layer 36 (shown in fig. 9) as a mask, a portion of the conductive material 350 is removed, and the conductive material 350 above the first chip 33 remains, and the remaining conductive material 350 is a conductive layer 352 for forming the shielding shell 35 with the conductive sidewall 351.
Specifically, the conductive material 350 is a metal, and the excess conductive material can be removed by a dry etching process. For example: the conductive material 350 is aluminum, and a portion of the conductive material 350 may be removed by a dry etching process using chlorine gas as an etching gas.
The embodiment reduces the problem of coupling capacitance and avoids affecting other chips 20 by removing excessive conductive material 350 while ensuring that the first chip 33 is locally shielded.
For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A wafer level system packaging method, comprising:
forming a bonding structure, the bonding structure comprising: the device comprises a device wafer and a plurality of chips bonded to the device wafer, wherein the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; a plastic packaging area is enclosed between the adjacent chips and the device wafer;
carrying out selective spraying treatment, spraying a plastic packaging material to the plastic packaging area, and carrying out curing treatment on the plastic packaging material to form a plastic packaging layer covering the device wafer and the side wall of the chip;
forming a groove surrounding each first chip in the plastic packaging layer;
forming a conductive material in the trench and over the first chip; the conductive material in the groove is a conductive side wall, and the conductive material above the first chip is a conductive layer and is used for being connected with the conductive side wall to form a shielding shell.
2. The encapsulation method of claim 1, wherein the selective spray coating process comprises:
providing a movable spray head;
and moving the spray head above the device wafer, and spraying plastic package materials to the plastic package area by the spray head when the spray head moves to pass above the plastic package area.
3. The packaging method according to claim 2, wherein the nozzle moves at least twice over the same molding region to form the molding layer; and the moving path of the sprayer when the sprayer moves above the plastic package area for the previous time is provided with a first direction, the moving path of the sprayer when the sprayer moves above the same plastic package area for the next time is provided with a second direction, and the second direction is different from the first direction.
4. The packaging method according to claim 2 or 3, wherein the chips are distributed on the device wafer in an array along the X direction and the Y direction, and a plurality of rows of plastic package regions and a plurality of columns of plastic package regions are defined between the chips distributed in the array and the device wafer; the moving path of the spray head has a direction including: one or more of + X direction, -X direction, + Y direction, or-Y direction.
5. The encapsulation method of claim 4, wherein the path of travel of the spray head has a direction further comprising: an oblique direction at 45 degrees to the X direction or an oblique direction at 45 degrees to the Y direction.
6. The packaging method according to claim 2, wherein before the selective spray coating process, position information of a mold sealing area on the device wafer is acquired; and performing the selective spraying treatment based on the acquired position information.
7. The packaging method according to claim 6, wherein the method of acquiring the position information of the plastic package region comprises: placing the chip on the device wafer based on preset position information, and taking the preset position information as position information of a plastic package area on the device wafer; or after the chip is arranged on the device wafer, the surface of the device wafer is irradiated by light, and the position information of the plastic package area is obtained by collecting the light information reflected by the surface of the device wafer.
8. The encapsulation method according to claim 6, wherein the method of performing the selective spray coating process based on the acquired position information includes: the method comprises the steps that when a nozzle moves above a device wafer, the real-time position of the nozzle on the device wafer is obtained in real time; and controlling the spray head to spray plastic package material to the plastic package area in the process of moving on the device wafer based on the real-time position and the acquired position information.
9. The encapsulation method according to claim 2, wherein in the selective spray coating process, a vertical distance between the nozzle and the device wafer is 5mm to 30mm, a moving speed of the nozzle is 0.01m/s to 0.1m/s, and a flow rate of the nozzle spraying the molding compound is 1ml/s to 10 ml/s.
10. The encapsulation method of claim 1, wherein the selective spray coating process comprises:
providing a nozzle and a movable carrying platform;
and placing the device wafer on the movable carrying platform, enabling the device wafer to move below a spray head, and spraying a plastic packaging material to the plastic packaging area by the spray head when the plastic packaging area moves to the position below the spray head.
11. The encapsulation method according to claim 1, wherein the curing process is performed after the selective spray coating process is finished.
12. The packaging method according to claim 11, further comprising, before the curing, heating the molding compound in the molding zone during the selective spraying, wherein a process temperature of the heating is lower than a process temperature of the curing.
13. The packaging method according to claim 12, wherein the process temperature of the heating treatment is in a range of 20 ℃ to 120 ℃; the process temperature range of the curing treatment is 120-160 ℃.
14. The packaging method of claim 1, wherein the step of forming a conductive material in the trench and over the first chip comprises:
forming a conductive material covering the plastic packaging layer and the chip;
removing a portion of the conductive material and retaining the conductive material over each first chip, the retained conductive material being the conductive layer.
15. The packaging method according to claim 14, wherein a surface of the conductive sidewall facing away from the first chip is an outer side surface; the step of removing a portion of the conductive material and leaving the conductive material over the first chip includes:
forming a mask layer on the conductive material above the first chip, wherein the mask layer shields the conductive layer above the first chip, and the side wall of the mask layer is aligned with the outer side face;
and removing the conductive material exposed by the mask layer.
16. The packaging method of claim 1, wherein the trench is formed by an etching process.
17. The packaging method of claim 1, wherein the conductive material is a metal, the metal being formed by an electroplating process.
18. The packaging method of claim 1, wherein the trench exposes the device wafer, or wherein a bottom of the trench is in the molding layer.
CN201811608042.8A 2018-12-26 2018-12-26 Wafer level system packaging method Active CN111370335B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811608042.8A CN111370335B (en) 2018-12-26 2018-12-26 Wafer level system packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811608042.8A CN111370335B (en) 2018-12-26 2018-12-26 Wafer level system packaging method

Publications (2)

Publication Number Publication Date
CN111370335A true CN111370335A (en) 2020-07-03
CN111370335B CN111370335B (en) 2022-03-15

Family

ID=71207871

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811608042.8A Active CN111370335B (en) 2018-12-26 2018-12-26 Wafer level system packaging method

Country Status (1)

Country Link
CN (1) CN111370335B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112897451A (en) * 2021-01-19 2021-06-04 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment
CN116705771A (en) * 2022-12-30 2023-09-05 成都电科星拓科技有限公司 Plastic package reliability heat dissipation enhanced electromagnetic shielding structure and packaging method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150024547A1 (en) * 2011-09-30 2015-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. EMI Package and Method for Making Same
CN105304509A (en) * 2014-06-08 2016-02-03 联测总部私人有限公司 Semiconductor packages and methods of packaging semiconductor devices
CN107104094A (en) * 2016-02-22 2017-08-29 矽品精密工业股份有限公司 Package structure and method for fabricating the same
CN107275241A (en) * 2013-02-27 2017-10-20 日月光半导体制造股份有限公司 Semiconductor packages and correlation technique with thermal-enhanced conformal shielding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150024547A1 (en) * 2011-09-30 2015-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. EMI Package and Method for Making Same
CN107275241A (en) * 2013-02-27 2017-10-20 日月光半导体制造股份有限公司 Semiconductor packages and correlation technique with thermal-enhanced conformal shielding
CN105304509A (en) * 2014-06-08 2016-02-03 联测总部私人有限公司 Semiconductor packages and methods of packaging semiconductor devices
CN107104094A (en) * 2016-02-22 2017-08-29 矽品精密工业股份有限公司 Package structure and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112897451A (en) * 2021-01-19 2021-06-04 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment
CN112897451B (en) * 2021-01-19 2023-12-22 潍坊歌尔微电子有限公司 Sensor packaging structure, manufacturing method thereof and electronic equipment
CN116705771A (en) * 2022-12-30 2023-09-05 成都电科星拓科技有限公司 Plastic package reliability heat dissipation enhanced electromagnetic shielding structure and packaging method thereof

Also Published As

Publication number Publication date
CN111370335B (en) 2022-03-15

Similar Documents

Publication Publication Date Title
US10217702B2 (en) Semiconductor device and method of forming an embedded SoP fan-out package
KR102258874B1 (en) semiconductor device with PARTIAL EMI SHIELDING removal using laser ablation
EP3428965A1 (en) Semiconductor package including emi shielding structure and method for forming the same
US20190067205A1 (en) Thermal and electromagnetic interference shielding for die embedded in package substrate
US20180134546A1 (en) Semiconductor device and manufacturing method thereof
KR102490537B1 (en) Semiconductor package and fabricating method thereof
KR20190053235A (en) Wafer level package and method
CN111370335B (en) Wafer level system packaging method
US20220059470A1 (en) Semiconductor package including an electromagnetic shield and method of fabricating the same
CN109887890B (en) Fan-out type inverted packaging structure and preparation method thereof
CN111370329A (en) Fan-out type wafer level packaging method
US10910286B2 (en) Wafer-level system-in-package packaging method and package structure thereof
CN111370431B (en) Packaging method of photoelectric sensing integrated system
CN111370328A (en) Wafer level packaging method
CN111370327B (en) Fan-in wafer level packaging method
CN111370334B (en) 3D packaging method
CN110875281B (en) Wafer level system packaging method and packaging structure
CN111371970B (en) Packaging method of camera shooting assembly
CN111370320B (en) Packaging method
CN111370333B (en) Wafer level system packaging method
CN111370324B (en) Packaging method
CN111370338B (en) Packaging method
CN111370326B (en) Packaging method
CN111370325B (en) System-in-package method and spraying device
CN111370330A (en) Wafer level packaging method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant