CN111369952A - GIP circuit and display panel - Google Patents

Abstract

The invention discloses a GIP circuit and a display panel, wherein the GIP circuit comprises: the multi-stage GIP unit, the driving IC, the synchronous signal line, the TFT switch and the TFT switch line; the method comprises the steps that multiple stages of GIP units are cascaded, and the multiple stages of GIP units are divided into multiple sections of GIP units; each section of GIP unit comprises a starting GIP unit, and the starting GIP unit controls the section of GIP unit through a cascade connection wire; each initial GIP unit is connected with a TFT switch, the output ends of all the TFT switches are connected with the GIP unit, the input ends of all the TFT switches are connected with the driving IC through the same synchronous signal line, and the control ends of all the TFT switches are connected with the driving IC through the same TFT switch line. According to the technical scheme, when the display panel displays a static picture or two frames of pictures are similar, the power consumption of the display panel can be reduced to a certain extent, GIP actions are reduced, and the energy-saving characteristic is achieved.

Description

GIP circuit and display panel

Technical Field

The invention relates to the technical field of driving circuits, in particular to a GIP circuit and a display panel.

Background

The GIP driving mode of the panel is step-by-step driving, so that the GIP will work back and forth from the first stage to the last stage during refreshing, and thus, repeated refreshing exists for a pure color picture or two similar pictures, which undoubtedly increases the power consumption of the panel.

Referring to fig. 1, it can be seen that the off-leakage current of the igzo TFT is small compared to the a-Si TFT/LTPS TFT, and the on-current of the igzo TFT is also large compared to the a-Si TFT, so that the transistor size is smaller compared to the conventional a-Si TFT, the aperture ratio of the pixel of the liquid crystal panel can be increased, lower power consumption can be provided, and the purpose of saving power on the screen can be achieved. The design of this scheme is based on IGZO TFTs.

Referring to fig. 2, the GIP technique directly integrates a driving circuit (i.e., GIP circuit) on the display panel to generate multi-level scanning signals for gating the display pixels, and the GIP starts to be driven step by step under the action of the start signal, and so on. The synchronization signal STV and the clock signal CK together determine the order of the output signal Gn, and it can be seen that the output GIP signal is stepped down and GIP is driven in odd and even left and right. Therefore, when the picture is refreshed every frame, the GIP circuit can act once, so that the power consumption of the panel is not large when the picture displays a static picture or a dynamic picture.

Disclosure of Invention

Therefore, it is desirable to provide a GIP circuit and a display panel, which can solve the problem of excessive power consumption of the panel in a pure color picture or two similar pictures.

To achieve the above object, the present invention provides a GIP circuit and a display panel, including: the multi-stage GIP unit, the driving IC, the synchronous signal line, the TFT switch and the TFT switch line;

the method comprises the steps that multiple stages of GIP units are cascaded, and the multiple stages of GIP units are divided into multiple sections of GIP units;

each section of GIP unit comprises a starting GIP unit, and the starting GIP unit controls the section of GIP unit through a cascade connection wire;

each starting GIP unit is connected with a TFT switch, the output ends of all the TFT switches are connected with the GIP units, the input ends of all the TFT switches are connected with a driving IC through the same synchronous signal line, the control ends of all the TFT switches are connected with the driving IC through the same TFT switch line, and the driving IC is used for closing the TFT switch line corresponding to each section of GIP unit when the current data line signal of each section of GIP unit is the same as the last data line signal.

Furthermore, the semiconductor integrated circuit further comprises a clock signal line, each stage of GIP unit is connected with the driving IC through the same clock signal line, and the clock signal line is used for providing a clock signal.

Furthermore, the clock signal line also comprises an inverted clock signal line, and each stage of GIP unit is connected with the driving IC through the same inverted clock signal line.

Further, a GIP unit output line for connecting the GIP unit and the pixel is included.

Further, the driving IC is used for turning on the TFT switch of a section of GIP unit after the section of GIP unit is driven and the off time of the TFT switch of the section of GIP unit is greater than a preset value.

Further, the material of the TFT switch is IGZO.

The inventor provides a GIP circuit display panel, wherein the GIP circuit is the GIP circuit of any one of the embodiments, and further comprises: a plurality of rows of pixels, pixel switches, data lines;

each pixel is connected with the output end of the pixel switch;

each stage of GIP unit is connected with a row of pixels through a GIP unit output line, and the GIP unit output line is connected with the control end of the pixel switch of each pixel in the row where the GIP unit output line is located;

the data line is connected to the input terminal of the pixel switch of each pixel in the row, and the data line is further connected to the driving IC.

Different from the prior art, the technical scheme segments the synchronous signal line, and the multiple segments of synchronous signal lines respectively control the multiple segments of GIP units. And a TFT switch and a switch line are respectively arranged on one synchronous signal line, and after the TFT switch is turned on, the Gout in the area is sequentially output. When the display panel displays a static picture or two frames of pictures are similar, the power consumption of the display panel can be reduced to a certain extent, GIP actions are reduced, and the display panel has the characteristic of energy conservation.

Drawings

FIG. 1 is an I-V curve of the LTPS, a-Si and IGZO TFT in the background art;

FIG. 2 is a schematic diagram of a GIP circuit according to the prior art;

fig. 3 is a schematic structural diagram of the GIP circuit according to the present embodiment;

FIG. 4 is a timing diagram of the GIP circuit of the present embodiment;

FIG. 5 is a schematic diagram of a pixel and a data line according to the present embodiment;

fig. 6 is a logic diagram of the GIP circuit driving method according to the present embodiment.

Description of reference numerals:

1. a GIP unit;

11. a start GIP unit;

2. a TFT switch line;

21. a TFT switch;

3. a driver IC;

4. a pixel;

5. a data line.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 6, the present embodiment provides a GIP circuit, including: a multi-stage GIP unit 1, a driving IC3, a synchronization signal line STV (STV1, STV2 … STVm), a TFT switch 21, and a TFT switch line 2. The multi-stage GIP units 1 are cascaded, and the multi-stage GIP units 1 are divided into a plurality of sections of GIP units. Each section of GIP units includes a start GIP unit 11, and the start GIP unit 11 controls the section of GIP units through a cascade connection. Each start GIP cell 11 is connected with a TFT switch 21, the output terminals of all the TFT switches 21 are connected with the GIP cell 1, the input terminals of all the TFT switches 21 are connected with a driving IC3 through the same synchronization signal line STV, the control terminals of all the TFT switches 21 are connected with a driving IC3 through the same TFT switch line 2, and the driving IC is configured to close the TFT switch line corresponding to each segment of GIP cell when the current data line signal of the segment of GIP cell is the same as the previous data line signal.

In the technical scheme, the synchronous signal STV is added to drive the GIP unit in a segmented mode. The synchronizing signal lines are segmented, and the plurality of segments of synchronizing signal lines control the plurality of stages of GIP units, respectively. It can be seen that the synchronization signal STV is divided into STV1, STV2 … STVm segment control multi-stage GIP cells, and each synchronization signal STV has a TFT as a switch control STV signal. After the TFT switch is turned on, the Gout of the area is sequentially output. When refreshing the picture, firstly comparing whether the data line data signals of all GIP units under the control of the synchronous signal STV are the same as the previous data line data signals, if so, not refreshing the GIP units, and keeping Holding; if not, the section of GIP unit is refreshed, and the timing diagram refers to fig. 4. When the screen displays a static picture or two frames of pictures are similar, the power consumption of the panel can be reduced to a certain degree, the GIP action is reduced, and the energy-saving characteristic is achieved.

Referring to fig. 3, generally, each section of GIP units at least includes a first-level GIP unit 1, and if the section of GIP units is the first-level GIP unit 1, the GIP unit 1 is the initial GIP unit 11; in the case of a multi-stage GIP unit, the first-stage GIP unit 1 is a start GIP unit 11, two adjacent GIP units (in driving order) are connected by a cascade connection, and the start GIP unit 11 also controls the section of GIP unit by the cascade connection. Specifically, the synchronization signal line STV1 is connected to the start GIP cell 11 of the first stage GIP cell, the first stage GIP cell may be a two-stage GIP cell, and the last stage GIP cell is the start GIP cell, as shown in fig. 3, but may be any other number of stages; the synchronization signal line STV2 is connected to the start GIP cell 11 of the second stage GIP cell; the synchronization signal line STVm connects the start GIP units 11 of the mth stage GIP units. Similarly, the number of GIP units in each segment depends on the actual situation.

Referring to fig. 3, in the present embodiment, the GIP units 11 of each stage are connected to the driving IC3 through the same clock signal line, and the clock signal line is used for providing a clock signal. Generally, an inverted clock signal line is further included, and the GIP units 1 of each stage are connected to the driving IC through the same inverted clock signal line. The phase of the inverted clock signal line is opposite to the phase of the clock signal line and is 180 degrees. The clock signal line and the inverted clock signal line can improve the driving capability.

Referring to fig. 5, in the present embodiment, a GIP unit output line (G1, G2 … Gn) and a pixel 4 are further included. The GIP cell output line G may perform a progressive scan of the multi-stage GIP cells. In order to apply the GIP circuit to the display panel, each stage of GIP cells 11 is connected to the pixels through one GIP cell output line G. Specifically, the display panel includes a plurality of pixel 4 array arrangements, pixel switches, and data lines 5(date1, date2 … date). Each pixel 4 is provided with a pixel switch, and each pixel 4 is connected with the output end of the pixel switch. Each stage GIP cell is connected to the control terminal of the pixel switch of each pixel 4 in the row via one GIP cell output line. The data line 5 is connected to the input terminals of the pixel switches of each pixel 4 in the row, and the data line 5 is further connected to a driving IC 3. The display panel connects the pixel switch of each pixel 4 through the output line G of the GIP unit and the data line 5, so that the GIP unit can control the transmission of the data line signal of each pixel.

In this embodiment, the driver IC3 is responsible for driving the panel and controlling the driving current, and can control the structure of the GIP circuit, such as controlling the on/off of the TFT switch or the pixel switch, controlling the transmission of various signals through the synchronization signal line, controlling the transmission of clock signals through the clock signal line, and so on.

Referring to fig. 1, the TFT switches function to control the signal lines to be turned on and off, so the performance of the TFT switches also needs to be considered. Fig. 1 is an I-V curve of LTPS, a-Si, and IGZO TFTs, and it can be seen that compared with an a-Si TFT/LTPS TFT, the TFT made of Indium Gallium Zinc Oxide (IGZO) material has a smaller off-leakage current and a larger on-current, so that compared with the conventional a-Si TFT, the TFT has a smaller transistor size, and can improve the aperture ratio of the pixel of the liquid crystal display panel, provide lower power consumption, and achieve the purpose of saving power on the screen. The design of this scheme is preferably a TFT based on Indium Gallium Zinc Oxide (IGZO) material.

Referring to fig. 6, the GIP circuit driving method according to the present embodiment is as follows: before the output line of the GIP unit scans, the driving IC firstly judges whether the data line signal of the GIP unit is the same as the signal of the previous frame; if the two are the same: the driving IC controls a synchronous signal line and a TFT (thin film transistor) switch line connected with a starting GIP unit of the section of GIP units to be closed, the section of GIP units are kept not to be refreshed, and the Gout signal of the area keeps Holding; if not: the drive IC controls the synchronous signal line and the TFT switch line connected with the initial GIP unit of the section of GIP unit to be opened, and the STV synchronous signal enables the region Gout signal to act step by step to update the region picture.

The driving IC is also used for turning on the TFT switch of the section of the GIP unit after the section of the GIP unit is driven and the turn-off time of the TFT switch of the section of the GIP unit is greater than a preset value. If the GOUT signal of the section of GIP unit is in the Holding state for more than the preset time, the preset time can be 3 frames, 4 frames, 5 frames or even longer, and the driving IC controls the TFT switch line to work at a low frequency.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present patent.

Claims (7)

1. A GIP circuit, comprising: the multi-stage GIP unit, the driving IC, the synchronous signal line, the TFT switch and the TFT switch line;

the method comprises the steps that multiple stages of GIP units are cascaded, and the multiple stages of GIP units are divided into multiple sections of GIP units;

each section of GIP unit comprises a starting GIP unit, and the starting GIP unit controls the section of GIP unit through a cascade connection wire;

each starting GIP unit is connected with a TFT switch, the output ends of all the TFT switches are connected with the GIP units, the input ends of all the TFT switches are connected with a driving IC through the same synchronous signal line, the control ends of all the TFT switches are connected with the driving IC through the same TFT switch line, and the driving IC is used for closing the TFT switch line corresponding to each section of GIP unit when the current data line signal of each section of GIP unit is the same as the last data line signal.

2. The GIP circuit of claim 1, further comprising a clock signal line, wherein each stage of GIP cells is connected to the driving IC through the same clock signal line, and the clock signal line is used for providing a clock signal.

3. The GIP circuit of claim 2, wherein the clock signal lines further comprise inverted clock signal lines, and each stage of GIP cells are connected to the driving IC through the same inverted clock signal line.

4. The GIP circuit according to claim 1, further comprising a GIP cell output line for connecting the GIP cell and the pixel.

5. The GIP circuit of claim 1, wherein the driver IC is configured to turn on the TFT switches of a segment of the GIP cells after the segment of the GIP cells are driven and the turn-off time of the TFT switches of the segment of the GIP cells is greater than a predetermined value.

6. The GIP circuit according to claim 1, wherein said TFT switch is made of IGZO.

7. A GIP circuit display panel, wherein the GIP circuit is a GIP circuit according to any one of claims 1 to 6, further comprising: a plurality of rows of pixels, pixel switches, data lines;

each pixel is connected with the output end of the pixel switch;

each stage of GIP unit is connected with the control end of the pixel switch of each pixel in the row through a GIP unit output line;

the data line is connected to the input terminal of the pixel switch of each pixel in the row, and the data line is further connected to the driving IC.

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