CN115359831A - Shifting register unit and control method thereof, grid drive circuit and display device - Google Patents

Abstract

The application discloses a shift register unit and a control method thereof, a grid drive circuit and a display device, wherein the shift register unit of the embodiment of the application comprises: the input circuit transmits a signal of the second input end to the pull-up node under the control of an input signal of the first input end; the pull-up circuit outputs a clock signal of the clock signal end to the output end under the control of the potential of the pull-up node; the first reset circuit resets a pull-up node through the potential of the first power supply signal terminal under the control of a signal of the first reset terminal; and the second reset circuit resets the pull-up node through the potential of the first power supply signal terminal under the control of a signal of the second reset terminal, wherein the invalid level of the signals accessed by the first reset terminal and the second reset terminal is less than the potential accessed by the first power supply signal terminal. The embodiment provided by the application resets the pull-up node by the electric potential larger than the invalid electric level of the signals of the first reset end and the second reset end, and avoids output leakage jumping.

Description

Shifting register unit and control method thereof, grid drive circuit and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a control method thereof, a gate driving circuit, and a display device.

Background

With the continuous development of the thin film transistor liquid crystal display (TFT-LCD) industry, low-cost, narrow-frame, light and thin products have attracted more attention, and under this background, the Gate Driver on Array (GOA for short) technology of the Array substrate has come into play. The GOA technology is to make the gate driving circuit and the Thin Film Transistor (TFT) array on the array substrate together, and to realize the line-by-line turn-on of the pixels through the cascade relationship of the shift register units, so that the display displays colorful pictures.

In each shift register unit in the GOA circuit, the most basic structure is an input module, a pull-up module and a reset module, the output level of the output end in the circuit is related to a pull-up node, however, at present, a transistor directly related to the pull-up node is usually in a sub-threshold state in an off state, which causes the leakage of the pull-up node, when the leakage is large, the output voltage has obvious jump, and the phenomenon of uneven cross striation is caused on display.

Disclosure of Invention

In order to solve at least one of the above problems, a first aspect of the present application provides a shift register unit comprising:

the input circuit is electrically connected with the first input end, the second input end and the pull-up node and is configured to transmit a signal of the second input end to the pull-up node under the control of an input signal of the first input end;

the pull-up circuit is electrically connected with the pull-up node, the clock signal end and the output end and is configured to output the clock signal of the clock signal end to the output end under the control of the potential of the pull-up node;

the first reset circuit is electrically connected with the pull-up node, the first reset end and the first power signal end and is configured to reset the pull-up node through the potential of the first power signal end under the control of the signal of the first reset end; and

a second reset circuit electrically connected to the pull-up node, the second reset terminal and the first power signal terminal, and configured to reset the pull-up node by a potential of the first power signal terminal under the control of a signal from the second reset terminal,

and the invalid level of the signals accessed by the first reset end and the second reset end is less than the potential of the first power supply signal end.

In some optional embodiments, the shift register unit further comprises:

a first pull-down control circuit configured to transmit a second power signal to the first pull-down node under control of a second power signal at a second power signal terminal;

a first pull-down circuit configured to pull down the first pull-down node by a third power signal of the third power signal terminal under control of a potential of the pull-up node; and

a first noise reduction circuit electrically connected to the pull-up node, the first power signal terminal and the first pull-down node, configured to pull down the pull-up node by a potential of the first power signal terminal under control of the first pull-down node,

and the invalid level of the signal accessed by the third power supply signal end is less than the potential accessed by the first power supply signal end.

In some optional embodiments, the shift register unit further comprises:

a second pull-down control circuit configured to transmit the fourth power signal to the second pull-down node under control of a fourth power signal at a fourth power signal terminal;

a second pull-down circuit configured to pull down a second pull-down node by a third power signal of a third power signal terminal under control of a potential of the pull-up node; and

and the second noise reduction circuit is electrically connected with the pull-up node, the first power supply signal end and the second pull-down node and is configured to pull down the pull-up node through the potential of the first power supply signal end under the control of the second pull-down node.

In some alternative embodiments, the first and second optical elements, among others,

the input circuit includes: a first electrode of the first transistor is electrically connected to the second input end, a second electrode of the first transistor is electrically connected to the pull-up node, and a control electrode of the first transistor is electrically connected to the first input end;

the pull-up circuit includes: the first pole of the second transistor is electrically connected to the clock signal end, the second pole of the second transistor is electrically connected to the output end, the control pole of the second transistor is electrically connected to the pull-up node, the first end of the first capacitor is electrically connected to the pull-up node, and the second end of the first capacitor is connected to the output end;

the first reset circuit includes: a third transistor, a first pole of which is electrically connected to the pull-up node, a second pole of which is electrically connected to the first power signal terminal, and a control electrode of which is electrically connected to the first reset terminal; and

the second reset circuit includes a fourth transistor having a first electrode electrically connected to the pull-up node, a second electrode electrically connected to the first power signal terminal, and a control electrode electrically connected to the second reset terminal.

In some alternative embodiments, the first and second electrodes may be, among other things,

the first pull-up control circuit includes: a fifth transistor and a sixth transistor, a first pole and a control pole of the fifth transistor being electrically connected to the second power supply signal terminal, a second pole being electrically connected to the control pole of the sixth transistor, a first pole of the sixth transistor being electrically connected to the second power supply signal terminal, and a second pole being electrically connected to the first pull-down node;

the first pull-down circuit includes: a seventh transistor and an eighth transistor, wherein a first electrode of the seventh transistor is electrically connected to a second electrode of the fifth transistor, the second electrode is electrically connected to the third power signal terminal, a control electrode is electrically connected to the pull-up node, a first electrode of the eighth transistor is electrically connected to the first pull-down node, the second electrode is electrically connected to the third power signal terminal, and the control electrode is electrically connected to the pull-up node; and

the first noise reduction circuit includes: and a ninth transistor, wherein a first electrode of the ninth transistor is electrically connected to the pull-up node, a second electrode of the ninth transistor is electrically connected to the first power signal terminal, and a control electrode of the ninth transistor is electrically connected to the first pull-down node.

In some alternative embodiments, the first and second electrodes may be, among other things,

the second pull-up control circuit includes: a tenth transistor and an eleventh transistor, a first pole and a control pole of the tenth transistor being electrically connected to the fourth power supply signal terminal, a second pole being electrically connected to a control pole of the eleventh transistor, a first pole of the eleventh transistor being electrically connected to the fourth power supply signal terminal, and a second pole being electrically connected to the second pull-down node;

the second pull-down circuit includes: a twelfth transistor and a thirteenth transistor, a first pole of the twelfth transistor is electrically connected to the second pole of the tenth transistor, the second pole is electrically connected to the third power signal terminal, a control pole is electrically connected to the pull-up node, a first pole of the thirteenth transistor is electrically connected to the second pull-down node, the second pole is electrically connected to the third power signal terminal, and the control pole is electrically connected to the pull-up node; and

the second noise reduction circuit includes: and a fourteenth transistor, a first pole of which is electrically connected to the pull-up node, a second pole of which is electrically connected to the first power signal terminal, and a control electrode of which is electrically connected to the second pull-down node.

In some optional embodiments, the shift register unit further comprises:

the auxiliary pull-up circuit is electrically connected with the clock signal end, the pull-up node and the auxiliary output end and is configured to output a clock signal to the auxiliary output end under the control of the pull-up node;

the third noise reduction circuit is electrically connected with the output end, the first pull-down node, the second pull-down node and the first power signal end, and is configured to pull down the output end through the potential of the first power signal end under the control of the first pull-down node and through the potential of the first power signal end under the control of the second pull-down node; and

and the auxiliary noise reduction circuit is electrically connected with the auxiliary output end, the first pull-down node, the second pull-down node and the third power signal end and is configured to pull down the auxiliary output end through the potential of the third power signal end under the control of the first pull-down node and pull down the auxiliary output end through the potential of the third power signal end under the control of the second pull-down node.

A second aspect of the present application provides a gate drive circuit comprising N cascaded shift register cells as described above, N being a natural number greater than 2, wherein

The shift register unit includes an auxiliary pull-up circuit configured to output a clock signal to the auxiliary output terminal under control of the pull-up node, and an auxiliary noise reduction circuit configured to pull down the auxiliary output terminal by a potential of the third power signal terminal under control of the first pull-down node and pull down the auxiliary output terminal by a potential of the third power signal terminal under control of the second pull-down node,

the first input end of the nth stage shift register unit is electrically connected with the auxiliary output end of the (N-1) th stage shift register unit, the first reset end of the mth stage shift register unit is electrically connected with the auxiliary output end of the (m + 1) th stage shift register unit, N is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N;

the first input end of the 1 st-stage shift register unit is electrically connected with the initial signal end of the grid drive circuit, and the first reset end of the Nth-stage shift register unit is electrically connected with the cut-off signal end of the grid drive circuit.

A third aspect of the present application provides a display device comprising the gate driving circuit as described above.

A fourth aspect of the present application provides a control method using the shift register unit as described above, comprising:

in the first stage, high level signals are provided for the first input end and the second input end, and the input circuit transmits signals accessed by the second input end to a pull-up node so as to pull up the potential of the pull-up node;

in the second stage, the pull-up circuit transmits the clock signal to the output end under the control of the potential of the pull-up node;

in the third stage, the first reset circuit resets the pull-up node and the output end through the potential of the first power supply signal end under the control of the signal of the first reset end.

The beneficial effect of this application is as follows:

aiming at the existing problems at present, a shift register unit and a control method thereof, a grid drive circuit and a display device are formulated, a first reset circuit and a second reset circuit are arranged and are connected to a first power supply signal end, and the invalid level of signals accessed by the first reset end and the second reset end is smaller than the potential of the first power supply signal end, so that the first reset circuit and the second reset circuit are in an invalid stage, the first reset circuit and the second reset circuit cannot generate electric leakage, the reduction time of the output end voltage is prevented from being prolonged, the output voltage has voltage jump, the brightness consistency of a display picture is improved, and the display device has a wide application prospect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 shows a schematic principle diagram of a prior art shift register cell;

FIG. 2 shows a plot of the current-voltage characteristics of transistors in the shift register cell of FIG. 1;

FIG. 3 is a circuit timing diagram of the key port signals in the shift register unit of FIG. 1;

FIG. 4 is a block diagram of a shift register cell according to an embodiment of the present application;

FIG. 5 is a schematic circuit diagram of a shift register cell according to an embodiment of the present application;

FIG. 6 shows a schematic timing diagram of critical port signals in a shift register cell according to an embodiment of the present application;

fig. 7 shows a schematic block diagram of a gate driving circuit according to an embodiment of the present application.

Detailed Description

In order to more clearly illustrate the present application, the present application is further described below in conjunction with the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not intended to limit the scope of the present application.

It is to be noted that, unless otherwise defined, technical or scientific terms used in the present disclosure should have the ordinary meaning as understood by one having ordinary skill in the art to which the present disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiment of the present application, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are turned on.

Before describing embodiments of the present application, a conventional shift register unit in the related art is first explained.

As shown in fig. 1, a circuit diagram of a shift register unit is shown. As can be seen from fig. 1, the shift register unit includes an input module formed by a transistor M1, a pull-up module formed by a transistor M3 and a capacitor C1, a reset module formed by a transistor M2, and a global reset module formed by a transistor M7. In addition, a noise reduction module formed by transistors M10 and M10' is also included in some cases. Wherein, the sources or drains of the transistors M1, M2, M7, M10 and M10' are electrically connected to the pull-up node PU, which is a transistor affecting the output level of the output terminal Gout. Referring to fig. 2, when Vgs of the transistor drops to 0V, the transistor is not completely turned off but in a sub-threshold state, and simulation experiments show that Ids leakage of the transistor in the sub-threshold state is as high as 10 ^-9 A and is an order of magnitude higher than-2V, which is a large magnitude leakage in the driving circuit of the display panel.

Based on the above structural basis, as shown in fig. 1 and fig. 3, the control electrode of the transistor M1 is electrically connected to Out _ C of the upper stage, the first electrode is electrically connected to the output terminal Gout of the upper stage, the control electrode is connected to the low level pulled down by the power supply terminal LVGL in the stage of further raising the pull-up node, the first electrode is connected to the low level pulled down by the power supply terminal VGL, the low level of LVGL is generally less than VGL, for example, LVGL is-10v, VGL is-8V, and Vgs = -2V in the turn-off stage, so that the leakage of the transistor M1 is small in the stage of raising the pull-up node; differently, the first poles of the transistors M2, M7, M10 and M10' are all electrically connected to the pull-up node PU, the control poles are respectively connected to the reset terminal RST _ PU, the global reset terminal T-RST, the first pull-down node PD1 and the second pull-down node PD2, the reset terminal RST _ PU and the global reset terminal T-RST are usually provided by the power supply terminal LVGL, the low-level signals of the first pull-down node PD1 and the second pull-down node PD2 shown in fig. 1 are also provided by the power supply terminal LVGL, the pull-up node PU is pulled down by the power supply terminal LVGL in the lift phase, so that Vgs of the transistors M2, M7, M10 and M10' is 0V and all in the sub-threshold state, as shown in fig. 3, the transistors M2, M7, M10 and M10' are greatly leaked in the pull-up lift phase, the pull-up node PU is significantly powered down, and the voltage drop thereof causes the turn-on capability of the transistor M3, thereby causing the output terminal drop time Tf to become large. Because the gate scanning signals are provided for the pixels in each row by the GOA circuits in a cascade connection mode, the output falling time of the GOA circuits in different rows is different due to the fact that the characteristics of transistors in the GOA circuit units in different rows are slightly different, the leakage current difference is superposed and amplified, the pixel voltage variation of the pixels in different rows under the gray scale pattern is different, and further the pixel voltage difference is expressed, the light and shade difference between different rows is macroscopically expressed, for example, the display cross striations occur, and the display effect is reduced.

Based on at least one of the above problems, referring to fig. 4, an embodiment of the present application provides a shift register unit, including:

an Input circuit 10 electrically connected to the first Input terminal Input1, the second Input terminal Input2, and the pull-up node PU, and configured to transmit a signal of the second Input terminal Input2 to the pull-up node PU under control of an Input signal of the first Input terminal Input1;

a pull-up circuit 20 electrically connected to the pull-up node PU, the clock signal terminal CLK, and the output terminal Gout, and configured to output the clock signal of the clock signal terminal CLK to the output terminal Gout under control of a potential of the pull-up node PU;

a first reset circuit 30 electrically connected to the pull-up node PU, the first reset terminal RST _ PU, and the first power signal terminal VGL, and configured to reset the pull-up node PU by a potential of the first power signal terminal VGL under the signal control of the first reset terminal RST _ PU; and

a second reset circuit 40 electrically connected to the pull-up node PU, the second reset terminal T-RST and the first power signal terminal VGL, configured to reset the pull-up node PU by a potential of the first power signal terminal VGL under the control of a signal of the second reset terminal T-RST,

the inactive level of the signals accessed by the first reset terminal RST _ PU and the second reset terminal T-RST is less than the potential of the first power supply signal terminal VGL.

In this embodiment, by providing the first reset circuit and the second reset circuit, both of which are connected to the first power signal terminal, and the invalid levels of the signals accessed by the first reset terminal and the second reset terminal are smaller than the potential of the first power signal terminal, the first reset circuit and the second reset circuit do not generate electric leakage in the invalid stage, so that the voltage drop time of the output terminal is prevented from being prolonged, the voltage jump of the output voltage is prevented, and the brightness uniformity of the display image is improved.

In order to explain the structural and functional advantages of the shift register unit in the embodiments of the present application in detail, the following description is made in detail with reference to specific circuit structures with specific examples. It should be specifically noted here that the embodiments of the present application are not limited to the circuit structure of the specific shift register unit, which is illustrated below, that is, the input circuit 10 and the pull-up circuit 20 included in the shift register unit of the present application are essentially main structural modules in the shift register unit, and the first reset circuit 30 and the second reset circuit 40 are respectively used for current-stage reset and global reset of the pull-up node PU. That is, although the circuit configuration of 21T1C is described in detail as an example in the drawings, the present application is not limited thereto, and other numbers of shift register units, such as 11T1C, 17T2C, etc., which are not illustrated, are also applicable as long as the same inventive concept as above is satisfied.

In a specific example, referring to fig. 4 and 5 in combination, fig. 3 shows a schematic structural block diagram of a shift register unit according to an embodiment of the present application, and fig. 4 shows a circuit schematic diagram of a 21T1C circuit satisfying the structural block diagram shown in fig. 3.

As shown in fig. 4 and 5, the shift register unit includes: an input circuit 10, a pull-up circuit 20, a first reset circuit 30, and a second reset circuit 40.

Specifically, the first reset circuit 30 is electrically connected to the pull-up node PU, the first reset terminal RST _ PU, and the first power signal terminal VGL, and configured to reset the pull-up node PU by a potential of the first power signal terminal VGL under the control of a signal of the first reset terminal RST _ PU; the second reset circuit 40 is electrically connected to the pull-up node PU, the second reset terminal T-RST and the first power signal terminal VGL, is configured to reset the pull-up node PU by a potential of the first power signal terminal VGL under the signal control of the second reset terminal T-RST, and requires an inactive level of signals switched in by the first reset terminal RST _ PU and the second reset terminal T-RST to be less than a potential of the first power signal terminal VGL.

Generally, the first reset terminal RST _ PU and the second reset terminal T-RST are electrically connected to the power signal terminal LVGL (i.e., the third power signal terminal hereinafter) when being switched into the inactive level, and the power signal terminal LVGL is usually at a low level lower than the potential of the first power signal terminal VGL, so that the requirement that the inactive level of the first reset terminal RST _ PU and the second reset terminal T-RST switched-in signal is less than the potential of the first power signal terminal VGL can be satisfied in a conventional connection manner of the current inactive level electrically connected to the power signal terminal LVGL. When the invalid levels of the first reset terminal RST _ PU and the second reset terminal T-RST access signals are the potentials of the power signal terminal LVGL, the first reset circuit 30 and the second reset circuit 40 reset the pull-up node PU through the first power signal terminal VGL having a higher potential, so that the pull-up node PU is prevented from leaking electricity by a large margin, the delay of the drop time of the output terminal Gout is prevented, and the voltage jump of the output terminal Gout is prevented.

It should be particularly noted that, the above inactive level of the first reset terminal RST _ PU and the second reset terminal T-RST access signal is not limited to the potential of the power signal terminal LVGL, but is intended to illustrate that the setting requirement that the inactive level of the first reset terminal RST _ PU and the second reset terminal T-RST is less than the potential of the first power signal terminal VGL in the present application is satisfied without changing the connection manner of the existing first reset terminal RST _ PU and the existing second reset terminal T-RST, so as to achieve the purpose of reducing the output voltage jump without changing more lines. In practical applications, any other connection manner may be adopted as long as the inactive level of the first reset terminal RST _ PU and the second reset terminal T _ RST is less than the potential of the first power signal terminal VGL.

Further specifically, the first reset circuit 30 includes: a third transistor M3, a first pole of the third transistor M3 being electrically connected to the pull-up node PU, a second pole being electrically connected to the first power signal terminal VGL, and a control electrode being electrically connected to the first reset terminal RST _ PU; the second reset circuit 40 includes a fourth transistor M4, a first pole of the fourth transistor M4 is electrically connected to the pull-up node PU, a second pole is electrically connected to the first power signal terminal VGL, and a controller is electrically connected to the second reset terminal T-RST.

Because the invalid level of the signals accessed by the first reset terminal RST _ PU and the second reset terminal T _ RST is less than the potential of the first power signal terminal VGL, it is ensured that Vgs of the third transistor M3 and the fourth transistor M4 is less than 0V in a time period when the pull-up node PU is unnecessarily reset, that is, the third transistor M3 and the fourth transistor M4 are required to be turned off, so that the third transistor M3 and the fourth transistor M4 are not in a sub-threshold region, the leakage current of the third transistor M3 and the fourth transistor M4 is greatly reduced, the leakage influence is greatly reduced, the potential of the pull-up node PU is pulled down, and the jump of the output terminal Gout is avoided.

Preferably, the difference between the inactive levels of the signals switched on by the first reset terminal RST _ PU and the second reset terminal T _ RST and the potential of the first power signal terminal VGL may be set to be-2V, so that referring to the current-voltage characteristic curve of the transistor shown in fig. 2, the leakage current during the off period of the third transistor M3 and the fourth transistor M4 may be reduced to 1/10 of the leakage current in the prior art by setting Vgs to be-2V, so that the value of the possible leakage current can be ignored, the jump of the output voltage can be ignored, and the influence of the jump on the output voltage can be avoided.

Alternatively, for example, the inactive levels of the first reset terminal RST _ PU and the second reset terminal T-RST are-10V, and the potential of the first power signal terminal VGL is-8V, or the first reset terminal RST _ PU and the second reset terminal T-RST are respectively set to have other values, so that the difference between the inactive level of the signal switched in by the first reset terminal RST _ PU and the second reset terminal T-RST and the potential of the first power signal terminal VGL is-2V, the leakage current during the turn-off period of the third transistor M3 and the fourth transistor M4 can be reduced to 1/10 of the leakage current in the prior art. The inactive levels of the first reset terminal RST _ PU and the second reset terminal T-RST may be provided through the power signal terminal LVGL (i.e., a third power signal terminal hereinafter), or may be provided by other signal lines or power signal terminals, which is not limited herein, and for convenience of description, the following embodiment exemplifies that the inactive levels of the signals to which the first reset terminal RST _ PU and the second reset terminal T-RST are connected are provided by the power signal terminal LVGL.

It should be noted that, the present application also does not intend to limit the specific potential difference between the inactive levels of the first reset terminal RST _ PU and the second reset terminal T _ RST and the first power signal terminal VGL, and it can be understood by those skilled in the art that the larger the absolute value of the potential difference (i.e., the more negative the potential difference), the better the effect of eliminating the leakage is.

In further detail, with continued reference to fig. 5, the input circuit 10 includes: the first transistor M1, the first pole of the first transistor M1 is electrically connected to the second Input terminal Input2, the second pole is electrically connected to the pull-up node PU, and the control pole is electrically connected to the first Input terminal Input1.

The pull-up circuit 20 includes: a second transistor M2 and a first capacitor C1, wherein a first electrode of the second transistor M2 is electrically connected to the clock signal terminal CLK, a second electrode is electrically connected to the output terminal Gout, a control electrode is electrically connected to the pull-up node PU, a first end of the first capacitor C1 is electrically connected to the pull-up node PU, and a second end is connected to the output terminal Gout.

Further, as shown with continued reference to fig. 4 and 5, the shift register unit further includes: a first pull-down control circuit 51 and a first pull-down circuit 61.

Wherein, the first pull-down control circuit 51 is configured to transmit the second power signal to the first pull-down node PD1 under the control of the second power signal terminal VDD 1; the first pull-down circuit 61 is configured to pull down the first pull-down node PD1 by the third power supply signal of the third power supply signal terminal LVGL under the control of the potential of the pull-up node PU.

In this case, optionally, the shift register unit further includes: the first noise reduction circuit 71 is electrically connected to the pull-up node PU, the first power signal terminal VGL, and the first pull-down node PD1, and is configured to pull down the pull-up node PU by a potential of the first power signal terminal VGL under the control of the first pull-down node PD1, where an inactive level of a signal accessed by the third power signal terminal LVGL is smaller than a potential accessed by the first power signal terminal VGL.

Through the arrangement, the first power supply signal end VGL with the potential smaller than the invalid level of the third power supply signal end LVGL access signal is used as the power supply signal end of the pull-down pull-up node PU, so that when the first noise reduction circuit is accessed and the noise reduction circuit does not work, the leakage and voltage jump of the pull-up node PU caused by the leakage of the circuit are avoided, and the increase of the drop time and the voltage jump of the output end Gout are avoided.

Those skilled in the art understand that the setting of the inactive level of the access signal of the third power signal terminal LVGL is the same as that in the above embodiment, and preferably, the inactive level of the access signal of the third power signal terminal LVGL may be set to be 2V or more smaller than the potential of the first power signal terminal VGL, which is not described herein again.

Specifically, referring to fig. 5, the first pull-up control circuit 51 includes: a fifth transistor M5 and a sixth transistor M6, a first pole and a control pole of the fifth transistor M5 being electrically connected to the second power signal terminal VDD1, a second pole being electrically connected to a control pole of the sixth transistor M6, a first pole of the sixth transistor M6 being electrically connected to the second power signal terminal VDD1, and a second pole being electrically connected to the first pull-down node PD1.

The first pull-down circuit 61 includes: a seventh transistor M7 and an eighth transistor M8, a first pole of the seventh transistor M7 is electrically connected to the second pole of the fifth transistor M5, the second pole is electrically connected to the third power signal terminal LVGL, the control pole is electrically connected to the pull-up node PU, a first pole of the eighth transistor M8 is electrically connected to the first pull-down node PD1, the second pole is electrically connected to the third power signal terminal LVGL, and the control pole is electrically connected to the pull-up node PU.

The first noise reduction circuit 71 includes: and a ninth transistor M9 having a first electrode electrically connected to the pull-up node PU, a second electrode electrically connected to the first power signal terminal VGL, and a controller electrically connected to the first pull-down node PD1.

Since the invalid level of the signal connected to the control electrode of the ninth transistor M9 is a signal pulling down the first pull-down node PD1, that is, the potential of the third power signal terminal LVGL, which is smaller than the potential of the first power signal terminal VGL, it is ensured that Vgs of the ninth transistor M9 is smaller than 0V in a time period when the pull-up node PU is not necessarily pulled down, that is, in a time period when the ninth transistor M9 needs to be turned off, so that the ninth transistor M9 is not in a sub-threshold region, the leakage current thereof is greatly reduced, the leakage influence is greatly reduced, the potential of the pull-up node PU is pulled down, and the jump of the output terminal Gout is avoided.

It should be noted that, although fig. 5 illustrates an example in which the first pull-down control circuit 51 includes two transistors and the first pull-down circuit 61 includes two transistors, the present application is not limited thereto, and in practical applications, the first pull-down control circuit 51 may include only one transistor and the first pull-down circuit 61 also includes only one transistor, in this case, the first electrode and the control electrode of the transistor of the first pull-down control circuit 51 may still be electrically connected to the second power signal terminal VDD1, but the second electrode thereof may be electrically connected to the first pull-down node PD1, the first electrode of the transistor of the first pull-down circuit 61 may be directly electrically connected to the first pull-down node PD1, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU, and the first pull-down control circuit may also transmit the second power signal to the first pull-down node PD1 under the control of the second power signal of the second power signal terminal lvvdd 1, and the control of the pull-up node 61 is no longer performed on the third pull-down node lvpd 1.

Further alternatively, the shift register unit includes, in addition to the first pull-down control circuit 51 and the second pull-down circuit 61: a second pull-down control circuit 52 configured to transmit the fourth power signal to the second pull-down node PD2 under the control of the fourth power signal terminal VDD 2; the first pull-down circuit 62 is configured to pull down the second pull-down node PD2 by the third power supply signal of the third power supply signal terminal LVGL under the control of the potential of the pull-up node PU.

In this case, optionally, the shift register unit further includes: the second noise reduction circuit 72 is electrically connected to the pull-up node PU, the first power signal terminal VGL and the second pull-down node PD2, and configured to pull down the pull-up node PU by a potential of the first power signal terminal VGL under the control of the second pull-down node PD2, and similarly, an inactive level of a signal received by the third power signal terminal LVGL is smaller than a potential received by the first power signal terminal VGL.

Through the arrangement, the first power supply signal end VGL with the potential larger than the invalid level of the third power supply signal end LVGL access signal is used as the power supply signal end of the pull-down pull-up node PU, so that when the first noise reduction circuit is accessed and the noise reduction circuit does not work, the leakage and voltage jump of the pull-up node PU caused by the leakage of the circuit are avoided, and the reduction time increase and the voltage jump of the output end Gout are avoided.

Those skilled in the art understand that the setting of the inactive level of the access signal of the third power signal terminal LVGL is the same as that in the above embodiment, and preferably, the inactive level of the access signal of the third power signal terminal LVGL may be set to be 2V or more smaller than the potential of the first power signal terminal VGL, which is not described herein again.

Specifically, referring to fig. 5, the second pull-up control circuit 52 includes: a tenth transistor M10 and an eleventh transistor M11, a first pole and a control pole of the tenth transistor M10 being electrically connected to the fourth power signal terminal VDD2, a second pole being electrically connected to a control pole of the eleventh transistor M11, a first pole of the eleventh transistor M11 being electrically connected to the fourth power signal terminal VDD2, and a second pole being electrically connected to the second pull-down node PD2.

The second pull-down circuit 62 includes: a twelfth transistor M12 and a thirteenth transistor M13, wherein a first electrode of the twelfth transistor M12 is electrically connected to the second electrode of the tenth transistor M10, the second electrode is electrically connected to the third power signal terminal LVGL, the control electrode is electrically connected to the pull-up node PU, a first electrode of the thirteenth transistor M13 is electrically connected to the second pull-down node PD2, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU.

The second noise reduction circuit 72 includes: a fourteenth transistor M14, a first pole of the fourteenth transistor M14 is electrically connected to the pull-up node PU, a second pole is electrically connected to the first power signal terminal VGL, and a control electrode is electrically connected to the second pull-down node PD2.

Similarly, since the invalid level of the signal received by the control electrode of the fourteenth transistor M14 is a signal for pulling down the second pull-down node PD2, that is, the potential of the third power signal terminal LVGL, which is smaller than the potential of the first power signal terminal VGL, it is ensured that Vgs of the fourteenth transistor M14 is smaller than 0V in a time period in which the pull-down node PU is not necessary, that is, in a time period in which the fourteenth transistor M14 needs to be turned off, so that the fourteenth transistor M14 is not in a sub-threshold interval, the leakage current thereof is greatly reduced, the leakage influence is greatly reduced, and the potential of the pull-up node PU is pulled down, thereby avoiding the jump of the output terminal Gout.

It should be understood by those skilled in the art that when the shift register unit includes the first pull-down control circuit 51, the first pull-down circuit 61, the second pull-down control circuit 52 and the second pull-down circuit 62, the signals accessed by the second power signal terminal VDD1 and the fourth power signal terminal VDD2 should be complementary in time, that is, a time period when the signal accessed by the first power signal terminal VDD1 is high, a time period when the signal accessed by the fourth power signal terminal VDD2 is low, and a time period when the signal accessed by the second power signal terminal VDD1 is low, and a signal accessed by the fourth power signal terminal VDD2 is high, so that the first pull-down control circuit 51 and the first pull-down circuit 61 alternate with the second pull-down control circuit 52 and the second pull-down circuit 62.

It should be noted that, although fig. 5 shows an example in which the second pull-down control circuit 52 includes two transistors and the second pull-down circuit 62 includes two transistors, the present application is not limited thereto, and in practical applications, the second pull-down control circuit 52 may include only one transistor and the first pull-down circuit 62 also includes only one transistor, in which case, the first electrode and the control electrode of the transistor of the second pull-down control circuit 52 may still be electrically connected to the fourth power signal terminal VDD2, but the second electrode may be electrically connected to the second pull-down node PD2, the first electrode of the transistor of the second pull-down circuit 62 may be directly electrically connected to the second pull-down node PD2, the second electrode is electrically connected to the third power signal terminal LVGL, and the control electrode is electrically connected to the pull-up node PU, and the first pull-down control circuit may also transmit the fourth power signal to the second pull-down node PD1 under the control of the fourth power signal terminal VDD2, and the pull-down potential of the second pull-down circuit 62 is no longer controlled by the third power signal terminal lvpd 2.

As shown with continued reference to fig. 4 and 5, the shift register circuit may further include: an auxiliary pull-up circuit 21, a third noise reduction circuit 73, and an auxiliary noise reduction circuit 74.

The auxiliary pull-up circuit 21 is electrically connected to the clock signal terminal CLK, the pull-up node PU, and the auxiliary output terminal Out _ C, and configured to output the clock signal of the clock signal terminal CLK to the auxiliary output terminal Out _ C under the control of the pull-up node PU. Specifically, the auxiliary pull-up circuit 21 may include a fifteenth transistor M15, a first pole of the fifteenth transistor M15 is electrically connected to the clock signal terminal CLK, a second pole is electrically connected to the auxiliary output terminal Out _ C, and a control pole is electrically connected to the pull-up node PU.

The third noise reduction circuit 73 is electrically connected to the output terminal Gout, the first pull-down node PD1, the second pull-down node PD2, and the first power signal terminal VGL, and is configured to pull down the output terminal Gout through a potential of the first power signal terminal VGL under the control of the first pull-down node PD1 and pull down the output terminal Gout through a potential of the first power signal terminal VGL under the control of the second pull-down node PD2. Specifically, the third noise reduction circuit 73 includes a noise reduction transistor M16 and a noise reduction transistor M16', in which a first pole of the noise reduction transistor M16 is electrically connected to the output terminal Gout, a second pole is electrically connected to the first power supply signal terminal VGL, and a control pole is electrically connected to the first pull-down node PD1; a first pole of the noise reduction transistor M16' is electrically connected to the output terminal Gout, a second pole is electrically connected to the first power supply signal terminal VGL, and a control pole is electrically connected to the second pull-down node PD2.

The auxiliary noise reduction circuit 74 is electrically connected to the auxiliary output terminal Out _ C, the first pull-down node PD1, the second pull-down node PD2, and the third power signal terminal LVGL, and is configured to pull down the auxiliary output terminal Out _ C through a potential of the third power signal terminal LVGL under the control of the first pull-down node PD1, and to pull down the auxiliary output terminal Out _ C through a potential of the third power signal terminal LVGL under the control of the second pull-down node PD2. Specifically, the auxiliary noise reduction circuit 74 includes an auxiliary noise reduction transistor M17 and an auxiliary noise reduction transistor M17', wherein a first pole of the auxiliary noise reduction transistor M17 is electrically connected to the auxiliary output terminal Out _ C, a second pole is electrically connected to the third power signal terminal LVGL, and a control pole is electrically connected to the first pull-down node PD1; a first electrode of the auxiliary noise reduction transistor M17' is electrically connected to the auxiliary output terminal Out _ C, a second electrode is electrically connected to the third power signal terminal LVGL, and a control electrode is electrically connected to the second pull-down node PD2.

In this application, the function of the fifteenth transistor M15 is equivalent to that of the second transistor M2, and in one scanning period, the high level time period of the output signal of the auxiliary output terminal Out _ C is the same as the high level time period of the output signal of the output terminal Gout, but the difference is that when the auxiliary output terminal Out _ C and the output terminal Gout are pulled down by the respective noise reduction units, the level values of the low level signals after being pulled down are different, the low level signal of the auxiliary output terminal Out _ C is the potential of the third power supply signal terminal LVGL, and the low level signal of the output terminal Gout is the potential of the first power supply signal terminal VGL.

In this example, the first Input terminal Input1 is connected to the potential of the auxiliary output terminal Out _ C of the shift register unit of the previous stage, and the second Input terminal Input2 is connected to the potential of the output terminal Gout of the shift register unit of the previous stage, so that the first transistor M1 leakage can be reduced by using the difference between the inactive levels of the auxiliary output terminal Out _ C and the output terminal Gout.

In addition, in the embodiment of the present application, in order to make the transistor in the first reset circuit 30 no longer be in the sub-threshold region for the time period that needs to be turned off, the auxiliary output terminal Out _ C may be used as a cascade port of the first reset terminal RST _ PU of the next stage in the cascade, and the specific function will be described in detail below.

In addition to the above respective block circuits, in order to be able to reduce noise for the first pull-down node PD1 and the second pull-down node PD2, as shown with reference to fig. 5, the shift register unit may further include a fifth noise reduction circuit including a transistor M18 and a transistor M18'. Specifically, the transistor M18 has a first pole electrically connected to the first pull-down node PD1, a second pole electrically connected to the third power signal terminal LVGL, and a control pole electrically connected to the first Input terminal Input1; a first pole of the transistor M18' is electrically connected to the second pull-down node PD2, a second pole is electrically connected to the third power signal terminal LVGL, and a control pole is electrically connected to the first Input terminal Input1.

With the above arrangement, the first pull-down node PD1 and the second pull-down node PD2 can be pulled down by the potential of the third power signal terminal LVGL under the control of the Input signal accessed from the first Input terminal Input1, so as to ensure the normal lifting of the pull-up node PU and the normal output of the output terminal Out.

To further understand the functional advantages of the circuit configuration in the embodiments of the present application, further description is provided below with reference to the timing diagram of the critical port signal shown in fig. 6. For convenience of understanding, the potential of the first power signal terminal VGL is denoted by VGL, the potential of the third power signal terminal LVGL is denoted by LVGL, and the high level signal of the clock signal terminal VLK is denoted by VGH.

Referring to fig. 6, a frame of scan signals of the shift register unit mainly includes three stages.

The first phase corresponds to a time period T1, in which the first Input terminal Inout1 of the Input circuit 10 inputs a high level signal, and the second Input terminal Input2 also inputs a high level signal, the first transistor M1 is turned on, and transmits the high level signal inputted by the second Input terminal Input2 to the pull-up node PU to pull up the potential of the pull-up node PU. During the period of pulling up the pull-up node PU, the potential of the pull-up node PU rises at a rate of charging the first capacitor C1 due to the presence of the first capacitor C1 in the pull-up circuit 20.

In the first stage, since the first reset terminal RST _ PU is at the low level LVGL, the third transistor M3 is completely turned off, and at this time, a signal inputted from the second reset terminal serving as the global reset terminal is also at the low level LVGL, and the fourth transistor M4 is completely turned off. In addition, the fourth noise reduction circuit makes the first pull-down node PD1 and the second pull-down node PD2 in a pull-down state by the low-level signal LVGL of the third power signal terminal LVGL.

The second phase corresponds to a time period T2, in which the pull-up circuit 20 continues to be charged and raised by the first capacitor C1, so that the potential of the pull-up node PU is raised further, the potential of the pull-up node PU is sufficient to turn on the second transistor M2 in the pull-up circuit 20, the pull-up circuit 20 transmits the clock signal of the clock signal terminal CLK to the output terminal Gout under the control of the potential of the pull-up node PU, and the output terminal Gout outputs a high level signal.

At this stage, the first pull-down circuit 61 and/or the pull-down circuit 62 keeps the first pull-down node PD1 and the second pull-down node PD2 in the pull-down state by the low-level signal LVGL of the third power signal terminal LVGL under the control of the pull-up node PU.

In particular, in the present application, in the second stage as the circuit output stage, the second transistor M2, the ninth transistor M9 and the fourteenth transistor M14 should all be in an off state, and in order to ensure that the above three transistors are not in the sub-threshold region in this stage, by making the potential of the inactive level signal connected to the control electrodes of the second transistor M2, the ninth transistor M9 and the fourteenth transistor M14 smaller than the potential of the first power signal connected to the second electrode, the potential of the pull-up node PU is prevented from being pulled low, thereby effectively shortening the off time Tf of the output terminal, avoiding the voltage jump of the output terminal, and improving the display effect.

In the third stage, the first reset terminal RST _ PU is connected to an active level signal, and the pull-up node PU and the output terminal Gout are reset through the potential of the first power signal terminal VGL under the control of the signal of the first reset terminal.

Based on the same inventive concept, a second aspect of the present application provides a gate driving circuit, comprising N cascaded shift register units as described in the above embodiments, where N is a natural number greater than 2, where

The shift register unit includes an auxiliary output circuit configured to output a clock signal to the auxiliary output terminal under control of the pull-up node, and an auxiliary noise reduction circuit configured to pull-down the output terminal through a potential of the third power signal terminal under control of the first pull-down node and through a potential of the third power signal terminal under control of the second pull-down node,

the first input end of the nth stage shift register unit is electrically connected with the auxiliary output end of the (N-1) th stage shift register unit, the first reset end of the mth stage shift register unit is electrically connected with the auxiliary output end of the (m + 1) th stage shift register unit, N is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N;

the first input end of the 1 st stage shift register unit is electrically connected with the initial signal end of the grid drive circuit, and the first reset end of the Nth stage shift register unit is electrically connected with the cut-off signal end of the grid drive circuit.

Specifically, referring to fig. 7, an exemplary gate driving circuit having four shift register units GOA-1, GOA-2, GOA-3, and GOA-4 cascaded is shown. It can be seen that the auxiliary output terminal Out _ C of the level 1 shift register unit GOA-1 is electrically connected to the first Input terminal Input1 of the level 2 shift register unit GOA-2, and the output terminal Gout of the level 1 is electrically connected to the second Input terminal Input2 of the level 2 shift register unit GOA-2; an auxiliary output end Out _ C of the 2 nd-stage shift register unit GOA-2 is electrically connected to a first Input end Input1 of the 3 rd-stage shift register unit GOA-3, an output end Gout of the 2 nd stage is electrically connected to a second Input end Input2 of the 3 rd-stage shift register unit GOA-3, and an auxiliary output end Out _ C of the 2 nd stage is simultaneously electrically connected to a first reset end RST _ PU of the 1 st-stage shift register unit GOA-1; an auxiliary output terminal Out _ C of the 3 rd stage shift register unit GOA-3 is electrically connected to a first Input terminal Input1 of the 4 th stage shift register unit GOA-4, an output terminal Gout of the 3 rd stage is electrically connected to a second Input terminal Input2 of the 4 th stage shift register unit GOA-4, and an auxiliary output terminal Out _ C of the 3 rd stage is simultaneously electrically connected to a first reset terminal RST _ PU of the 2 nd stage shift register unit GOA-2. The first and second Input terminals Input1 and Input2 of the 1 st stage may be electrically connected to the start signal terminal STV at the same time, and the first reset terminal of the 4 th stage is electrically connected to the off signal terminal (not shown).

In this application, because the second pole of the transistor in the first reset circuit is electrically connected to the first power signal terminal VGL, the connection structure of the circuit is simplified and the voltage jump of the output terminal can be avoided by using the characteristic that the invalid level signal of the auxiliary output terminal is smaller than the potential of the first power signal terminal VGL in the cascade connection and by using the auxiliary output terminal as the cascade connection terminal of the first reset terminal, in addition, the gate driving circuit has the advantages of short drop time and reduced voltage jump of the output terminal of the shift register in the above embodiments through the shift register unit including the cascade connection in the above embodiments, and further description is omitted.

In addition, the number of cascades is only illustrative and is not intended to be limiting, and an appropriate number of cascades may be set according to actual needs, and the number of clock signal lines is also only illustrative and may be adjusted according to specific needs in actual applications.

A third aspect of the present application provides a display device including the gate driver circuit of the embodiment of the present application.

In this embodiment, the gate driving circuit of the display device is formed by cascaded shift register units, and in each shift register unit, the invalid level of the signal accessed by the first reset terminal and the second reset terminal is smaller than the potential of the first power signal terminal, so that in the stage of invalidating the first reset circuit and the second reset circuit, the first reset circuit and the second reset circuit do not generate electric leakage, the voltage drop time of the output terminal is prevented from being prolonged, the voltage jump of the output voltage is avoided, the brightness consistency of the display picture is improved, and the display device has a wide application prospect.

It should be noted that the gate driving circuit according to the embodiments of the present application can be applied to various display devices, and those skilled in the art should understand that any display device based on the operation mode of the gate driving circuit of the present application is within the scope of the present application.

A fourth aspect of the present application provides a control method using a shift register unit of an embodiment of the present application, including:

in a first stage, high-level signals are provided to the first input end and the second input end as input signals, and the input circuit transmits signals accessed by the second input end to the pull-up node to pull up the potential of the pull-up node;

in a second stage, the pull-up circuit transmits the clock signal to an output terminal under the control of the potential of the pull-up node;

in a third stage, the first reset circuit resets the pull-up node and the output terminal through the potential of the first power signal terminal under the control of the signal of the first reset terminal.

In the above mode, the invalid level of the signal accessed by the first reset terminal and the second reset terminal is smaller than the potential of the first power supply signal terminal, so that in the stage that the first reset circuit and the second reset circuit are invalid, the first reset circuit and the second reset circuit cannot generate electric leakage, the reduction time of the output end voltage is prevented from being prolonged, the voltage jump of the output voltage is avoided, and the brightness consistency of the display picture is improved. The specific implementation manner of this embodiment is the same as that of the previous embodiment, and is not described herein again.

Aiming at the existing problems, the shift register unit, the control method thereof, the grid drive circuit and the display device are formulated, and the first reset circuit and the second reset circuit are arranged and are connected to the first power supply signal end, and the invalid level of the signals accessed by the first reset end and the second reset end is smaller than the potential of the first power supply signal end, so that the first reset circuit and the second reset circuit are in the invalid stage, the first reset circuit and the second reset circuit cannot generate electric leakage, the voltage drop time of the output end is prevented from being prolonged, the voltage jump of the output voltage exists, the brightness consistency of a display picture is improved, and the shift register unit has a wide application prospect.

It should be understood that the above-mentioned examples are given for the purpose of illustrating the present application clearly and not for the purpose of limiting the same, and that various other modifications and variations of the present invention may be made by those skilled in the art in light of the above teachings, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed.

Claims (10)

1. A shift register cell, comprising:

an input circuit electrically connected to a first input terminal, a second input terminal and a pull-up node, and configured to transmit a signal of the second input terminal to the pull-up node under control of an input signal of the first input terminal;

a pull-up circuit electrically connected to the pull-up node, a clock signal terminal and an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under control of a potential of the pull-up node;

the first reset circuit is electrically connected with the pull-up node, a first reset end and a first power signal end and is configured to reset the pull-up node through the potential of the first power signal end under the control of a signal of the first reset end; and

a second reset circuit electrically connected to the pull-up node, a second reset terminal and the first power signal terminal, and configured to reset the pull-up node by a potential of the first power signal terminal under the control of a signal of the second reset terminal,

and the invalid level of the signals accessed by the first reset terminal and the second reset terminal is less than the potential of the first power supply signal terminal.

2. The shift register cell of claim 1, further comprising:

a first pull-down control circuit configured to transmit a second power signal to a first pull-down node under control of the second power signal at the second power signal terminal;

a first pull-down circuit configured to pull down the first pull-down node by a third power supply signal of a third power supply signal terminal under control of a potential of the pull-up node; and

a first noise reduction circuit electrically connected to the pull-up node, the first power signal terminal, and the first pull-down node, configured to pull down the pull-up node by a potential of the first power signal terminal under control of the first pull-down node,

and the invalid level of the signal accessed by the third power supply signal end is less than the potential accessed by the first power supply signal end.

3. The shift register cell of claim 2, further comprising:

a second pull-down control circuit configured to transmit a fourth power signal to a second pull-down node under control of the fourth power signal at a fourth power signal terminal;

a second pull-down circuit configured to pull down the second pull-down node by a third power supply signal of the third power supply signal terminal under control of a potential of the pull-up node; and

and the second noise reduction circuit is electrically connected with the pull-up node, the first power supply signal end and the second pull-down node and is configured to pull down the pull-up node through the potential of the first power supply signal end under the control of the second pull-down node.

4. The shift register cell of claim 1, wherein,

the input circuit includes: a first transistor having a first pole electrically connected to the second input terminal, a second pole electrically connected to the pull-up node, and a control pole electrically connected to the first input terminal;

the pull-up circuit includes: a second transistor having a first terminal electrically connected to the clock signal terminal, a second terminal electrically connected to the output terminal, a control terminal electrically connected to the pull-up node, and a first capacitor having a first terminal electrically connected to the pull-up node and a second terminal electrically connected to the output terminal;

the first reset circuit includes: a third transistor having a first electrode electrically connected to the pull-up node, a second electrode electrically connected to the first power signal terminal, and a control electrode electrically connected to a first reset terminal; and

the second reset circuit includes a fourth transistor, a first pole of the fourth transistor is electrically connected to the pull-up node, a second pole of the fourth transistor is electrically connected to the first power signal terminal, and a control pole of the fourth transistor is electrically connected to the second reset terminal.

5. The shift register cell of claim 2, wherein,

the first pull-down control circuit includes: a fifth transistor and a sixth transistor, a first pole and a control pole of the fifth transistor being electrically connected to the second power supply signal terminal, a second pole being electrically connected to the control pole of the sixth transistor, a first pole of the sixth transistor being electrically connected to the second power supply signal terminal, a second pole being electrically connected to the first pull-down node;

the first pull-down circuit includes: a seventh transistor and an eighth transistor, a first pole of the seventh transistor being electrically connected to the second pole of the fifth transistor, a second pole of the seventh transistor being electrically connected to the third power supply signal terminal, a control pole of the seventh transistor being electrically connected to the pull-up node, a first pole of the eighth transistor being electrically connected to the first pull-down node, a second pole of the eighth transistor being electrically connected to the third power supply signal terminal, and a control pole of the eighth transistor being electrically connected to the pull-up node; and

the first noise reduction circuit includes: a ninth transistor, a first pole of which is electrically connected to the pull-up node, a second pole of which is electrically connected to the first power signal terminal, and a control pole of which is electrically connected to the first pull-down node.

6. The shift register cell of claim 3, wherein,

the second pull-down control circuit includes: a tenth transistor and an eleventh transistor, a first pole and a control pole of the tenth transistor being electrically connected to the fourth power supply signal terminal, a second pole being electrically connected to the control pole of the eleventh transistor, a first pole of the eleventh transistor being electrically connected to the fourth power supply signal terminal, and a second pole being electrically connected to the second pull-down node;

the second pull-down circuit includes: a twelfth transistor and a thirteenth transistor, a first pole of the twelfth transistor being electrically connected to the second pole of the tenth transistor, a second pole of the twelfth transistor being electrically connected to the third power supply signal terminal, a control pole of the thirteenth transistor being electrically connected to the pull-up node, a first pole of the thirteenth transistor being electrically connected to the second pull-down node, a second pole of the thirteenth transistor being electrically connected to the third power supply signal terminal, and a control pole of the thirteenth transistor being electrically connected to the pull-up node; and

the second noise reduction circuit includes: a fourteenth transistor, a first pole of which is electrically connected to the pull-up node, a second pole of which is electrically connected to the first power signal terminal, and a control pole of which is electrically connected to the second pull-down node.

7. The shift register cell of claim 3, further comprising:

an auxiliary pull-up circuit electrically connected to the clock signal terminal, the pull-up node and an auxiliary output terminal, and configured to output the clock signal to the auxiliary output terminal under control of the pull-up node;

a third noise reduction circuit electrically connected to the output terminal, the first pull-down node, the second pull-down node, and the first power signal terminal, and configured to pull down the output terminal by a potential of the first power signal terminal under control of the first pull-down node and pull down the output terminal by a potential of the first power signal terminal under control of the second pull-down node; and

and the auxiliary noise reduction circuit is electrically connected with the auxiliary output end, the first pull-down node, the second pull-down node and the third power signal end and is configured to pull down the auxiliary output end through the potential of the third power signal end under the control of the first pull-down node and pull down the auxiliary output end through the potential of the third power signal end under the control of the second pull-down node.

8. A gate drive circuit comprising N cascaded shift register cells as claimed in any one of claims 1 to 7, N being a natural number greater than 2, wherein

The shift register unit includes an auxiliary pull-up circuit configured to output the clock signal to the auxiliary output terminal under control of the pull-up node, and an auxiliary noise reduction circuit configured to pull down the auxiliary output terminal by a potential of the third power supply signal terminal under control of the first pull-down node and pull down the auxiliary output terminal by a potential of the third power supply signal terminal under control of the second pull-down node,

the first input end of the nth stage shift register unit is electrically connected with the auxiliary output end of the (N-1) th stage shift register unit, the first reset end of the mth stage shift register unit is electrically connected with the auxiliary output end of the (m + 1) th stage shift register unit, N is greater than 1 and less than or equal to N, and m is greater than or equal to 1 and less than N;

the first input end of the 1 st stage shift register unit is electrically connected with the initial signal end of the grid drive circuit, and the first reset end of the Nth stage shift register unit is electrically connected with the cut-off signal end of the grid drive circuit.

9. A display device comprising the gate driver circuit according to claim 8.

10. A control method using a shift register cell according to any one of claims 1 to 7, comprising:

in a first stage, providing high-level signals to the first input end and the second input end, and transmitting the signals accessed by the second input end to the pull-up node by the input circuit so as to pull up the potential of the pull-up node;

in a second stage, the pull-up circuit transmits the clock signal to an output terminal under the control of the potential of the pull-up node;

in a third stage, the first reset circuit resets the pull-up node and the output terminal through the potential of the first power signal terminal under the control of the signal of the first reset terminal.

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