CN111355510A - 5G three-frequency power amplifier device - Google Patents
5G three-frequency power amplifier device Download PDFInfo
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- CN111355510A CN111355510A CN202010159635.1A CN202010159635A CN111355510A CN 111355510 A CN111355510 A CN 111355510A CN 202010159635 A CN202010159635 A CN 202010159635A CN 111355510 A CN111355510 A CN 111355510A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
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Abstract
The invention discloses a 5G three-frequency power amplifier device, and particularly relates to the technical field of 5G communication, which comprises an uplink signal channel switching circuit, three paths of uplink low-noise amplification circuits, a downlink signal channel switching circuit, three paths of downlink power amplification circuits, an input signal detection circuit, a monitoring unit, an output signal detection circuit, a power supply circuit and a switching logic management circuit, wherein the uplink signal channel switching circuit is connected with the three paths of uplink low-noise amplification circuits, the downlink signal channel switching circuit is connected with the three paths of downlink power amplification circuits, and the downlink signal channel switching circuit is in signal coupling with the input signal detection circuit. Any three-frequency signal of the invention can be connected with three interfaces PA _ IN and three interfaces LNA _ OUT corresponding to the three interfaces PA _ IN, and the switching logic is controlled by the uplink and downlink switch time sequence control of the corresponding synchronous interface 1, synchronous interface 2 and synchronous interface 3.
Description
Technical Field
The invention relates to the technical field of 5G communication, in particular to a 5G three-frequency power amplifier device.
Background
In a 5G communication network system, the frequency bands are more, single-frequency power amplification only supports the radio-frequency signal processing of a certain frequency band, and different communication frequency bands need different power amplifiers. The frequency division is carried out according to the current 5G (2.6GHz, 3.5GHz and 4.9GHz), and three radio frequency power amplification modules are required. Therefore, when the device needs to support radio frequency signals of multiple frequency bands to work, a plurality of radio frequency power amplifier modules are needed, and the device size is inevitably occupied.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a 5G three-frequency power amplifier device, which can effectively solve the frequency judgment of three signals so as to support the radio frequency signal processing of three frequency bands, and a three-frequency circuit is integrated in the device, so that the integration level is high, and the cost has great advantages.
In order to achieve the purpose, the invention provides the following technical scheme: A5G three-frequency power amplifier device comprises an uplink signal channel switching circuit, three uplink low-noise amplification circuits, a downlink signal channel switching circuit, three downlink power amplification circuits, an input signal detection circuit, a monitoring unit, an output signal detection circuit, a power supply circuit and a switching logic management circuit, wherein the uplink signal channel switching circuit is connected with the three uplink low-noise amplification circuits, the downlink signal channel switching circuit is connected with the three downlink power amplification circuits, the downlink signal channel switching circuit is in signal coupling with the input signal detection circuit, the three downlink power amplification circuits are in signal coupling with the output signal detection circuit, the output ends of the input signal detection circuit and the output signal detection circuit are both connected with the input end of the monitoring unit, and the output end of the monitoring unit is connected with the input end of the switching logic management circuit, the output end of the power supply circuit is connected with the switching logic management circuit;
the three-way downlink power amplifying circuit comprises PA _2.6G, PA _3.5G, PA _4.9G, the three-way uplink low-noise amplifying circuit comprises LNA _2.6G, LNA _3.5G, LNA _4.9G, the output end of the three-way downlink power amplifying circuit is connected with ANT _2.6G, ANT _3.5G, ANT _4.9G, and the input end of the three-way uplink low-noise amplifying circuit is connected with ANT _2.6G, ANT _3.5G, ANT _ 4.9G.
IN a preferred embodiment, the downlink signal channel switching circuit is used for switching downlink signal combinations, the inputs of the downlink signal channel switching circuit are connected with PA _ IN1, PA _ IN2 and PA _ IN3, and the output of the downlink signal channel switching circuit is connected with PA _2.6G, PA _3.5G, PA _ 4.9G.
IN a preferred embodiment, the input signal detection circuit is used for detecting three-frequency signals of PA _ IN1, PA _ IN2 and PA _ IN3 and sending the detected information to the monitoring unit through the radio frequency chip.
In a preferred embodiment, the three downlink power amplifiers are configured to amplify three downlink signal powers, and an input of the three downlink power amplifiers is connected to an output of the downlink signal channel switching circuit.
In a preferred embodiment, the output signal detection circuit is configured to detect output power of the three paths of downlink power amplifiers, and send information detected by the radio frequency chip to the monitoring unit.
In a preferred embodiment, the three uplink low-noise amplification circuits are configured to perform low-noise amplification on three uplink signals, and an output of the three uplink low-noise amplification circuits is connected to an input of the uplink signal channel switching circuit.
In a preferred embodiment, the uplink signal channel switching circuit is used for uplink signal combination switching, the input of the uplink signal channel switching circuit is connected with LNA _2.6G, LNA _3.5G, LNA _4.9G, and the output of the uplink signal channel switching circuit is connected with LNA _ OUT1, LNA _ OUT2 and LNA _ OUT 3.
In a preferred embodiment, the monitoring unit is configured to control the downlink signal channel switching circuit, the uplink signal channel switching circuit, the input signal detection circuit, the output signal detection circuit, and the switching logic management circuit.
In a preferred embodiment, the power supply circuit is used to provide power to the device.
In a preferred embodiment, the switching logic management circuit is configured to control the three paths of uplink low noise amplification circuits, the three paths of downlink power amplification circuits, the uplink signal channel switching circuit, and the downlink signal channel switching circuit.
The invention has the technical effects and advantages that:
according to the 5G three-frequency power amplifier device, after three-frequency (2.6GHz, 3.5GHz and 4.9GHz) signals enter the device, the signals can be automatically judged, then corresponding channels are opened, any signal combination mode can work under the device, three working modes, namely a signal three-to-one mode, a signal three-to-two mode and a signal three-to-three mode, are supported, the application is flexible, the use is convenient, and the device is suitable for processing radio frequency signals of 5G multiple frequency bands.
Drawings
Fig. 1 is a schematic block diagram of a 5G triple-band power amplifier of the present invention.
Fig. 2 is a circuit diagram of the input signal detection circuit and the downlink signal channel switching circuit of the present invention.
Fig. 3 is a circuit diagram of the uplink signal channel switching circuit according to the present invention.
Fig. 4 is a diagram of a three-way uplink low-noise amplifier circuit according to the present invention.
Fig. 5 is a circuit diagram of the three-way downlink power amplifying circuit and the output signal detection circuit of the present invention.
The reference signs are: the system comprises an uplink signal channel switching circuit 1, three uplink low-noise amplification circuits 2, a downlink signal channel switching circuit 3, three downlink power amplification circuits 4, an input signal detection circuit 5, a monitoring unit 6, an output signal detection circuit 7, a power supply circuit 8 and a switching logic management circuit 9.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more example embodiments. In the following description, numerous specific details are provided to give a thorough understanding of example embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, steps, and so forth. In other instances, well-known structures, methods, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The invention provides a 5G three-frequency power amplifier device, which comprises an uplink signal channel switching circuit 1, three uplink low-noise amplifying circuits 2, a downlink signal channel switching circuit 3, three downlink power amplifying circuits 4, an input signal detecting circuit 5, a monitoring unit 6, an output signal detecting circuit 7, a power supply circuit 8 and a switching logic management circuit 9, wherein the uplink signal channel switching circuit 1 is connected with the three uplink low-noise amplifying circuits 2, the downlink signal channel switching circuit 3 is connected with the three downlink power amplifying circuits 4, the downlink signal channel switching circuit 3 is in signal coupling with the input signal detecting circuit 5, the three downlink power amplifying circuits 4 are in signal coupling with the output signal detecting circuit 7, the output ends of the input signal detecting circuit 5 and the output signal detecting circuit 7 are connected with the input end of the monitoring unit 6, the output end of the monitoring unit 6 is connected with the input end of a switching logic management circuit 9, and the output end of the power supply circuit 8 is connected with the switching logic management circuit 9;
the three-way downstream power amplifying circuit 4 comprises PA _2.6G, PA _3.5G, PA _4.9G, the three-way upstream low-noise amplifying circuit 2 comprises LNA _2.6G, LNA _3.5G, LNA _4.9G, the output end of the three-way downstream power amplifying circuit 4 is connected with ANT _2.6G, ANT _3.5G, ANT _4.9G, and the input end of the three-way upstream low-noise amplifying circuit 2 is connected with ANT _2.6G, ANT _3.5G, ANT _ 4.9G.
The downlink signal channel switching circuit 3 is used for switching downlink signal combination, the input of the downlink signal channel switching circuit is connected with PA _ IN1, PA _ IN2 and PA _ IN3, and the output of the downlink signal channel switching circuit is connected with PA _2.6G, PA _3.5G, PA _ 4.9G.
The input signal detection circuit 5 is used for detecting three-frequency signals of PA _ IN1, PA _ IN2 and PA _ IN3, and sending information detected by the radio frequency chip to the monitoring unit 6.
The three downlink power amplifying circuits 4 are used for amplifying the power of three downlink signals, and the input of the three downlink power amplifying circuits is connected with the output of the downlink signal channel switching circuit 3.
The output signal detection circuit 7 is used for detecting the output power of the three downlink power amplifiers 4 and sending the information detected by the radio frequency chip to the monitoring unit 6.
The three uplink low-noise amplification circuits 2 are used for realizing low-noise amplification of three uplink signals, and the output of the three uplink low-noise amplification circuits is connected with the input of the uplink signal channel switching circuit 1.
The uplink signal channel switching circuit 1 is used for uplink signal combination switching, the input of the uplink signal channel switching circuit is connected with LNA _2.6G, LNA _3.5G, LNA _4.9G, and the output of the uplink signal channel switching circuit is connected with LNA _ OUT1, LNA _ OUT2 and LNA _ OUT 3.
The monitoring unit 6 is used for controlling the downlink signal channel switching circuit 3, the uplink signal channel switching circuit 1, the input signal detection circuit 5, the output signal detection circuit 7 and the switching logic management circuit 9.
The power circuit 8 is used for supplying power to the device.
The switching logic management circuit 9 is configured to control the three uplink low-noise amplification circuits 2, the three downlink power amplification circuits 4, the uplink signal channel switching circuit 1, and the downlink signal channel switching circuit 3.
The implementation mode is specifically as follows: as shown IN fig. 1-5, if a downstream signal of a tri-band signal (2.6GHz, 3.5GHz, 4.9GHz) is input from the PA _ IN1 interface of fig. 1 and processed by the input signal detection circuit 5, for example, if PA _ IN1 determines that 2.6G is a target signal, the switching logic management circuit turns on the corresponding circuit channel, so that the downstream signal of 2.6GHz is switched from the signal of PA _ IN1 to the corresponding PA _2.6G through the upstream signal channel switching circuit 1, the power amplification is then switched to the ANT _2.6G by the two-to-one switch, and the power amplification is then output to the ANT _2.6G, so as to realize the 2.6GHz downstream power amplification of the present apparatus, and at the same time, under the timing control of the downstream switch of the synchronous interface 1, the upstream signal of 2.6GHz receives the two-to-one switch from the ANT _2.6G and then is connected to the LAN _2.6G low-noise amplification circuit, and the signal selects the corresponding output interface _ OUT1 through the upstream signal channel switching circuit, so as to realize the present, the device is simultaneously controlled by an uplink switch time sequence of a synchronous interface 1, a power supply of a low-noise amplifying circuit is controlled to follow the whole system, only when a useful signal is detected when input into PA _ IN1, the uplink signal can be correspondingly switched to an identified working frequency, if a downstream signal of PA _ IN1 judges that a target signal is 3.5G or 4.9G, the working principle of a power amplifier circuit and a low-noise discharging circuit is the same as 2.6GHz, only the working frequency is different, the working frequency is not repeated here, and IN addition, the PA _ IN2, the PA _ IN3, the LNA _ OUT2, the LNA _ OUT3 working signal processing mode PA _ IN1 and LNA _ OUT1 are not repeated here, the device has the advantages that any signal of three frequencies (2.6GHz, 3.5GHz and 4.9GHz) can be connected with the three interfaces of PA _ IN1, PA _ IN2 and PA _ 3) and the corresponding three interfaces of LNA _ OUT (LNA _ OUT 7, LNA 2 and LNA 3) can be switched simultaneously corresponding to the synchronous interface 1, and the LNA _ OUT3 is controlled by the synchronous interface, The uplink and downlink switch time sequence control of the synchronous interface 2 and the synchronous interface 3;
further, the present embodiment supports three working modes:
the first working mode is as follows: one path mode (one-OUT-of-three mode), downlink signals of three frequency (2.6GHz, 3.5GHz, 4.9GHz) band signals, wherein one signal is input from the PA _ IN1 interface of fig. 1, and processed by the input signal detection circuit 5, for example, if PA _ IN1 determines that 2.6G is the target signal, the switching logic management circuit 9 turns on the corresponding circuit channel, so that the 2.6GHz downlink signal is switched from the signal of PA _ IN1 to the corresponding PA _2.6G through the uplink signal channel switching circuit 1, the power amplification is followed by the output of the ANT _2.6G through the switch-on switch, the 2.6GHz uplink signal is received from the ANT _2.6G through the switch-on switch and then is followed by the low noise amplifier circuit of LAN _2.6G, the signal selects the corresponding output interface LNA _ OUT1 through the uplink signal channel switching circuit 1, and the switching logic is controlled by the uplink and downlink switch timing control of the corresponding synchronous interface 1, therefore, the processing of the uplink and downlink signals of the device IN a2.6 GHz one-path mode is realized, if the downlink signals judge that the target signals are 3.5GHz and 4.9GHz, the working principle of a power amplifier circuit and a low-noise discharge circuit is the same as 2.6GHz, but the working frequency is different, the working frequency is not repeated, and of course, the signals can be input from interfaces PA _ IN2 and PA _ IN3, and the signal flow is the same;
the second working mode is as follows: two-way mode (signal three-IN-two mode), downlink signals of three-frequency (2.6GHz, 3.5GHz, 4.9GHz) band signals, wherein any two signals are respectively input from the PA _ IN1 and PA _ IN2 interfaces of fig. 1, and are processed by the input signal detection circuit 5, for example, if PA _ IN1 determines 2.6G as a target signal, PA _ IN2 determines 3.5G as a target signal, the switching logic management circuit 9 turns on the corresponding circuit channel, so that the 2.6GHz downlink signal is switched from the signal of PA _ IN1 to the corresponding PA _2.6G through the uplink signal channel switching circuit 1, the power is amplified and then output to the ANT _2.6G through the two-to-one switch, the 2.6GHz uplink signal receives the two-to-one-to-2.6G low-noise amplification circuit from the ANT _2.6G, and the signal selects the corresponding output interface 1, so as to the LNA signal of 3.5GHz, thereby, the signal from PA _ IN2 is switched to the corresponding PA _3.5G through the uplink signal channel switching circuit 1, the power amplification is followed by the two-switch one-switch output to ANT _3.5, the 3.5GHz uplink signal is received from ANT _3.5G and then is followed by the LAN _3.5G low noise amplifier circuit, the signal is passed through the uplink signal channel switching circuit 1, the corresponding output interface LNA _ OUT2 is selected, and the switching logic is controlled by the uplink and downlink switch time sequence control of the corresponding synchronous interface 1 and synchronous interface 2, thereby realizing the 2.6GHz and 3.5GHz two-way mode uplink and downlink signal processing of the device, if the PA _ IN1 and PA _ IN2 downlink signals judge that the target signal is 2.6GHz and 4.9GHz combination or 3.5GHz and 4.9GHz combination, the power amplifier circuit and low noise discharge circuit work principle is the same as the PA _ IN1, PA _ IN2 target signal is 2.6GHz and 3.5GHz combination, the power amplifier circuit does not work repeatedly, and the frequency is not the same, the downlink signal judgment target signal may be any two signal combinations of three frequencies (2.6GHz, 3.5GHz, and 4.9GHz), the downlink signal judgment target signal is different IN the port combination mode only if the port combination mode is different, the working frequencies are different and are not repeated here, the downlink signal judgment target signal may be any two signal combinations of three frequencies (2.6GHz, 3.5GHz, and 4.9GHz) only if the port combination mode is different, the working frequencies are different and are not repeated here;
the third working mode is as follows: three-way mode (signal three-select three mode), downlink signals of three-frequency (2.6GHz, 3.5GHz, 4.9GHz) band signals, wherein three signals are respectively input from PA _ IN1, PA _ IN2, PA _ IN3 interfaces of fig. 1, for example, the input signal detection circuit 5 processes the signals, for example, if PA _ IN1 is judged to be 2.6GHz as a target signal, PA _ IN2 is judged to be 3.5GHz as a target signal, PA _ IN3 is judged to be 4.9GHz as a target signal, the switching logic management circuit 9 turns on the corresponding circuit channel, so that the downlink signal of 2.6GHz is switched from the signal of PA _ IN1 to the corresponding PA _2.6G through the uplink signal channel switching circuit 1, power amplification is followed by two-to-one-switch output to ANT _2.6G, the uplink signal of 2.6GHz is received from ANT _2.6G through two-to one-switch and then is followed by the LAN _2.6G low noise amplification circuit, the corresponding LNA 1 output signal output through the LNA _ OUT interface, therefore, a 3.5GHz downlink signal is switched from the PA _ IN2 to the corresponding PA _3.5G through the uplink signal path switching circuit 1, the power amplification is followed by the output of the two-switch-one switch to the ANT _3.5, the 3.5GHz uplink signal is received from the ANT _3.5G and is followed by the LAN _3.5G low noise amplifier circuit, the signal is selected to correspond to the output interface LNA _ OUT2 through the uplink signal path switching circuit 1, the 4.9GHz downlink signal is received from the PA _ IN3 through the uplink signal path switching circuit 1 and is switched to the corresponding PA _4.9G, the power amplification is followed by the output of the two-switch-one switch to the ANT _4.9G, the 4.9GHz uplink signal is received from the ANT _4.9G and is followed by the LAN _4.9G low noise amplifier circuit, the signal is selected to correspond to the output interface OUT _3 through the uplink signal path switching circuit 1, and simultaneously the corresponding LNA _ OUT logic is switched to the synchronous controlled interface 1, The uplink and downlink switch time sequence control of the synchronous interface 2 and the synchronous interface 3 realizes the uplink and downlink signal processing of the device IN three modes of 2.6GHz, 3.5GHz and 4.9GHz, and can also be working combination modes such as 6 IN total, such as PA _ IN1, PA _ IN2 and PA _ IN3 downlink signal sequence being triple-frequency (2.6GHz, 4.9GHz and 3.5GHz) signal combination, and the like, and only the port signal combination modes are different, the working frequencies are different, and the operation is not repeated here.
As shown IN fig. 2, the signal channel switching circuit includes a downlink signal channel switching circuit 3 and an input signal detection circuit 5, the input signal detection circuit 5 is used for identifying a tri-band signal of the apparatus, the downlink signal channel switching circuit 3 is used for switching a downlink signal channel of the apparatus, for example, signals are input from PA _ IN1, PA _ IN2 and PA _ IN3, and are coupled to the input signal detection circuit 5 to respectively extract respective target rf signals, the power detection is performed on the tri-band (2.6GHz, 3.5GHz and 4.9GHz) signals by the rf power detection chip, and the detection data is fed back to the monitoring unit, for example, when the coupled signal of PA _ IN1 is detected to be a2.6 GHz rf signal, the monitoring unit 6 determines the target signal by a monitoring algorithm, controls the switching logic management circuit 9 to select the PA2.6G channel to be turned on, and then the signals pass through the downlink signal channel switching circuit 3, switching to PA2.6G channel, power amplification and then switching to two-switch one-switch output to ANT _2.6G, PA _ IN2, PA _ IN3 signal flow are the same.
As shown in fig. 3, the uplink signal path switching circuit 1, as the uplink signal path switching function of the present apparatus, for example, when the signal passes through the input signal detection circuit 5, determines 2.6GHz as the target signal, so as to select to turn on the LNA 2.6G path, the uplink signal receives the two-switch-one switch from ANT _2.6G and then is connected to the LAN _2.6G low noise amplifier circuit, and the signal passes through the uplink signal path switching circuit 1 to select the corresponding output interface LNA _ OUT1, LNA _ OUT2, and LNA _ OUT3, and the same procedure is applied.
The working principle of the invention is as follows:
the downlink signals of three-frequency (2.6GHz, 3.5GHz, 4.9GHz) band signals, wherein one signal is input from the PA _ IN1 interface of fig. 1 and processed by the input signal detection circuit 5, for example, if PA _ IN1 determines that 2.6G is the target signal, the switching logic management circuit 9 starts the corresponding circuit channel, so that the 2.6GHz downlink signal is switched from the signal of PA _ IN1 to the corresponding PA _2.6G through the uplink signal channel switching circuit 1, the signal is amplified and then output to ANT _2.6G through a one-to-two switch, so as to realize the 2.6GHz downlink power amplification of the present device, and simultaneously, under the timing control of the downlink switch of the synchronous interface 1, the 2.6GHz uplink signal receives a one-to-two switch from ANT _2.6G and then is output to the LAN _2.6G low-noise amplification circuit, the signal selects the corresponding output interface _ OUT1 through the uplink signal channel switching circuit 1, so as to realize the 2.6GHz uplink low-noise amplification of the present device, the device is simultaneously controlled by an uplink switch time sequence of a synchronous interface 1, a power supply of a low-noise amplifying circuit is controlled to follow the whole system, only when a useful signal is detected when input into PA _ IN1, the uplink signal can be correspondingly switched to an identified working frequency, if a downstream signal of PA _ IN1 judges that a target signal is 3.5G or 4.9G, the working principle of a power amplifier circuit and a low-noise discharging circuit is the same as 2.6GHz, only the working frequency is different, the working frequency is not repeated here, and IN addition, the PA _ IN2, the PA _ IN3, the LNA _ OUT2, the LNA _ OUT3 working signal processing mode PA _ IN1 and LNA _ OUT1 are not repeated here, the device has the advantages that any signal of three frequencies (2.6GHz, 3.5GHz and 4.9GHz) can be connected with the three interfaces of PA _ IN1, PA _ IN2 and PA _ 3) and the corresponding three interfaces of LNA _ OUT (LNA _ OUT 7, LNA 2 and LNA 3) can be switched simultaneously corresponding to the synchronous interface 1, and the LNA _ OUT3 is controlled by the synchronous interface, And the uplink and downlink switch time sequence control of the synchronous interface 2 and the synchronous interface 3.
The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;
secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the invention, only the structures related to the disclosed embodiments are referred to, other structures can refer to common designs, and the same embodiment and different embodiments of the invention can be combined with each other without conflict;
and finally: the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention are intended to be included in the scope of the present invention.
Claims (10)
1. A three frequency power amplifier device of 5G which characterized in that: the device comprises an uplink signal channel switching circuit (1), three uplink low-noise amplification circuits (2), a downlink signal channel switching circuit (3), three downlink power amplification circuits (4), an input signal detection circuit (5), a monitoring unit (6), an output signal detection circuit (7), a power supply circuit (8) and a switching logic management circuit (9), wherein the uplink signal channel switching circuit (1) is connected with the three uplink low-noise amplification circuits (2), the downlink signal channel switching circuit (3) is connected with the three downlink power amplification circuits (4), the downlink signal channel switching circuit (3) is in signal coupling with the input signal detection circuit (5), the three downlink power amplification circuits (4) are in signal coupling with the output signal detection circuit (7), and the output ends of the input signal detection circuit (5) and the output signal detection circuit (7) are connected with the input end of the monitoring unit (6), the output end of the monitoring unit (6) is connected with the input end of a switching logic management circuit (9), and the output end of the power supply circuit (8) is connected with the switching logic management circuit (9);
the three-way downlink power amplifying circuit (4) comprises a power amplifier PA _2.6G, PA _3.5G, PA _4.9G, the three-way uplink low-noise amplifying circuit (2) comprises a power amplifier LNA _2.6G, LNA _3.5G, LNA _4.9G, the output end of the three-way downlink power amplifying circuit (4) is connected with an ANT _2.6G, ANT _3.5G, ANT _4.9G, and the input end of the three-way uplink low-noise amplifying circuit (2) is connected with an ANT _2.6G, ANT _3.5G, ANT _ 4.9G.
2. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the downlink signal channel switching circuit (3) is used for switching downlink signal combination, the input of the downlink signal channel switching circuit is connected with PA _ IN1, PA _ IN2 and PA _ IN3, and the output of the downlink signal channel switching circuit is connected with PA _2.6G, PA _3.5G, PA _ 4.9G.
3. The 5G three-frequency power amplifier device according to claim 2, characterized in that: the input signal detection circuit (5) is used for detecting three-frequency signals of PA _ IN1, PA _ IN2 and PA _ IN3 and sending information detected by the radio frequency chip to the monitoring unit (6).
4. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the three downlink power amplifying circuits (4) are used for amplifying the power of three downlink signals, and the input of the three downlink power amplifying circuits is connected with the output of the downlink signal channel switching circuit (3).
5. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the output signal detection circuit (7) is used for detecting the output power of the three paths of downlink power big circuits (4) and sending information detected by the radio frequency chip to the monitoring unit (6).
6. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the three uplink low-noise amplification circuits (2) are used for realizing low-noise amplification of three uplink signals, and the output of the three uplink low-noise amplification circuits is connected with the input of the uplink signal channel switching circuit (1).
7. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the uplink signal channel switching circuit (1) is used for uplink signal combination switching, the input of the uplink signal channel switching circuit is connected with LNA _2.6G, LNA _3.5G, LNA _4.9G, and the output of the uplink signal channel switching circuit is connected with LNA _ OUT1, LNA _ OUT2 and LNA _ OUT 3.
8. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the monitoring unit (6) is used for controlling the downlink signal channel switching circuit (3), the uplink signal channel switching circuit (1), the input signal detection circuit (5), the output signal detection circuit (7) and the switching logic management circuit (9).
9. The 5G three-frequency power amplifier device according to claim 1, characterized in that: the power supply circuit (8) is used for supplying power to the device.
10. The 5G three-frequency power amplifier device according to claim 1, characterized in that: and the switching logic management circuit (9) is used for controlling the three paths of uplink low-noise amplification circuits (2), the three paths of downlink power amplification circuits (4), the uplink signal channel switching circuit (1) and the downlink signal channel switching circuit (3).
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| CN202010159635.1A CN111355510A (en) | 2020-03-11 | 2020-03-11 | 5G three-frequency power amplifier device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010159635.1A CN111355510A (en) | 2020-03-11 | 2020-03-11 | 5G three-frequency power amplifier device |
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| CN111355510A true CN111355510A (en) | 2020-06-30 |
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