CN111354644A - LDMOS device and manufacturing method thereof - Google Patents
LDMOS device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 38
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 26
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- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
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- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
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- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
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- 239000004065 semiconductor Substances 0.000 abstract description 3
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The application relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof. The method comprises the following steps: forming a pad oxidation layer on the first conductive type epitaxial layer through thermal oxidation; depositing a silicon nitride dielectric layer on the cushion oxide layer; opening the photoresist in the region where the ultra-shallow trench needs to be formed to form an etching window; etching and removing the silicon nitride dielectric layer at the position of the etching window; etching by taking the residual silicon nitride dielectric layer as a hard mask layer to form an ultra-shallow trench; forming an injection oxide layer on the surface of the ultra-shallow trench through thermal oxidation; injecting a drift region by taking the residual silicon nitride dielectric layer as a hard mask layer to form the drift region; forming a first liner oxide layer through a second thermal oxidation to enable the drift region to generate first thermal diffusion; forming an isolation trench in the first conductive type epitaxial layer on one side of the drift region; and forming a second liner oxide layer on the surface of the isolation trench through thermal oxidation so that the drift region undergoes second thermal diffusion.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof.
Background
The BCD (Bipolar-CMOS-DMOS) technology integrates different devices such as a Bipolar device with a precise analog function, a CMOS device with a digital design, an LDMOS device and the like on the same chip. For a Laterally Diffused Metal-Oxide Semiconductor (LDMOS) device, the on-resistance is an important index, and in the BCD process, the LDMOS device is integrated with the CMOS device in the same chip, but due to the device's on-resistanceHigh breakdown voltage BV (Breakdown Voltage) and low characteristic on-resistance RspThe (Specific on-Resistance) has a contradiction relationship, and the two are required to be compromised, so that the requirements of the application of the switch tube cannot be met.
Related art to obtain high breakdown voltage BV and low characteristic on-resistance RspAdditional reticles are typically required to do this, but this approach increases the manufacturing cost of the process platform.
Therefore, how to form high breakdown voltage BV and low characteristic on-resistance R while avoiding adding extra mask platespThe LDMOS device becomes a technical problem to be solved in the field.
Disclosure of Invention
The application provides an LDMOS device and a manufacturing method thereof, which can solve the problems of high breakdown voltage BV and low characteristic on-resistance R in the related artspThe problem of adding extra reticles is often required.
As a first aspect of the present application, there is provided a method of manufacturing an LDMOS device, the method of manufacturing the LDMOS device comprising at least the steps of:
providing a first conductive type substrate;
epitaxially growing a first conductive type epitaxial layer on the first conductive type substrate;
forming a cushion layer oxide layer on the first conductive type epitaxial layer through first thermal oxidation;
depositing a silicon nitride dielectric layer on the cushion layer oxide layer;
photoetching the silicon nitride dielectric layer, opening photoresist in an area needing to form the ultra-shallow groove, and forming an etching window;
etching and removing the silicon nitride dielectric layer at the position of the etching window;
removing the photoresist, and etching by taking the residual silicon nitride dielectric layer as a hard mask layer; forming a super shallow trench in the first conductive type epitaxial layer which is not covered by the silicon nitride dielectric layer;
forming an injection oxide layer on the surface of the ultra-shallow trench through second thermal oxidation;
injecting a drift region by taking the residual silicon nitride dielectric layer as a hard mask layer to form a drift region without thermal diffusion;
forming a first liner oxide layer on the injection oxide layer through third thermal oxidation, so that the drift region generates first thermal diffusion;
forming an isolation groove in the first conductive type epitaxial layer on one side of the drift region through a photoetching process;
forming a second liner oxide layer on the surface of the isolation trench through fourth thermal oxidation, so that second thermal diffusion occurs in the drift region;
depositing to form a silicon oxide layer, so that the silicon oxide layer covers the residual silicon nitride dielectric layer and is filled in the ultra-shallow trench and the isolation trench;
manufacturing a grid structure of the LDMOS transistor;
and forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid electrode structure.
Optionally, the steps of: manufacturing a grid structure of the LDMOS transistor; the method comprises the following steps:
performing chemical mechanical polishing by taking the silicon nitride dielectric layer as a stop layer;
performing first conductive type impurity injection to form a first conductive type region in the first conductive type epitaxial layer on the other side of the drift region;
manufacturing a grid structure on the first conductive type epitaxial layer; one side of the gate structure extends to the silicon oxide layer at the position of the ultra-shallow trench, and the other side of the gate structure extends to the first conductive type region.
Optionally, in the step: after the silicon nitride dielectric layer is used as a stop layer to carry out chemical mechanical polishing, the steps are as follows: before the gate structure is manufactured, the following steps are also carried out:
and implanting ions of the first conductivity type to form a surface electric field reducing structure in the epitaxial layer of the first conductivity type.
Optionally, the steps of: forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid structure, and the LDMOS tube comprises:
forming a second conductive type heavily doped region on one side of the ultra-shallow trench far away from the grid structure;
forming a heavily doped region of a first conductivity type in the region of the first conductivity type.
Optionally, the steps of: and injecting a drift region by taking the residual silicon nitride dielectric layer as a hard mask layer to form the drift region without thermal diffusion, wherein the method comprises the following steps:
and taking the residual silicon nitride dielectric layer as a hard mask layer, and performing drift region injection with energy of 30 KeV-150 KeV to form a drift region without thermal diffusion.
Optionally, in the step: before the first conductive type epitaxial layer is formed by epitaxial growth on the first conductive type substrate, the following steps are further performed:
and implanting into the first conductive type substrate to form a second conductive type buried layer, wherein the second conductive type buried layer extends downwards from the upper surface of the first conductive type substrate.
Optionally, the first conductivity type is P-type, and the second conductivity type is N-type.
Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.
As a second aspect of the present application, an LDMOS device is provided, which is manufactured by the method for manufacturing an LDMOS device of the first aspect of the present application, the LDMOS device at least includes:
the epitaxial layer comprises a first conductive type substrate and a first conductive type epitaxial layer formed on the first conductive type substrate; a drift region is formed in the first conductive type epitaxial layer;
the ultra-shallow trench isolation structure comprises an ultra-shallow trench arranged in the drift region and silicon oxide filled in the ultra-shallow trench;
the isolation groove is positioned in the first conduction type epitaxial layer on one side of the drift region, and silicon oxide is filled in the isolation groove;
and a grid structure of the LDMOS transistor, wherein a source electrode and a drain electrode of the LDMOS transistor are formed on two sides of the grid structure.
Optionally, the drain of the LDMOS transistor includes a second conductive type heavily doped region, and the second conductive type heavily doped region is located at one side of the ultra-shallow trench isolation structure, which is far away from the gate structure.
Optionally, a first conductive type region is further formed in the first conductive type epitaxial layer on the other side of the drift region.
Optionally, the source of the LDMOS transistor includes a heavily doped region of the first conductivity type, and the heavily doped region of the first conductivity type is located in the first conductivity type region.
Optionally, the gate structure is located on the first conductivity type epitaxial layer and extends along a surface of the first conductivity type epitaxial layer; one side of the gate structure extends to the surface of the ultra-shallow trench isolation structure, and the other side of the gate structure extends to the surface of the first conductive type region.
Optionally, the gate structure includes a gate insulating dielectric layer, a gate polysilicon layer disposed on the gate insulating dielectric layer, and sidewall dielectric layers disposed on two sides of the polysilicon layer;
one side of the gate insulating medium layer is connected with the ultra-shallow trench isolation structure, and the other side of the gate insulating medium layer extends to the first conduction type region along the surface of the first conduction type epitaxial layer.
Optionally, a second conductive type buried layer is implanted into the first conductive type substrate, and the second conductive type buried layer extends downward from the upper surface of the first conductive type substrate.
Optionally, a surface electric field reducing structure is formed in the first conductivity type epitaxial layer adjacent to the second conductivity type buried layer.
The technical scheme at least comprises the following advantages:
according to the method and the device, the mask number of the manufacturing process can be reduced under the condition of obtaining BV/Rsp equivalent to that of the related technology, and the competitiveness of the technology is favorably improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a structural view of a related art LDMOS device;
FIG. 2A is a schematic structural diagram of an LDMOS device manufactured in the embodiment of the present application after step S5 of the manufacturing method of the LDMOS device is completed;
FIG. 2B is a schematic structural diagram of an LDMOS device according to the present embodiment, which is formed after step S9 of the method for manufacturing the LDMOS device is completed;
fig. 2C is a schematic structural diagram of the LDMOS device in the embodiment of the present application after opening the photoresist in the step S11 for the isolation trench region to be formed by photolithography development;
FIG. 2D is a schematic structural diagram of a completed step S12 of a method for manufacturing an LDMOS device according to an embodiment of the present application;
FIG. 2E is a schematic structural diagram of the LDMOS device manufactured in the example of the present application after step S13 is completed;
fig. 2F is a schematic structural diagram of an LDMOS device according to an embodiment 5 of the present application after a P-type region is formed;
fig. 2G is a schematic structural diagram of the LDMOS device of embodiment 5 after the structure for reducing the surface electric field is formed;
FIG. 3 is a schematic diagram of an LDMOS device without a surface electric field reduction structure in an embodiment of the present application;
FIG. 4 is a schematic diagram of an LDMOS device with a structure for reducing a surface electric field formed on a P-type epitaxial layer according to an embodiment of the present application;
FIG. 5 is a distribution diagram of BV/Rsp of LDMOS devices provided by the embodiments and related technologies.
Reference numerals for the related art fig. 1 are as follows:
101-P type substrate, 102-N type buried layer, 103-P type epitaxial layer, 104-ultra shallow trench isolation structure, 105-Shallow Trench Isolation (STI) structure, 106-drift region, 107-RESURF layer, 108-P type region, 109-gate insulating dielectric layer, 110-gate polysilicon layer, 111-side wall dielectric layer, 112-N type heavily doped region, 113-P type heavily doped region
For the series of fig. 2, fig. 3 and fig. 4, the reference numbers relating to the present application are as follows:
101-a P-type substrate, 102-an N-type buried layer, 103-a P-type epitaxial layer, 104-an ultra-shallow trench isolation structure, 105-an isolation trench, 106-a drift region, 108-a P-type region, 109-a gate insulating dielectric layer, 110-a gate polycrystalline silicon layer, 111-a side wall dielectric layer, 112-an N-type heavily doped region, 113-a P-type heavily doped region and 200-an etching window.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
The first conductivity type and the second conductivity type mentioned in the present application are P-type or N-type, and for convenience of description, the first conductivity type is P-type and the second conductivity type is N-type.
FIG. 1 is a diagram illustrating a related art method for obtaining a high breakdown voltage BV and a low characteristic on-resistance RspAnd an LDMOS device structure is generally adopted. Referring to fig. 1, the LDMOS transistor comprises a P-type substrate layer 101, an N-type buried layer 102 and a P-type epitaxial layer 103 which are sequentially stacked from bottom to top, wherein the LDMOS transistor is formed on the P-type epitaxial layer 103. In the P-type epitaxial layer 103, below the LDMOS transistor, a Reduced Surface Field (RESURF) structure is formed by P-type boron ion implantation. The LDMOS transistor comprises a grid structure, a source region structure and a drain region structure, wherein the grid structure is arranged on the P-type epitaxial layer 103, and the source region structure and the drain region structure are respectively positioned on two sides of the grid structure. The drain region structure comprises a drift region 106 formed in a P-type epitaxial layer 103, an N-type heavily doped region 112 is formed in the drift region 106, an Ultra Shallow Trench Isolation (USTI) structure 104 is arranged in the drift region 106 between the N-type heavily doped region 112 and one side of a gate structure, and a Shallow Trench Isolation (STI) structure 105 is arranged in the P-type epitaxial layer 103 on the side of the drain region structure away from the gate structure.
The source region structure comprises a P-type body region 108 formed in a P-type epitaxial layer 103, a P-type heavily doped region 113 and another N-type heavily doped region 112 are formed in the P-type body region 108, and the other side of the gate structure extends to the other N-type heavily doped region 112.
The gate structure comprises a gate insulating medium layer 109 arranged on the P-type epitaxial layer 103, and one side of the gate insulating medium layer 109 extends to the ultra-shallow trench isolation structure 104 along the surface of the P-type epitaxial layer 103; the other side of the gate insulating medium layer 109 extends to the second N-type heavily doped region 112 along the surface of the P-type epitaxial layer 103; the gate insulating dielectric layer 109 is provided with a gate polysilicon layer 110, and side wall dielectric layers 111 are arranged on two sides of the laminated structure of the gate insulating dielectric layer 109 and the gate polysilicon layer 110.
For the LDMOS device structure in the related art, in order to increase the on-current of the device, i.e., reduce the on-resistance of the device, the ultra-shallow trench isolation structure 104 is additionally introduced on a part of the drift region, and at the same time, the electric field distribution at the edge of the gate structure can be improved. However, in order to introduce the ultra-shallow trench isolation structure 104, additional masks are required, which increases the manufacturing cost of the process platform; in addition, for the fabrication process of the LDMOS device in the related art, the implantation of the drift region 106 is performed after the completion of the ultra-shallow trench isolation structure 104, and this process also requires an additional mask for implantation.
The embodiment of the application can form high breakdown voltage BV and low characteristic on-resistance R while avoiding adding extra mask platesspThe LDMOS device of (1).
Example 1:
the embodiment provides a manufacturing method of an LDMOS device, which comprises the following steps of sequentially:
s1: providing a P-type substrate 101;
s2: epitaxially growing a P-type epitaxial layer 103 on the P-type substrate 101;
s3: forming a pad oxide layer 151 on the P-type epitaxial layer by first thermal oxidation;
s4: depositing a silicon nitride dielectric layer 152 on the pad oxide layer 151;
s5: referring to fig. 2A, a mask capable of forming an ultra-shallow trench pattern is used, a photoresist 153 is formed on the silicon nitride dielectric layer 152 by photolithography and development, the photoresist 153 in the region where the ultra-shallow trench is to be formed is opened, and an etching window 200 is formed;
s6: etching to remove the silicon nitride dielectric layer 152 at the position of the etching window 200;
s7: removing the photoresist, etching by taking the residual silicon nitride dielectric layer 152 as a hard mask layer, and etching to form an ultra-shallow trench in the P-type epitaxial layer 103 which is not covered by the silicon nitride dielectric layer 152;
etching to form an ultra-shallow trench extending downwards from the upper surface of the P-type epitaxial layer 103, wherein the depth of the ultra-shallow trench extension is
S8: forming an injection oxide layer 157 on the surface of the ultra-shallow trench through second thermal oxidation;
s9: referring to fig. 2B, drift region implantation is performed with the remaining silicon nitride dielectric layer 152 as a hard mask layer, and a drift region 106 without thermal diffusion is formed in the P-type epitaxial layer 103 around the ultra-shallow trench;
the ion implantation energy used during the drift region implantation is 30KeV to 150KeV, and the drift region implantation process performed with the remaining silicon nitride dielectric layer 152 as the hard mask layer in step S9 can block the drift region from being implanted into the active region of other devices, and the drift region implantation region is not thermally diffused, so that the drift region 106 formed without thermal diffusion has the same size as the ultra shallow trench opening, and the depth is shallower
S10: forming a first liner oxide layer 154 on the implant oxide layer 157 by a third thermal oxidation, so that a first thermal diffusion occurs in the drift region 106 during the third thermal oxidation;
after forming the first pad oxide layer 154 on the implanted oxide layer 157, the first pad oxide layer 154 is connected with the implanted oxide layer 157 into a whole, and the components of the first pad oxide layer 154 and the implanted oxide layer 157 are all silicon oxide, and the structure that the first pad oxide layer 154 and the implanted oxide layer 157 are connected into a whole covers the inner wall of the ultra-shallow trench; in the third thermal oxidation process to form the first pad oxide layer 154, the drift region 106, which is originally formed in S9 and is not thermally diffused, begins to diffuse all around, i.e., the drift region 106 is thermally diffused for the first time.
S11: the device structure after the step S10 is completed is coated with the photoresist 153, the photoresist 153 in the region where the isolation trench 105 needs to be formed is opened through photolithography and development (see fig. 2C), the region not covered by the photoresist 153 is etched away, and the isolation trench 105 is formed in the first conductivity type epitaxial layer on the drift region 106 side (see fig. 2D).
Wherein the isolation trench 105 extends downward from the upper surface of the P-type epitaxial layer 103, and the depth of the downward extension of the isolation trench 105 is
S12: referring to fig. 2D, a second pad oxide layer 155 is formed on the surface of the isolation trench 105 by a fourth thermal oxidation, so that the drift region 106 is thermally diffused a second time in the fourth thermal oxidation;
during the fourth thermal oxidation to form the second pad oxide layer 155, the drift region 106 where the first thermal diffusion occurs at S10 begins to diffuse further around, i.e., the drift region 106 undergoes the second thermal diffusion.
S13: referring to fig. 2E, silicon oxide is deposited on the surface of the device after step S12 to form a silicon oxide layer 156; the deposited silicon oxide layer covers the rest silicon nitride dielectric layer and is filled in the ultra-shallow trench and the isolation trench 105;
the formed silicon oxide layer 156 is integrated with the first pad oxide layer 154 formed on the inner wall of the ultra-shallow trench in step S10, so that the silicon oxide layer 156, the first pad oxide layer 154 and the implant oxide layer 157 filled in the ultra-shallow trench form the ultra-shallow trench isolation structure 104.
S14: and manufacturing a grid electrode structure of the LDMOS transistor, wherein a grid insulation medium layer of the grid electrode structure is connected with the ultra-shallow trench isolation structure 104.
S15: and forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid electrode structure.
The LDMOS device formed by the method of the present embodiment includes the following structure:
a P-type substrate 101, and a P-type epitaxial layer 103 formed on the P-type substrate 101; a drift region 106 is formed in the P-type epitaxial layer 103;
the ultra-shallow trench isolation structure 104, wherein the ultra-shallow trench isolation structure 104 comprises an ultra-shallow trench arranged in the drift region 106 and silicon oxide filled in the ultra-shallow trench;
the isolation trench 105 is located in the first conduction type epitaxial layer on one side of the drift region 106, and silicon oxide is filled in the isolation trench 105;
a P-type region 108, the P-type region 108 being located at the other side of the drift region 106;
and a grid electrode structure of the LDMOS transistor, wherein a grid insulation medium layer 109 of the grid electrode structure is connected with the ultra-shallow trench isolation structure 104.
The source electrode and the drain electrode of the LDMOS transistor are positioned on two sides of the grid electrode structure.
In the implantation process of the drift region 106 in this embodiment, no additional mask is required, that is, after the ultra-shallow trench is etched, the drift region implantation is performed by using the remaining silicon nitride dielectric layer 152 as the hard mask layer, and the drift region implantation process performed by using the remaining silicon nitride dielectric layer 152 as the hard mask layer can block the drift region from being implanted into the active region of another device. And then through the third thermal oxidation and the fourth thermal oxidation, thermal diffusion occurs in the drift region 106, so that impurities in the drift region 106 enter the accumulation region and the drain region of the device, thereby forming the LDMOS device with low on-resistance.
Example 2:
the present embodiment is based on embodiment 1, and is different from embodiment 1 in that step S14: the method for manufacturing the grid structure of the LDMOS transistor, wherein the grid insulation medium layer of the grid structure is connected with the ultra-shallow trench isolation structure 104, and the method comprises the following steps:
s141: referring to fig. 2F, Chemical Mechanical Polishing (CMP) is performed with the silicon nitride dielectric layer 152 as a stop layer, and the polishing is stopped when the silicon nitride dielectric layer 152 is removed by polishing, so as to form a smooth device surface, and the polished device surface is silicon oxide.
S142: referring to fig. 2F, performing P-type impurity implantation to form a P-type region 108 in the P-type epitaxial layer 103 on the other side of the drift region 106; wherein P-type region 108 may be a P-type body region or a P-type well region.
S143: manufacturing a grid structure on the P-type epitaxial layer 103; one side of the gate structure extends over the silicon oxide layer 156 at the ultra-shallow trench location and the other side extends over the P-type region 108.
Example 3:
the present embodiment is based on embodiment 2, and is different from embodiment 2 in that, for step S15: forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid structure, and comprising the following steps:
s151: forming an N-type heavily doped region 112 in the drift region 106 at the side of the ultra-shallow trench far away from the gate structure;
s152: a heavily P-doped region 113 is formed in P-type region 108 and another heavily N-doped region 112 is formed in P-type region 108 between heavily P-doped region 113 and the other side of the gate structure.
Example 4:
the present embodiment is based on embodiment 2, and the gate structure in embodiment 2 includes: the gate insulation dielectric layer 109, the gate polysilicon layer 110 arranged on the gate insulation dielectric layer 109, and the sidewall dielectric layers 111 positioned at two sides of the laminated structure of the gate insulation dielectric layer 109 and the gate polysilicon layer 110; one side of the gate structure is connected to the silicon oxide in the ultra-shallow trench, and the other side extends to the surface of the P-type region 108.
Example 5:
referring to fig. 2G, the present embodiment is different from embodiment 2 in that:
first, at S1: after providing the P-type substrate 101, at S2: before the P-type epitaxial layer 103 is formed by epitaxial growth on the P-type substrate 101, the following steps are also carried out:
and implanting into the P type substrate to form an N type buried layer, wherein the N type buried layer extends downwards from the upper surface of the P type substrate.
Secondly, after polishing in step S141, global or selective P-type boron ion implantation is performed before P-type impurity implantation in step S142, thereby forming the surface electric field reducing structure 107 in the P-type epitaxial layer.
By selecting proper implantation conditions of the drift region, the mask number of the manufacturing process can be reduced under the condition of obtaining equivalent BV/Rsp (refer to fig. 5), which is beneficial to improving the competitiveness of the technology.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (16)
1. A manufacturing method of an LDMOS device is characterized by at least comprising the following steps:
providing a first conductive type substrate;
epitaxially growing a first conductive type epitaxial layer on the first conductive type substrate;
forming a cushion layer oxide layer on the first conductive type epitaxial layer through first thermal oxidation;
depositing a silicon nitride dielectric layer on the cushion layer oxide layer;
photoetching the silicon nitride dielectric layer, opening photoresist in an area needing to form the ultra-shallow groove, and forming an etching window;
etching and removing the silicon nitride dielectric layer at the position of the etching window;
removing the photoresist, and etching by taking the residual silicon nitride dielectric layer as a hard mask layer; forming a super shallow trench in the first conductive type epitaxial layer which is not covered by the silicon nitride dielectric layer;
forming an injection oxide layer on the surface of the ultra-shallow trench through second thermal oxidation;
injecting a drift region by taking the residual silicon nitride dielectric layer as a hard mask layer to form a drift region without thermal diffusion;
forming a first liner oxide layer on the injection oxide layer through third thermal oxidation, so that the drift region generates first thermal diffusion;
forming an isolation groove in the first conductive type epitaxial layer on one side of the drift region through a photoetching process;
forming a second liner oxide layer on the surface of the isolation trench through fourth thermal oxidation, so that second thermal diffusion occurs in the drift region;
depositing to form a silicon oxide layer, so that the silicon oxide layer covers the residual silicon nitride dielectric layer and is filled in the ultra-shallow trench and the isolation trench;
manufacturing a grid structure of the LDMOS transistor;
and forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid electrode structure.
2. The method of fabricating the LDMOS device of claim 1, wherein the steps of: manufacturing a grid structure of the LDMOS transistor; the method comprises the following steps:
performing chemical mechanical polishing by taking the silicon nitride dielectric layer as a stop layer;
performing first conductive type impurity injection to form a first conductive type region in the first conductive type epitaxial layer on the other side of the drift region;
manufacturing a grid structure on the first conductive type epitaxial layer; one side of the gate structure extends to the silicon oxide layer at the position of the ultra-shallow trench, and the other side of the gate structure extends to the first conductive type region.
3. The method of fabricating the LDMOS device of claim 2, wherein in the step: after the silicon nitride dielectric layer is used as a stop layer to carry out chemical mechanical polishing, the steps are as follows: before the gate structure is manufactured, the following steps are also carried out:
and implanting ions of the first conductivity type to form a surface electric field reducing structure in the epitaxial layer of the first conductivity type.
4. The method of fabricating the LDMOS device of claim 2, wherein the steps of: forming a source electrode and a drain electrode of the LDMOS tube at two sides of the grid structure, and the LDMOS tube comprises:
forming a second conductive type heavily doped region on one side of the ultra-shallow trench far away from the grid structure;
forming a heavily doped region of a first conductivity type in the region of the first conductivity type.
5. The method of fabricating the LDMOS device of claim 1, wherein the steps of: and injecting a drift region by taking the residual silicon nitride dielectric layer as a hard mask layer to form the drift region without thermal diffusion, wherein the method comprises the following steps:
and taking the residual silicon nitride dielectric layer as a hard mask layer, and performing drift region injection with energy of 30 KeV-150 KeV to form a drift region without thermal diffusion.
6. The method of fabricating the LDMOS device of claim 1, wherein in the step: before the first conductive type epitaxial layer is formed by epitaxial growth on the first conductive type substrate, the following steps are further performed:
and implanting into the first conductive type substrate to form a second conductive type buried layer, wherein the second conductive type buried layer extends downwards from the upper surface of the first conductive type substrate.
7. The method for manufacturing an LDMOS device as claimed in any one of claims 1 to 6, wherein the first conductivity type is P-type and the second conductivity type is N-type.
8. The method for manufacturing an LDMOS device as claimed in any one of claims 1 to 6, wherein the first conductivity type is N-type and the second conductivity type is P-type.
9. An LDMOS device, wherein the LDMOS device is manufactured by the manufacturing method of the LDMOS device as claimed in any one of claims 1 to 6, and the LDMOS device at least comprises:
the epitaxial layer comprises a first conductive type substrate and a first conductive type epitaxial layer formed on the first conductive type substrate; a drift region is formed in the first conductive type epitaxial layer;
the ultra-shallow trench isolation structure comprises an ultra-shallow trench arranged in the drift region and silicon oxide filled in the ultra-shallow trench;
the isolation groove is positioned in the first conduction type epitaxial layer on one side of the drift region, and silicon oxide is filled in the isolation groove;
and a grid structure of the LDMOS transistor, wherein a source electrode and a drain electrode of the LDMOS transistor are formed on two sides of the grid structure.
10. The LDMOS device of claim 8, wherein the drain of the LDMOS transistor includes a heavily doped region of the second conductivity type located on a side of the ultra shallow trench isolation structure away from the gate structure.
11. The LDMOS device of claim 8, wherein a first conductivity type region is further formed in the first conductivity type epitaxial layer on the other side of the drift region.
12. The LDMOS device of claim 11, wherein the source of the LDMOS transistor includes a heavily doped region of first conductivity type located in the region of first conductivity type.
13. The LDMOS device of claim 11, wherein the gate structure is located on the first conductivity type epitaxial layer and extends along a surface of the first conductivity type epitaxial layer; one side of the gate structure extends to the surface of the ultra-shallow trench isolation structure, and the other side of the gate structure extends to the surface of the first conductive type region.
14. The LDMOS device of claim 11 or 13, wherein the gate structure includes a gate insulating dielectric layer, a gate polysilicon layer disposed on the gate insulating dielectric layer, and sidewall dielectric layers disposed on both sides of the polysilicon layer;
one side of the gate insulating medium layer is connected with the ultra-shallow trench isolation structure, and the other side of the gate insulating medium layer extends to the first conduction type region along the surface of the first conduction type epitaxial layer.
15. The LDMOS device of claim 8, wherein a second conductivity type buried layer is implanted in the first conductivity type substrate, the second conductivity type buried layer extending downward from an upper surface of the first conductivity type substrate.
16. The LDMOS device of claim 15, wherein the surface electric field reducing structure is formed in the first conductivity type epitaxial layer adjacent to the second conductivity type buried layer.
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