CN111354297A

CN111354297A - Pixel circuit suitable for low update frequency and related display device

Info

Publication number: CN111354297A
Application number: CN202010193780.1A
Authority: CN
Inventors: 林志隆; 陈柏澍; 邱文庆; 郑贸薰; 陈勇志
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-09-20
Filing date: 2020-03-19
Publication date: 2020-06-30
Anticipated expiration: 2040-03-19
Also published as: CN111354297B; TWI708233B; TW202113788A

Abstract

A pixel circuit suitable for low update frequency and a related display device are provided, the pixel circuit comprises a light emitting unit, a driving transistor, a first capacitor, a compensation circuit, a light emitting control circuit and a reset circuit. The first end, the second end and the control end of the driving transistor are respectively coupled to the first node, the second node and the third node. The first capacitor is coupled to the third node. The compensation circuit is coupled to the first node, the second node and the third node, and is used for providing the data voltage to the third node through the first node, the driving transistor and the second node in sequence. The light-emitting control circuit is used for selectively conducting the first node and a first power supply end and selectively conducting the light-emitting unit and the second node. The reset circuit is coupled to the fourth node. The fourth node is coupled to the first node, the second node and the third node through the compensation circuit. The reset circuit is used for setting the first node, the second node and the third node to have the same voltage through the fourth node.

Description

Pixel circuit suitable for low update frequency and related display device

Technical Field

The present disclosure relates to a pixel circuit and a display device, and more particularly, to a pixel circuit suitable for low refresh frequency.

Background

Modern people focus on the health management of individuals, often using wearable devices (e.g., smartband and watch) to measure various physiological indices. Wearable devices typically perform data gathering, storage, and wireless communication functions for long periods of time without external power supplies. Therefore, one of the design requirements of the wearable device is to reduce power consumption as much as possible with a limited total amount of power. Reducing the refresh rate of the display module is one of the effective means for saving power, but the brightness of the pixel circuit is gradually changed due to leakage at a low refresh rate, thereby reducing the display quality.

Disclosure of Invention

The present disclosure provides a pixel circuit, which includes a light emitting unit, a driving transistor, a first capacitor, a compensation circuit, a light emitting control circuit, and a reset circuit. The driving transistor comprises a first end, a second end and a control end. The first end, the second end and the control end of the driving transistor are respectively coupled to the first node, the second node and the third node. The first capacitor is coupled to the third node. The compensation circuit is coupled to the first node, the second node and the third node, and is used for providing the data voltage to the third node through the first node, the driving transistor and the second node in sequence. The light-emitting control circuit is used for selectively conducting the first node and a first power supply end and selectively conducting the light-emitting unit and the second node. The reset circuit is coupled to the fourth node. The fourth node is coupled to the first node, the second node and the third node through the compensation circuit. The reset circuit is used for setting the first node, the second node and the third node to have the same voltage through the fourth node.

The present disclosure provides a display device including a source driver, a gate driver and a plurality of pixel circuits. The source driver is used for providing data voltages. The gate driver is used for providing a first control signal, a second control signal, a third control signal and a fourth control signal. Each pixel circuit comprises a light-emitting unit, a driving transistor, a first capacitor, a compensation circuit, a light-emitting control circuit and a reset circuit. The driving transistor comprises a first end, a second end and a control end. The first end, the second end and the control end of the driving transistor are respectively coupled to the first node, the second node and the third node. The first capacitor is coupled to the third node. The compensation circuit is coupled to the first node, the second node and the third node, and is used for providing the data voltage to the third node through the first node, the driving transistor and the second node in sequence according to a second control signal and a third control signal. The light-emitting control circuit is used for selectively conducting the first node and the first power end according to a fourth control signal and for selectively conducting the light-emitting unit and the second node. The reset circuit is coupled to the fourth node. The fourth node is coupled to the first node, the second node and the third node through the compensation circuit. The reset circuit is used for setting the first node, the second node and the third node to have the same voltage through the fourth node according to the first control signal. The pixel circuits comprise a first pixel circuit, a second pixel circuit and a third pixel circuit which are respectively positioned on the (i-1) th row, the (i) th row and the (i + 1) th row. The first control signal of the second pixel circuit is identical to the second control signal of the first pixel circuit. The third control signal of the second pixel circuit is the same as the second control signal of the third pixel circuit, and i is a positive integer.

The pixel circuit and the display device can reduce the electric leakage phenomenon of the control end of the driving transistor, thereby being suitable for electronic products with low image update frequency.

Drawings

Fig. 1 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure.

Fig. 2 is a simplified waveform diagram of a plurality of control signals provided to the pixel circuit of fig. 1.

Fig. 3A is an equivalent circuit operation diagram of the pixel circuit of fig. 1 in a reset phase.

Fig. 3B is an equivalent circuit operation diagram of the pixel circuit of fig. 1 in the compensation stage.

Fig. 3C is an equivalent circuit operation diagram of the pixel circuit of fig. 1 in a light-emitting stage.

Fig. 4 is a functional block diagram of a pixel circuit according to another embodiment of the disclosure.

Fig. 5 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure.

Fig. 6 is a simplified functional block diagram of a display device according to an embodiment of the disclosure.

Description of reference numerals:

100. 400, 500, 630: pixel circuit

110. 510: driving transistor

120. 420: reset circuit

130: compensation circuit

140: light emission control circuit

150. 520, the method comprises the following steps: light emitting unit

C1: first capacitor

C2: second capacitor

M1: first switch

M2: second switch

M3: third switch

M4: the fourth switch

M5: fifth switch

M6: sixth switch

M7: seventh switch

S1: a first control signal

S2: the second control signal

S3: third control signal

S4: a fourth control signal

OVDD: high voltage of system

OVSS: low voltage of system

Pw 1: first power supply terminal

Pw 2: the second power supply terminal

Pw 3: third power supply terminal

Idr: drive current

N1: first node

N2: second node

N3: third node

N4: fourth node

Vdata: data voltage

CT [0] to CT [ n ], D1 to D4, EM [0] to EM [ n ]: control signal

600: display device

610: source driver

620: gate driver

R < 1 > -R < n-1 >: line of pixels

Vref: reference voltage

Detailed Description

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

Fig. 1 is a functional block diagram of a pixel circuit 100 according to an embodiment of the disclosure. The pixel circuit 100 includes a driving transistor 110, a reset circuit 120, a compensation circuit 130, a light-emitting control circuit 140, a light-emitting unit 150, a first capacitor C1, and a second capacitor C2. The first terminal, the second terminal and the control terminal of the driving transistor 110 are respectively coupled to the first node N1, the second node N2 and the third node N3, and the driving transistor 110 is used for determining the magnitude of the driving current Idr provided to the light emitting unit 150, so that the light emitting unit 150 generates a corresponding luminance.

The compensation circuit 130 is coupled to the first node N1, the second node N2 and the third node N3, and is used for providing the data voltage Vdata to the third node N3 through the first node N1, the driving transistor 110 and the second node N2 in sequence to detect the threshold voltage of the driving transistor 110. The driving transistor 110 determines the driving current Idr according to the data voltage Vdata received by the control terminal. The first capacitor C1 has a first terminal coupled to the third node N3, a second terminal for receiving the system high voltage OVDD, and a first capacitor C1 for storing the detected threshold voltage of the driving transistor 110.

The reset circuit 120 is coupled to the fourth node N4, and the fourth node N4 is coupled to the first node N1, the second node N2 and the third node N3 through the compensation circuit 130. The reset circuit 120 is used to set the first node N1, the second node N2 and the third node N3 to have the same voltage through the fourth node N4. In this way, when the third node N3 receives the data voltage Vdata during each frame period (frame period), the gate voltage of the driving transistor 110 has the same variation trend (e.g., rising or falling), thereby improving the variation of the driving current Idr caused by the hysteresis effect of the driving transistor 110. The first terminal of the second capacitor C2 is coupled to the fourth node N4, and the second terminal is used for receiving the system high voltage OVDD.

The light-emitting control circuit 140 is for receiving a system high voltage OVDD from the first power terminal Pw1, and is coupled between the first node N1 and the first power terminal Pw1, and is coupled between the second node N2 and the light-emitting unit 150. The first terminal of the light-emitting unit 150 is coupled to the light-emitting control circuit 140, and the second terminal is used for receiving the system low voltage OVSS from the second power terminal Pw 2. The light-emitting control circuit 140 is used for selectively turning on the first node N1 and the first power terminal Pw1 to enable the driving transistor 110 to generate the driving current Idr. The light emitting control circuit 140 is further configured to selectively turn on the light emitting unit 150 and the second node N2 such that the light emitting unit 150 receives the driving current Idr.

In one embodiment, the reset circuit 120 includes a first switch M1 and a second switch M2. The first terminal of the first switch M1 is coupled to the first node N1. The second terminal of the first switch M1 is coupled to the third node N3. The control terminal of the first switch M1 is used for receiving a first control signal S1. The first terminal of the second switch M2 is coupled to the fourth node N4. A second terminal of the second switch M2 is for receiving the system low voltage OVSS from the third power terminal Pw 3. The control terminal of the second switch M2 is used for receiving the first control signal S1.

In one embodiment, the compensation circuit 130 includes a third switch M3, a fourth switch M4, and a fifth switch M5. The first terminal of the third switch M3 is coupled to the third node N3. The second terminal of the third switch M3 is coupled to the fourth node N4. The control terminal of the third switch M3 is used for receiving the second control signal S2. The first terminal of the fourth switch M4 is coupled to the second node N2. The second terminal of the fourth switch M4 is coupled to a fourth node N4. The control terminal of the fourth switch M4 is configured to receive the second control signal S2. The first terminal of the fifth switch M5 is coupled to the first node N1. The second terminal of the fifth switch M5 is for receiving the data voltage Vdata. The control terminal of the fifth switch M5 is configured to receive the third control signal S3.

In one embodiment, the light control circuit 140 includes a sixth switch M6 and a seventh switch M7. The first terminal of the sixth switch M6 is coupled to the first power terminal Pw 1. The second terminal of the sixth switch M6 is coupled to the first node N1. The control terminal of the sixth switch M6 is configured to receive the fourth control signal S4. A first terminal of the seventh switch M7 is coupled to the second node N2. A second end of the seventh switch M7 is coupled to the first end of the light emitting unit 150. The control terminal of the seventh switch M7 is configured to receive the fourth control signal S4.

In practice, the plurality of switches and driving transistors 110 in the pixel circuit 100 can be implemented by various suitable types of P-type transistors, such as Thin-Film transistors (TFTs), Field Effect Transistors (FETs), Bipolar Junction Transistors (BJTs), etc. The Light Emitting unit 150 may be implemented by an Organic Light-Emitting Diode (OLED) or a Micro LED.

Fig. 2 is a simplified waveform diagram of a plurality of control signals provided to the pixel circuit 100. Fig. 3A is an equivalent circuit operation diagram of the pixel circuit 100 in the reset phase. Fig. 3B is an equivalent circuit operation diagram of the pixel circuit 100 in the compensation stage. Fig. 3C is an equivalent circuit operation diagram of the pixel circuit 100 in the light-emitting stage.

Referring to fig. 2 and fig. 3A, in the compensation phase, the first control signal S1 and the second control signal S2 have a Logic High Level (e.g., a low voltage Level that can turn on the P-type transistor); the third and fourth control signals S3 and S4 have a Logic Low Level (Logic Low Level, e.g., a high voltage Level that may turn off a P-type transistor).

Therefore, the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4 are turned on, and the rest of the switches in the pixel circuit 100 are turned off. The system low voltage OVSS is transmitted to the first node N1, the second node N2 and the third node N3 through the fourth node N4.

Since the first power source terminal Pw1 and the second power source terminal Pw2 are disconnected from the third power source terminal Pw3 during the compensation phase, the pixel circuit 100 does not generate a large current, and thus power consumption can be reduced.

Referring to fig. 2 and 3B, in the compensation phase, the first control signal S1 and the fourth control signal S4 have a logic low level; the second control signal S2 and the third control signal S3 have a logic high level.

Therefore, the third switch M3, the fourth switch M4, and the fifth switch M5 are turned on, and the rest of the switches in the pixel circuit 100 are turned off. The data voltage Vdata is transferred to the third node N3 through the fifth switch M5, the driving transistor 110, the fourth switch M4 and the third switch M3, so as to set the third node N3 to a voltage as shown in formula 1.

V3 is Vdata-Vth formula 1

Reference numeral V3 in equation 1 represents the voltage of the third node N3; reference Vth represents the threshold voltage of the driving transistor 110.

Referring to fig. 2 and 3C, in the light-emitting phase, the first control signal S1, the second control signal S2 and the third control signal S3 have a logic low level; the fourth control signal S4 has a logic high level.

Therefore, the sixth switch M6 and the seventh switch M7 are turned on, and the rest of the switches in the pixel circuit 100 are turned off. The driving transistor 110 operates in a saturation region because the third node N3 has a voltage shown in equation 1, and provides a driving current Idr shown in equation 2 to the light emitting cell 150, so that the light emitting cell 150 generates a corresponding brightness.

Reference Vsg in equation 2 represents the voltage difference between the first terminal and the control terminal of the driving transistor 110; the symbol k represents the product of Carrier Mobility (Carrier Mobility) of the driving transistor 110, the unit capacitance of the gate oxide layer and the gate width-to-length ratio.

As can be seen from equation 2, the magnitude of the driving current Idr is independent of the threshold voltage of the driving transistor 110. Therefore, even if the device characteristics of the pixel circuit 100 vary, the pixel circuit 100 can still accurately provide the gray scale value expected in design.

Referring to fig. 3C, in the light-emitting period, a first leakage current L1 flows from the first node N1 to the third node N3 through the first switch M1; a second leakage current L2 flows from the third node N3 to the third power terminal Pw3 through the third switch M3, the fourth node N4 and the second switch M2; the third leakage current L3 flows from the fourth node N4 to the second node N2 through the fourth switch M4. Although the originally stored charge of the third node N3 is lost due to the second leakage current L2 and the third leakage current L3, the first leakage current L1 can supplement new charge to the third node N3, thereby reducing the voltage variation of the third node N3.

In addition, the second switch M2 and the fourth switch M4 are respectively connected in series to the third switch M3, so that the magnitudes of the second leakage current L2 and the third leakage current L3 can be reduced.

In addition, the second capacitor C2 may further reduce the leakage of the third node N3. In summary, the pixel circuit 100 is suitable for a display device with a low refresh rate.

In some embodiments, the first leakage current L1 is designed to be the same as the sum of the second leakage current L2 and the third leakage current L3 by adjusting parameters (e.g., channel width, doping concentration, etc.) of the first switch M1, the second switch M2, the third switch M3 and the fourth switch M4. In this way, the voltage at the third node N3 is in dynamic equilibrium during the light emitting phase.

In an embodiment where the capacitance of the first capacitor C1 of the pixel circuit 100 is larger, the second capacitor C2 of the pixel circuit 100 is omitted.

Fig. 4 is a functional block diagram of a pixel circuit 400 according to an embodiment of the disclosure. The pixel circuit 400 includes a driving transistor 110, a reset circuit 420, a compensation circuit 130, a light-emitting control circuit 140, a light-emitting unit 150, a first capacitor C1, and a second capacitor C2.

The reset circuit 420 is coupled to a fourth node N4 and coupled to the first terminal of the light emitting unit 150, wherein the fourth node N4 is coupled to the first node N1, the second node N2 and the third node N3 through the compensation circuit 130. The reset circuit 420 is configured to set the first node N1, the second node N2, the third node N3 and the first terminal of the light emitting unit 150 to have the same voltage through the fourth node N4. Thus, it is ensured that the brightness generated by the light emitting unit 150 is not affected by the residual charge during the previous frame.

The reset circuit 420 includes a first switch M1, a second switch M2, and an eighth switch M8. The first terminal of the first switch M1 is coupled to the first node N1. The second terminal of the first switch M1 is coupled to the third node N3. The control terminal of the first switch M1 is used for receiving a first control signal S1. A first terminal of the second switch M2 is coupled to the fourth node N4, and a second terminal of the second switch M2 is configured to receive the system low voltage OVSS. The control terminal of the second switch M2 is used for receiving the first control signal S1. A first terminal of the eighth switch M8 is coupled to the first terminal of the light emitting unit 150. The second terminal of the eighth switch M8 is coupled to the second terminal of the second switch M2. The control terminal of the eighth switch M8 is configured to receive the second control signal S2.

The first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4 inputted to the pixel circuit 400 may have waveforms as shown in fig. 2. Referring to fig. 2 and fig. 4, the eighth switch M8 is turned on during the reset phase and the compensation phase to provide the system low voltage OVSS to the first terminal of the light emitting unit 150, thereby preventing the light emitting unit 150 from emitting light by mistake. In addition, the eighth switch M8 is turned off during the light emitting period. The remaining connections, elements, embodiments and advantages of the pixel circuit 100 in fig. 1 are all applicable to the pixel circuit 400 in fig. 4, and for brevity, the description is not repeated here.

In an embodiment where the capacitance of the first capacitor C1 of the pixel circuit 400 is larger, the second capacitor C2 of the pixel circuit 400 may be omitted.

Fig. 5 is a schematic diagram of a pixel circuit 500 according to an embodiment of the disclosure. The pixel circuit 500 includes a driving transistor 510, a light emitting unit 520 and a plurality of switches implemented by transistors, and the pixel circuit 500 is configured to operate according to control signals D1-D4, a system high voltage OVDD, a system low voltage OVSS and a reference voltage Vref. When the light emitting unit 520 emits light, the charge at the control terminal of the driving transistor 510 is reduced by the third leakage current L3 and the fourth leakage current L4, and cannot be compensated.

Table one shows the variation of the control terminal voltages of the driving transistor 110 of the pixel circuit 400 and the driving transistor 510 of the pixel circuit 500 during a frame period (frame period) with a length of 66.7 microseconds (ms). As shown in table one, compared to the pixel circuit 500, the voltage at the control terminal of the driving transistor 110 of the pixel circuit 400 is reduced by 78.7%, 96.4% and 83.1% in the low, middle and high gray levels, respectively. Therefore, the pixel circuit 400 is suitable for a display device with a low refresh rate.

Watch 1

Fig. 6 is a simplified functional block diagram of a display device 600 according to an embodiment of the disclosure. The display device 600 includes a source driver 610, a gate driver 620 and a plurality of pixel circuits 630. The plurality of pixel circuits 630 form a plurality of pixel rows R [1] to R [ n-1] arranged in parallel, where n is a positive integer. The pixel circuit 630 is used for receiving data voltages from the source driver 610 via a plurality of data lines, and for receiving control signals CT [0] CT [ n ] and EM [0] EM [ n ] from the gate driver 620 via a plurality of gate lines. Each pixel circuit 630 is disposed at an intersection of a data line and a gate line, and may be implemented by the pixel circuit 100 or the pixel circuit 400 described above. For simplicity and ease of illustration, other elements and connections in the display device 600 are not shown in fig. 6.

In the embodiment where the pixel circuit 630 is implemented by the pixel circuit 100 or the pixel circuit 400, the pixel circuits 630 in the pixel row R [ i ] respectively use the control signal CT [ i-1], the control signal CT [ i +1] and the control signal EM [ i ] as the first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4, where i is a positive integer and less than or equal to n. Similarly, the pixel circuits 630 in the pixel row R [ i-1] have the control signals CT [ i-2], CT [ i-1], CT [ i ] and EM [ i-1] as the first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4, respectively. Similarly, the pixel circuits 630 in the pixel row R [ i +1] respectively use the control signals CT [ i ], CT [ i +1], CT [ i +2] and EM [ i +1] as the first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4, and so on.

In other words, the first control signal S1 for the pixel circuit 630 in the i-th row is the same as the second control signal S2 for the pixel circuit 630 in the i-1 th row (i.e., the control signal CT [ i-1 ]). The third control signal S3 for the pixel circuit 630 in the i-th row is the same as the second control signal S2 for the pixel circuit 630 in the i + 1-th row (i.e., the control signal CT [ i +1 ]).

As can be seen from the above, since the control signals CT [0] CT [ n ] can have similar waveforms, the gate driver 620 can be implemented with a simple circuit structure, thereby reducing the design difficulty of the display device 600.

Certain terms are used throughout the description and following claims to refer to particular components. However, as one skilled in the art will appreciate, the same elements may be referred to by different names. The description and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

It is only the preferred embodiment of the present disclosure that the equivalent changes and modifications made by the claims of the present disclosure should be covered by the scope of the present disclosure.

Claims

1. A pixel circuit, comprising:

a light emitting unit;

a driving transistor including a first terminal, a second terminal and a control terminal, wherein the first terminal, the second terminal and the control terminal of the driving transistor are coupled to a first node, a second node and a third node, respectively;

a first capacitor coupled to the third node;

a compensation circuit, coupled to the first node, the second node and the third node, for providing a data voltage to the third node via the first node, the driving transistor and the second node in sequence;

a light emitting control circuit for selectively connecting the first node and a first power source terminal, and for selectively connecting the light emitting unit and the second node; and

a reset circuit coupled to a fourth node, wherein the fourth node is coupled to the first node, the second node and the third node through the compensation circuit, and the reset circuit is configured to set the first node, the second node and the third node to have the same voltage through the fourth node.

2. The pixel circuit of claim 1, wherein the reset circuit comprises:

a first switch including a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, the second terminal of the first switch is coupled to the third node, and the control terminal of the first switch is configured to receive a first control signal; and

a second switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the fourth node, the second terminal of the second switch is configured to receive a reference voltage, and the control terminal of the second switch is configured to receive the first control signal.

3. The pixel circuit of claim 1, wherein the compensation circuit comprises:

a third switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the third node, the second terminal of the third switch is coupled to the fourth node, and the control terminal of the third switch is configured to receive a second control signal;

a fourth switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch is coupled to the second node, the second terminal of the fourth switch is coupled to the fourth node, and the control terminal of the fourth switch is configured to receive the second control signal; and

a fifth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth switch is coupled to the first node, the second terminal of the fifth switch is for receiving the data voltage, and the control terminal of the fifth switch is for receiving a third control signal.

4. The pixel circuit according to claim 1, wherein the emission control circuit comprises:

a sixth switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the sixth switch is coupled to the first power source terminal, the second terminal of the sixth switch is coupled to the first node, and the control terminal of the sixth switch is configured to receive a fourth control signal; and

a seventh switch including a first end, a second end and a control end, wherein the first end of the seventh switch is coupled to the second node, the second end of the seventh switch is coupled to the light emitting unit, and the control end of the seventh switch is configured to receive the fourth control signal.

5. The pixel circuit of claim 1, wherein the reset circuit comprises:

a first switch including a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, the second terminal of the first switch is coupled to the third node, and the control terminal of the first switch is configured to receive a first control signal;

a second switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the fourth node, the second terminal of the second switch is configured to receive a reference voltage, and the control terminal of the second switch is configured to receive the first control signal; and

an eighth switch including a first end, a second end, and a control end, wherein the first end of the eighth switch is coupled to the light emitting unit, the second end of the eighth switch is coupled to the second end of the second switch, and the control end of the eighth switch is configured to receive a second control signal.

6. The pixel circuit of claim 1, further comprising a second capacitor, wherein the second capacitor is coupled to the fourth node.

7. The pixel circuit of claim 1, wherein the reset circuit is configured to receive a first control signal, the compensation circuit is configured to receive a second control signal and a third control signal,

the first control signal, the second control signal and the third control signal are respectively used for providing a first pulse, a second pulse and a third pulse with logic high level, and the first pulse, the second pulse and the third pulse have the same pulse width.

8. A pixel circuit as claimed in claim 7, wherein the emission control circuit is configured to receive a fourth control signal,

wherein when the fourth control signal has a logic low level, the first control signal, the second control signal and the third control signal provide the first pulse, the second pulse and the third pulse in sequence,

when the fourth control signal has the logic high level, the first control signal, the second control signal, and the third control signal have the logic low level.

9. The pixel circuit according to claim 1, wherein when the light emitting unit emits light, a first leakage current flows from the first node to the third node through the reset circuit, a second leakage current flows from the third node to the fourth node through the compensation circuit, and a voltage of the third node is in a dynamic balance state.

10. A display device, comprising:

a source driver for providing a data voltage;

a gate driver for providing a first control signal, a second control signal, a third control signal and a fourth control signal; and

a plurality of pixel circuits, wherein each pixel circuit comprises:

a light emitting unit;

a first capacitor coupled to the third node;

a compensation circuit, coupled to the first node, the second node and the third node, for providing the data voltage to the third node via the first node, the driving transistor and the second node in sequence according to the second control signal and the third control signal;

a light emitting control circuit for selectively connecting the first node and a first power terminal according to the fourth control signal, and for selectively connecting the light emitting unit and the second node; and

a reset circuit coupled to a fourth node, wherein the fourth node is coupled to the first node, the second node and the third node through the compensation circuit, and the reset circuit is configured to set the first node, the second node and the third node to have the same voltage through the fourth node according to the first control signal;

the plurality of pixel circuits comprise a first pixel circuit, a second pixel circuit and a third pixel circuit which are respectively positioned on the (i-1) th row, the (i + 1) th row and the (i + 1) th row, the first control signal of the second pixel circuit is identical to the second control signal of the first pixel circuit, the third control signal of the second pixel circuit is identical to the second control signal of the third pixel circuit, and i is a positive integer.