CN111353590A - Synapse simulation method and device with STDP synapse plasticity - Google Patents
Synapse simulation method and device with STDP synapse plasticity Download PDFInfo
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Abstract
The invention relates to a simulation method and a simulation device for simulating brain nerve synapse work by adopting an electronic circuit in the technical field of electronics, in particular to the simulation of STDP synapse plasticity characteristics and work. The invention simulates and realizes the characteristics by an electronic circuit through researching and analyzing the characteristics of the working process of the brain nerve synapse, thereby being beneficial to constructing a more perfect simulated neural network together with a matched neuron simulation device and simulating and analyzing the working mechanism of the neural network.
Description
The invention belongs to the technical field of divisional application of Chinese patent application No. 2014106066977 according to censorship opinions, and particularly relates to a synapse simulation method for simulating a neurosynaptic by adopting an electronic circuit and a simulation device thereof.
Background the working mechanism of the brain is one of the most important scientific studies. The current research reveals that the brain realizes information transmission and processing by means of neurons and synapses connected with each other among the neurons, and also reveals many structural features and working details of the single neurons and synapses to a certain extent, but the brain still has a scientific problem on how to realize high-level functions of the brain by connection relation and signal processing of the neurons and synapses. This is mainly because the structure and operation of individual neurons and synapses can be observed by ex vivo neuronal dissection and microscopy, but the ex vivo single or multiple neurons cannot constitute a signal processing pathway, and we cannot observe the working process of the whole living brain of a living organism from a microscopic angle. Therefore, even though studies have published specific structural features and operational characteristics of neurons and synapses, it is often impossible to fully and reasonably explain what role they play in the overall neural network, how they function, how they relate to other neurons, and particularly how they form and perform macroscopic brain functions.
In order to simulate and demonstrate the work of cranial nerves and construct artificial intelligence with memory and thinking functions, more and more researches are currently carried out to simulate the work of cranial nerves by establishing a mathematical simulation model or a neuron simulation device. Especially in recent years, many applicants filed patent applications of many neuron and synapse simulation techniques based on discovery of synaptic plasticity based on synaptic STDP characteristics and on the development of learning and memory models based on such synaptic STDP plasticity.
The current simulation technology of the neural synapse generally comprises a pre-synaptic membrane input circuit, a post-synaptic membrane output circuit, a simulation circuit with synaptic transmission characteristics, and the like, wherein the synaptic transmission characteristics simulation circuit can adjust an output signal through an input signal according to the characteristics of chemical synaptic transmission, especially plasticity of synapse according to STDP characteristics. STDP property of synaptic Plasticity, Spike Timing-Dependent Plasticity, i.e., order Dependent synaptic Plasticity. The current theory holds that: the STDP plasticity of synaptic transmission, i.e., the transmission efficiency of synapses, is related to the timing of the spikes of action potentials of neurons before and after synaptic contacts, if the spikes of pre-synaptic neurons are earlier than those of post-synaptic neurons, a long-term potentiation (LTP) phenomenon occurs, and the effect of synaptic transmission potentiation is greater the smaller the spike delay (for convenience of description, we may refer to this case as its spike signal having LTP characteristics); if the pre-synaptic neuron spikes slower than the post-synaptic neuron spikes, a long-term inhibition (LTD) phenomenon of synaptic transmission occurs, and the smaller the spike delay, the greater the effect of synaptic transmission reduction (for ease of description, we may refer to the case where its spike signal has LTD characteristics). Clearly, both LTP and LTD characteristics of spike signaling pertain to STDP plasticity of synaptic transmission.
The existing synapse simulation technology has the following problems:
1. synapses with different transmission characteristics exist between different areas of the brain and neurons with different functions, and the simulated neural network is often constructed by adopting synapses with the same characteristics, so that the neural network with complex functions cannot be accurately constructed and simulated.
2. In particular, existing synapse simulation techniques essentially simulate mature synapses with normal synaptic transmission efficiency. In fact, there are many synapses in the cerebral cortex, and before coordinated stimulation of related neural activity, only one kind of "preset" synapse is generated in the natural development process of fetus and infant, and these "preset" synapses do not form effective synaptic transmission efficiency yet, and in the following learning, memory and thinking process, through coordinated stimulation of excitation activity of neurons before and after synapse, the "preset" synapses are gradually activated to develop effective synaptic transmission efficiency. The existing synapse simulation techniques do not notice and simulate this process. Applicants have discovered that this process is extremely important in explaining the transformation of memory, long-term memory, to long-term memory, and in explaining the different roles of cortical and hippocampal neurons in the process of declarative memory formation.
Disclosure of the inventionthe object of the present invention is to disclose several synapse simulation methods and apparatus, which can more perfectly simulate the operation of several different synapses in the brain for the purpose of performing neural activity of different functions in the brain.
The technology of the neuron simulation device working in cooperation with the invention, the neural network constructed by the neuron simulation device and the synapse simulation device together, and the simulation and demonstration of the neural network on the operation of the neural circuit are shown in detail in the parent application of the invention.
The invention discloses a synapse simulation method and a synapse simulation device, and relates to synapses with three different characteristics existing in a brain neural network: "solidified synapses", "plastic synapses" and "preset synapses". The following is directly taken from the parent application of the present invention.
The solidifying synapse simulating device comprises a front membrane input end and a rear membrane output end, and is characterized in that; a capacitor discharge circuit is connected in series between the front film input end and the rear film output end, and the capacitor discharge circuit is connected with a capacitor discharge circuit in parallel. Therefore, the simplest synaptic transmission channel with fixed synaptic transmission efficiency, namely, the synaptic transmission channel without synaptic plasticity, is formed. As a simplest scheme, the capacitor discharge circuit is composed of a discharge capacitor, the front end of the discharge capacitor is connected with the front film input end, and the rear end of the discharge capacitor is connected with the rear film output end through a transfer resistor; the capacitor discharge circuit is used for slowly discharging the charge of the discharge capacitor; a charging diode is connected in reverse parallel with the transfer resistor for providing a special path for reverse charging of the discharge capacitor for the action potential pulse from the postsynaptic membrane output terminal, so as to generate enhancement of synaptic transfer efficiency. When the device works, if the input end of the front membrane inputs low-frequency action potential pulses, due to the action of the discharge capacitor, after each action potential pulse passes through, the discharge capacitor needs to discharge through the bleeder circuit for a period of time to recover. If several low frequency pulses follow, the discharge capacitor is charged and not discharged, and the following pulses are presented with larger impedance, namely the phenomenon that synapse transmission generates synapse inhibition on low frequency action potential. If the high-frequency sharp pulse is input at the input end of the front film, the influence is small because the impedance of the capacitor to the high-frequency sharp pulse is small. Particularly, if the high-frequency action potential can cause neuron integration burst of the postsynaptic membrane to have high threshold action potential, the action potential is reversely transmitted to the postsynaptic membrane, and the discharge capacitor is reversely charged through the diode, so that the discharge capacitor presents obviously enhanced transmission efficiency on the next action potential pulse, namely, synapse transmission generates synapse enhancement (facilitation) phenomenon on the high-frequency action potential.
The solidified synapse simulation device adopts an extremely simple circuit to realize the synapse transmission function of the common synapse, although synapse inhibition and synapse enhancement are only simple and rough simulation, the solidified synapse simulation device has the characteristics of extremely simple circuit, extremely low cost and extremely low volume, can be applied to signal input and output channels, signal feedback channels and other signal direct transmission channels in a simulated neural network, and can obviously save the cost when the scale of the simulated neural network is large.
In the prior art, a plastic synapse simulation device using an electronic circuit generally includes a front membrane input terminal, a rear membrane output terminal, an STDP timing identification circuit, an STDP operation circuit, and a synapse transmission performance adjustment circuit, wherein the STDP timing identification circuit is capable of identifying and determining whether a spike signal thereof has an STDP characteristic according to spike signals appearing at the front membrane input terminal and the rear membrane output terminal, and identifying whether the LTP characteristic belongs to the LTD characteristic or the LTP characteristic, outputting signals of the two characteristics to an STDP operation circuit for addition and subtraction accumulation, wherein the output value after operation is used for controlling a synapse transmission efficiency adjusting circuit, the transmission efficiency adjusting circuit adjusts the value of the synaptic transmission efficiency (namely, the strength of the synaptic output signal), so as to realize the plasticity change of the synaptic transmission output signal, namely, realize the synaptic plasticity. In the prior art, the functions of the STDP timing identification circuit, the STDP operation circuit and the synapse transmission performance adjustment circuit are realized by a program mostly using a microprocessor. The invention discloses another method and device for simulating plastic synapses.
The simulation method of the plastic synapse with the synapse transmitting STDP plasticity function comprises the following steps:
⑴, controlling the output signal of the back membrane output end by the input signal of the pre-synaptic membrane input end to synchronize the output signal with the input signal, ⑵, detecting the spike potential signals of the pre-synaptic membrane input end and the back membrane output end, ⑶, when recognizing that the spike potential signal conforming to the STDP characteristic appears between the front membrane input end and the back membrane output end, charging and discharging a storage device through a charging loop and a discharging loop according to the signal characteristic, if the signal is the LTP characteristic, charging is carried out, if the signal is the LDP characteristic, discharging is carried out, the time width of charging or discharging is determined by the STDP characteristic, ⑷, adjusting the magnitude of the voltage (or current) amplitude of the synaptic output signal by the voltage value of the storage device and outputting the voltage to the back membrane output end, ⑸, and the storage device is set with an initialization voltage with a certain value when starting to work.
As an optimization, when the voltage on the storage device is greater than or less than the initialization voltage, the voltage difference is slowly eliminated through a bidirectional bleeder circuit until the voltage on the storage device is equal to the initialization voltage value. (this approach mimics the slow elimination of synaptic LTP and LTD effects, making the synaptic simulation method of the invention more complete).
The invention relates to a 'plasticity synapse' simulation device with a synapse transmission STDP plasticity function, which comprises a front membrane input end, a rear membrane output end, an STDP time sequence identification circuit and a transmission efficiency adjusting circuit. The STDP timing sequence identification circuit belongs to the prior art, can identify and judge whether the spike signal has STDP characteristics or not according to the spike signals appearing at the front film input end and the rear film output end, and identifies and judges whether the spike signal belongs to the LTP characteristics or the LTD characteristics. The STDP time sequence identification circuit can adopt a CPU or MCU or other microprocessors to perform analog-to-digital conversion on spike potential signals at the input end of the front film and the output end of the rear film, and then identify and output LTP characteristic signals and LTD characteristic signals according to the time sequence and time difference. Or a voltage comparator and a time base circuit can be adopted to identify and output the LTP characteristic signal and the LTD characteristic signal through logic according to the time sequence and time difference of the spike potential signal. This is the prior art, and there is a related art in disclosing synapse simulation techniques implemented with electronic circuits with synapse-transferring STDP plasticity. Moreover, the operational features and implementation techniques described herein with respect to the STDP timing identification circuit are equally applicable to other portions of the present invention.
The "plastic synapse" of the invention is characterized by: the STDP time sequence identification circuit is provided with an LTP output end and an LTD output end; (the STDP timing sequence identification circuit controls the output signals of the LTP output end and the LTD output end according to the time sequence of the appearance of the spike potentials at the front film input end and the rear film output end); the LTP output and the LTD output are each connected via a charging circuit and a discharging circuit to an energy storage device for storing electrical energy. When the STDP time sequence identification circuit identifies the LTP characteristics, LTP pulse output appears at the LTP output end, the pulse width of the LTP pulse is in negative correlation with the time interval of the front spike potential signal and the rear spike potential signal, namely the LTP pulse accords with the STDP characteristics, and the LTP pulse charges the storage device through the charging loop; when the LTD characteristics are identified, the STDP time sequence identification circuit outputs LTD pulses at the LTD output end, the pulse width of the LTD pulses is in negative correlation with the time interval of the front spike potential signal and the rear spike potential signal, and the LTD pulses are discharged to the storage device through the discharge loop.
The power storage device is connected with an initialization charging circuit; (the initial charging circuit is used to rapidly charge the storage device to an initial voltage when the circuit starts to work, and has an initial charge to make the synapse have a transfer efficiency in an initial state, and the initial voltage is the reference voltage of the storage device, and the synapse output is the standard synapse transfer efficiency).
The output of the power storage device is connected to the synapse transmission efficiency adjusting circuit and used as the reference voltage of the output of the synapse transmission efficiency adjusting circuit; the output signal of the synaptic transmission performance adjusting circuit is connected to the posterior membrane output end as a synaptic signal output. The synapse transmission efficiency regulating circuit is synchronously controlled by the input signal of the input end of the front membrane, and the output signal of the synapse transmission efficiency regulating circuit is modulated by the output voltage of the electric storage device in strength and synchronously controlled by the input signal of the input end of the front membrane in time. The output of the synapse propagation performance adjusting circuit may further comprise a circuit of the "solidified synapse" simulating device, so as to have both synapse-enhancing and synapse-inhibiting propagation characteristics.
The simulation method and device of "plastic synapse" of the invention, the transmission characteristic of the chemical synapse with synapse plasticity is simulated, but it is different from the method of the prior art which generally adopts the method of changing the circuit transmission impedance (varistor circuit) to realize the transmission efficiency, but the STDP time sequence identification circuit is used to identify the LTP and LTD characteristics, and the charging circuit and the discharging circuit are used to charge and discharge an accumulator device, so that the voltage on the accumulator device generates high and low changes along with the charging (LTP time) and discharging (LTD time), and is used to modulate the output of the synapse efficiency adjusting circuit, thereby the voltage value of the synapse output pulse generates the corresponding adjustment of high and low, thereby realizing the simulation of the STDP synapse plasticity. The synapse simulation device provided by the invention is used for adjusting synapse plasticity, namely synapse transmission efficiency, and reflects that output voltage change is not output impedance change, so that the synapse simulation device is more convenient to work in cooperation with various neuron simulation devices, is particularly suitable for being used for making an independent device and constructing a simulation demonstration device of a neural network, and can conveniently display the current transmission efficiency of synapses in real time by detecting the voltage value of a power storage device. Moreover, no programmed variable resistance circuit is required, which is closer to the 'natural' actual working condition. The simulation device of the plasticity synapse simulates the nerve synapse existing in the hippocampus, striatum, amygdala, partial cortical areas and other positions of the brain, has strong and rapidly generated STDP synapse plasticity, and is an important characteristic for forming short-term and long-term memory.
As an optimization, the electric storage device is also connected with a bidirectional bleeder circuit; the bidirectional bleeder circuit is used for slowly eliminating the voltage rising or voltage falling change of the storage device caused by charging and discharging in a certain time until the voltage on the storage device is equal to the initialization voltage. Therefore, the slow elimination of the synapse LTP and LTD effects is simulated, so that the synapse simulation device is more perfect and can be suitable for continuous multi-process simulation work. As a simple solution, the bidirectional bleeder circuit comprises a regulation circuit (the voltage of which is equal to the initialization voltage of the electrical storage device, i.e. the reference voltage), which is connected to the electrical storage device via a resistor. When the voltage of the electric storage device is larger than the set voltage of the voltage stabilizing circuit (namely when the synapse LTP effect occurs), the electric storage device slowly discharges to the voltage stabilizing circuit through the resistor (namely the LTP effect is slowly eliminated); when the voltage of the storage device is smaller than the regulated voltage set voltage (namely, when a synaptic LTD effect occurs), the voltage stabilizing circuit slowly charges the storage device through the resistor (namely, the LTP effect is slowly eliminated). After a certain time, namely after the effective period of synapse plasticity, the voltage of the electric storage device is equal to the set voltage of the voltage stabilizing circuit, namely the normal output amplitude when no synapse plasticity occurs.
The method for simulating the preset synapses comprises ⑴, presetting a synapse transmission channel between a front membrane input end and a rear membrane output end of a simulated synapse, closing the operation of the synapse transmission channel when the synapse transmission channel starts to operate, ⑵, detecting spike potential signals of the front membrane input end and the rear membrane output end, ⑶, calculating the occurrence condition of the signals (including integration or counting) when the spike potential signals meeting the STDP characteristic appear between the front membrane input end and the rear membrane output end, and ⑷, starting the preset synapse transmission channel to operate when the occurrence condition of the spike potential signals meeting the STDP characteristic meets a set rule, so that a transmission channel with synapse transmission efficiency is established between the front membrane input end and the rear membrane output end of the synapse.
The setting rule is one of the following two types: 1. counting the number of times of signals according with the LTP characteristics in the STDP characteristics, and starting the work of a preset synapse transmission channel if the number of times of the LTP reaches a set value within a set time; or 2, counting the times of the signals according with the LTP characteristics and the LTD characteristics without setting counting time, wherein the times of the signals with the LTP characteristics are added, and the times of the signals with the LTD characteristics are subtracted; and if the total count reaches a set value, starting the work of a preset synapse transmission channel.
In a further improvement, the method for simulating the preset synapse of the present invention further comprises:
⑸, after the preset synapse transmission channel is started, continuously detecting spike potential signals of the pre-synaptic membrane input end and the post-synaptic membrane output end, ⑹, calculating the occurrence condition of the signals when the spike potential signals which accord with the STDP characteristic appear between the current membrane input end and the post-synaptic membrane output end, and closing the preset synapse transmission channel to cut off the transmission channel of the pre-synaptic membrane input end and the post synaptic membrane output end when the occurrence condition of the spike potential signals which accord with the STDP characteristic meets a second set rule.
The second setting rule is one of the following two rules: 1. counting the number of times of signals according with the LTD characteristics, and if the number of times of the LTD reaches a set value within a set time, closing the work of a preset synapse transmission channel; 2. counting the times of the signals according with the LTP characteristics and the LTD characteristics at the same time, wherein the times of the signals with the LTP characteristics are added, and the times of the signals with the LTD characteristics are subtracted; and if the total count is lower than the set value, closing the operation of the synaptic transmission channel. It is obvious that in this latter setting rule, the setting value of the total count for closing the synaptic transmission channel is necessarily smaller than the setting value of the total count for starting the synaptic transmission channel.
The invention relates to a simulation device of a preset synapse, which comprises a front membrane input end, a rear membrane output end and a preset synapse transmission channel; the method is characterized in that: the STDP time sequence identification circuit is used for identifying a spike potential signal with STDP characteristics between the front film input end and the rear film input end; the output of the STDP timing sequence identification circuit is connected to an STDP integrating circuit, and the output of the STDP integrating circuit is connected to a threshold control circuit; the output end of the threshold control circuit is connected to a channel switch circuit; the channel switch circuit is used for controlling the connection and disconnection of the synapse transmission channel.
The working process is as follows: the STDP integrating circuit accumulates the signals which are identified and output by the STDP time sequence identifying circuit within a certain time according to a set rule and converts the signals into output values of the output signals; the threshold control circuit is used for detecting the output value of the output signal of the integrating circuit, and when the output value of the integrating circuit reaches or is higher than a set threshold 1, an output control signal is generated; and starting to connect the synaptic transmission channel through the channel switch circuit, and establishing the synaptic transmission channel with synaptic transmission efficiency between the front membrane input end and the rear membrane output end.
The working process further comprises the following steps: after the channel switch circuit starts to connect a synapse transmission channel, the threshold control circuit continuously detects the output value of the output signal of the integrating circuit, and when the output value of the integrating circuit is lower than a set threshold 2, the output control signal is closed; and closing the synaptic transmission channel through the channel switching circuit. I.e. to cut off the synaptic transmission channel between the anterior membrane input and the posterior membrane output. Obviously, the set threshold 2 needs to be smaller than the set threshold 1. As a more reasonable setting, setting threshold 2 may correspond to 65% to 85% of the value of setting threshold 1.
The predetermined synaptic transmission channel is a synaptic transmission channel with synaptic transmission efficiency, and the synaptic transmission characteristics comprise one or more of synaptic facilitation, synaptic inhibition, synaptic long-term plasticity, especially synaptic plasticity with STDP characteristic, and the transmission characteristics. The predetermined synaptic transmission channel is essentially a synaptic simulation device with transmission characteristics, which may be a "fixed synaptic" device as described above, a "plastic synaptic" device as described above, or other prior art synaptic simulation devices including synaptic connection devices made of memory varistor materials.
The setting rule of the integration circuit is as follows: the output value of the output signal is increased when the signal of the LTP characteristic occurs, and the output value of the output signal is decreased when the signal of the LTD characteristic occurs. (compared with the simulation method, the simulation device only adopts one mode of the operation rule of the STDP, wherein the operation rule is closer to the brain working characteristic).
Compared with the synapse simulation technology with synapse transmission STDP plasticity in the prior art, the simulation method and the simulation device for the preset synapse have different processing although the technology for detecting and identifying STDP characteristic spike signals between presynaptic and postsynaptic membranes is adopted. The conventional STDP synapse simulation technique initially has synaptic transmission efficiency, and then adjusts the synaptic transmission efficiency according to the detection of the identified spike signal conforming to the STDP characteristic: if the LTP characteristic signal appears, the synaptic transmission efficiency is improved, and if the LTD characteristic signal appears, the synaptic transmission efficiency is reduced, so that the synaptic transmission plasticity is realized. From the perspective of brain structure, this type of synapse exists more between neurons in the hippocampus, amygdala, striatum, etc. regions for short term (or long term) memory of information.
The presupposed synapse of the present invention comprises a synapse transmission channel with synapse transmission efficiency, i.e. the presupposed synapse comprises a synapse simulation device, and is based on the synapse simulation device, and a technology of how to recognize and judge signals, and then to start or close the synapse transmission channel. The synapse transmission channel is closed at the initial working stage, no synapse transmission efficiency is provided, and the work of connecting the synapse transmission channel is started only when spike potential signals which accord with LTP characteristics in STDP characteristics appear between the current membrane input end and the rear membrane output end for many times and are accumulated to a certain degree, so that effective synapse transmission efficiency is established between the front membrane input end and the rear membrane output end. It mimics a synapse between neurons in the brain cortex, etc., which initially does not have synaptic transmission efficiency, and requires multiple long-term co-stimulation of both neurons before and after the synapse is formed, before it is activated into an effective synapse, and once activated, its transmission efficiency is relatively stable.
A "Preset synapse" does not automatically close once it is activated as a valid synapse, and if a spike signal for the LTP signature is present, or if there is any synaptic transmission through it that activates a pre-synaptic neuron to generate an action potential (which actually generates the LTP signature), the STDP integration circuit increases in value until it reaches a maximum value, making the synaptic transmission effect more reliable, and the synapse continues to maintain effective transmission efficiency even in the absence of the LTP signal. Only when the LTP characteristic does not appear for a long time and the inhibitory signal of the LTD characteristic appears for a plurality of times, the numerical value of the integrating circuit is slowly reduced and is finally lower than the threshold value, the threshold control circuit closes the output signal, and the channel switch circuit closes the synapse transmission channel to ensure that the synapse fails again. This operation state is used to simulate the stability of the brain's long-term memory, but even if information is stored as long-term memory, if the information is not used for a long period of time and there is long-term confusion (competition) of other inhibitory information, the long-term memory is slowly forgotten.
In the invention, an STDP timing sequence identification circuit belongs to the prior art, and how an STDP integration circuit operates LTP and LTD characteristic signals output by the STDP timing sequence identification circuit can generally adopt a microprocessor such as an MCU (microprogrammed control Unit) and the like to count the LTP characteristic signals and the LTD characteristic signals according to a set rule, then compare a count value with a set value and output a control signal according to a comparison result. The invention also discloses another simulation technology for realizing the STDP integrating circuit by adopting the storage device. The STDP integrating circuit comprises a charging circuit, a discharging circuit and an electric storage device, wherein an LTP output end and an LTD output end of the STDP timing sequence identification circuit are respectively connected to the electric storage device through the charging circuit and the discharging circuit; the output end of the electric storage device is connected to the input end of the threshold control circuit. When the device works, the voltage of the electric storage device is adjusted along with the STDP effect, the threshold control circuit detects the voltage of the electric storage device, compares the voltage with a set value, and accordingly starts or closes the work of a synapse transmission channel. The starting synapse transmission channel can be activated through multiple LTP characteristic signals, so that the preset synapse becomes the effective synapse; and the synapse transmission channel can be closed through multiple LTD characteristic signals, so that the effective synapse is invalid, and the extinction of the synapse is simulated. The mode can realize STDP integral operation without adopting MCU or relying on artificial program, and more intuitively and naturally simulate the working process of human brain.
The preset synapse simulator is particularly suitable for being manufactured into an independent synapse simulator, and forms an experimental neural simulation network together with the neuron simulator disclosed by the invention, so that the experimental neural simulation network is used for demonstrating and researching the work and the function of a brain, and the neuron simulator and the synapse simulator can be freely connected according to needs without being limited by a topological structure and can form the neural simulation network according to any topological structure. In this application, the "preset synapse" simulation means may further comprise a voltage indication means for indicating the output voltage of the storage device. Therefore, the strength of the transmission efficiency of the synapse can be visually displayed, and scientific research experiments are facilitated.
By adopting the neuron and synapse simulation device, simulated neural networks with different working characteristics can be established.
Description of the drawings fig. 1 is a schematic diagram of the structure of a neuron. Fig. 2 is a circuit block diagram of a neuron simulation device of the prior art. Fig. 3 is a schematic diagram of the operation principle of a neural simulation network in the prior art. Fig. 4 is a schematic diagram of the structure of an axon of a neuron. Fig. 5 is a circuit block diagram of a first neuron simulation device according to the present invention. Fig. 6 is a schematic circuit diagram of a single-chip microcomputer for implementing the neuron simulation device of fig. 5. Fig. 7 is a schematic circuit diagram of a neuron simulation device of fig. 5 implemented using a general simulation circuit. Fig. 8 is a circuit block diagram of a second neuron simulation device according to the present invention. Fig. 9 is a schematic circuit diagram of a single-chip microcomputer for implementing the neuron simulation device of fig. 8. Fig. 10 is a schematic circuit diagram of a neuron simulation device of fig. 8 implemented using a general simulation circuit. Fig. 11 is a circuit schematic diagram of a modulation input circuit of the neuron simulation device. FIG. 12 is a schematic diagram of the electrical circuit of the "solidified synapse" of the present invention. FIG. 13 is a graphical illustration of synaptic transmission efficacy versus spike timing for STDP plasticity. FIG. 14 is a block circuit diagram of a prior art synapse-simulating device with STDP plasticity. FIG. 15 is a block circuit diagram of a "plastic synapse" simulation apparatus in accordance with the present invention. FIG. 16 is a schematic circuit diagram of one embodiment of the "plastic synapse" simulating device of FIG. 15. FIG. 17 is a block circuit diagram of a "Preset synapse" simulation apparatus in accordance with the present invention. FIG. 18 is a circuit block diagram of a "Preset synapse" simulation apparatus employing a storage device to implement an STDP integration circuit. FIG. 19 is a schematic circuit diagram of the "Preset synapse" simulation apparatus of FIG. 18. FIG. 20 is a circuit schematic of an embodiment of a "Preset synapse" simulation device. Fig. 21 is a circuit schematic diagram of an STDP identification circuit.
Detailed description of the preferred embodimentsthe following is a description of the principles and implementations of the present invention.
According to current studies, a typical interneuron, as shown in figure 1, is composed primarily of soma 1, dendrites 2, and axons 3. Neurons typically have multiple dendrites that branch repeatedly, like branches; both soma and dendrites may synapse with axon terminals from other neurons in front, becoming the input of the neuron, receiving signals from the preceding neurons. The interneuron generally has an axon 3, the end of the axon 3 forms synapse with dendrites or soma of other neurons in the back, and the axon 3 corresponds to the output end of the neuron and transmits signals to the following neurons.
Synapses (here primarily chemical synapses) are important links in signal transmission between neurons. Synapses include presynaptic membranes, postsynaptic membranes and synaptic clefts, with the presynaptic membrane being located at the axonal terminal of the preceding neuron and the postsynaptic membrane being located at the dendrite or soma of the following neuron. When a preceding neuron is stimulated to produce an action potential, the presynaptic membrane releases a neurotransmitter into the synaptic cleft, and the postsynaptic membrane absorbs the neurotransmitter and causes a change in the ionic substance inside the neuron, thereby producing electrical stimulation of the cell membrane. These electrical excitations are integrated within the neuron in a superposition, including spatial integration of the transmitted signals from multiple synapses and temporal integration of multiple signals from the same synapse, with the neuron bursting at an action potential when the integrated electrical excitation reaches or exceeds a certain threshold. The action potential is transmitted to the axon terminal and is transmitted to the next neuron through synapse to complete the processes of signal integration, triggering and transmission, and meanwhile, the residual excitation of the membrane is eliminated so as to carry out the next signal integration. The signaling efficiency of synapses can vary, i.e., synapses are plastic, which is the basis for learning and memory. According to the widely accepted theory at present, the plasticity of synaptic transmission potency changes in accordance with the STDP principle, i.e. the order dependent synaptic plasticity, as described in the "background" section of the present invention.
FIG. 2 is a circuit configuration of a typical current interneuron simulation technique, generally consisting of an input terminal (simulating the stimulation input of dendrites or soma), a signal processing module (for simulating the part of neurons that integrate and process signals), and an output terminal (for simulating axon output); the signal processing module comprises an input membrane integrating circuit (used for simulating the integration process of membrane excitation potential), a threshold value trigger circuit (used for simulating the action of neuron triggering action potential when the integration of the membrane excitation potential reaches a threshold value), a pulse generating circuit (used for simulating the pulse generation of the action potential), a membrane discharging circuit (used for simulating the action of depolarization of the membrane excitation potential after the action potential is triggered and forming a refractory period), and generally an action potential output circuit used for isolating and amplifying action potential pulses generated by the pulse generating circuit.
The simulation synapses generally adopt a rheologic technology and have An STDP effect, because the STDP effect of the synapses depends on the precise timing sequence of the spikes of the pre-synaptic post-membrane, namely, the signals of the action potentials of the axons of the pre-synaptic neurons, and the signals of the action potentials of the synapses of the pre-synaptic neurons generally cannot be generated by a computer system, and even though the computer system adopts a computer system with a complicated artificial neuron spike control function, the computer system has a complicated artificial spike control function, and the artificial spike control function of the artificial spike control function is required by a computer system with a complicated artificial spike control function, which is required by a computer system with a clock control terminal (a computer system with a clock signal simulation module) and a computer system with a complicated artificial spike control function of artificial spike control, which is required by a computer system with a clock signal simulation modules (a computer system with a special artificial spike control module, a special computer system with special clock signal, a special computer system.
Through further research on action potentials of neurons, the applicant notices that during the process of integrating input stimulation and generating the action potentials, the neurons can generate action potentials of different subtypes in different generation modes due to slight difference of the change forms of input stimulation signals and influence of the action of other peripheral neurons on the chemical substance environment outside the neurons, and brings great difference of working results.
FIG. 4 is a schematic structural diagram of an axon portion of a neuron. As in fig. 1, neurons are composed mainly of soma 1, dendrites 2, and axons 3. Axon 3 can be divided into axonal initial segment 4 (AI) from soma to axonal terminalS), the node of Ranvier 5(node of Ranvier), and the axon terminal, the axon initial segment 4, AIS, is divided into an AIS proximal segment 6, which is close to the soma, and an AIS distal segment 7, which is further away from the soma. It is generally believed by current theory that AIS, i.e. the axon 4, is the trigger region for action potentials for most neurons, although an explosion of neuron action potentials may theoretically occur anywhere in the neuron. The cell membrane at this location has a high density of voltage-gated Na+Ion channels, which have a lower valve potential than other locations, are more easily triggered and burst at action potentials. Excitatory signals from dendrites transmitted by other neurons through synapses are transmitted to soma and axon spreads and integrated in the axon initiation stage, AIS, and when the potential of the integrated excitatory signals reaches or exceeds the valve potential, a large amount of Na is present+The ion channel is opened, producing an action potential burst. After the action potential erupts, the other side is transmitted to the axon terminal, and acts on the next neuron, namely forming the reflex action of the neuron; on the other hand, action potential is transmitted to the soma and dendrite in the reverse direction, acts on postsynaptic membranes distributed on the soma and dendrite, and thus produces STDP synaptic plasticity. After the action potential bursts, the cell membrane is also depolarized, eliminating the residual excitation potential, and waiting for the next new integration process.
According to current theory, the burst of neuronal action potentials is transmitted back to the soma and dendrites, acts on the postsynaptic membranes on the soma and dendrites, and renders these synapses plastic, including synapse-enhancing LTP and synapse-inhibiting LTD. According to the current "synaptic plasticity theory" about learning and memory, synaptic plasticity is the fundamental factor for memory formation, and the learning and memory activities of the brain depend on synaptic plasticity to realize. The method is also the design theoretical basis of simulating learning and memory functions in the simulation technology of the current large polyneurons and neural networks.
And the applicant researches and analyzes different working mechanisms of sodium ion channels of two different subtypes, namely a NaV1.2 subtype and a NaV1.6 subtype, when the neuron explodes the action potential, so as to obtain a more accurate and more complete action potential explosion model of the neuron. The neuron integrates and reacts to dendritic input signals, generally, low threshold action potentials are exploded at the far section of an axon IAS and are transmitted to axon endings in a single direction to form reactive reflex activities to input information, which is a process of information re-acquisition (memory) and a process of brain thinking and reflex activities. The action potential is not transmitted to the soma and dendrite, and the synapse connected with the action potential can not generate synaptic plasticity, so that the stability of the formed memory can not be influenced. In both cases, neurons, through two different generation mechanisms, (corresponding to two cases of "passive memory" and "active memory" formed by the brain), will burst high-threshold action potentials in the cell body or the proximal segment of IAS, and transmit the action potentials to the axon terminal to form information reflection, and at the same time, transmit the action potentials to the cell body and dendrite in the opposite direction to trigger synapse plasticity connected with them, thereby forming memory. Therefore, the acquisition (memory) and re-acquisition (memory) of the information memory are realized by adopting different working mechanisms although the same neuron channel, so that the process of information re-acquisition (also the process of thinking and other reflex activities) can not damage and influence the original memory, and the working condition of the brain is better met. (more detailed analysis details see the specification of the parent application of the present application).
The applicant discloses two neuron simulation devices and methods capable of more perfectly and accurately simulating the neuron working process according to the research and analysis and aiming at different explosion mechanisms and forming processes of action potentials.
Fig. 5 is a schematic block diagram of a first neuron simulation device according to the present invention. The first neuron simulation device comprises a dendrite input end (dendrite input end for simulating neurons), a signal processing module (part for integrating and processing signals by the simulated neurons), and an axon output end (axon output end for simulating neurons); as the prior art, the signal processing module comprises a membrane integration circuit (for simulating the integration process of the excitation potential input to the membrane, an RC charging circuit composed of a resistor and a capacitor is generally adopted to form the membrane integration circuit), a membrane discharge circuit (sometimes also called as a depolarization circuit for simulating the action of depolarization of the membrane potential and forming a refractory period after the excitation integration of the membrane potential is triggered, a switch element is generally adopted to conduct to discharge the capacitor of the membrane integration circuit), a threshold trigger circuit (for simulating the action of the neuron triggering action potential when the excitation integration of the membrane potential reaches a trigger threshold, a voltage comparator circuit is generally adopted, for the purpose of differentiation, the first threshold trigger circuit is called as a first threshold trigger circuit, the trigger threshold is V1), and an action potential pulse generating circuit (an output pulse for simulating the action potential, for the purpose of differentiation, the first action potential pulse generating circuit is called as a first action potential pulse generating circuit), an output circuit for action potential is also included (without substantial analog function, only used for isolating and amplifying action potential pulse signal generated by the action potential pulse generating circuit); the specific connection relation is as follows: the dendrite input end is connected to the input end of the membrane integrating circuit, the output end of the membrane integrating circuit is connected to the input end of the first threshold value trigger circuit, and the output end of the first threshold value trigger circuit is connected to the input end of the first action potential pulse generating circuit; the output end of the first action potential pulse generating circuit is connected to the axon output end through an output circuit; the output end of the first action potential pulse generating circuit is simultaneously connected to the film integration discharging circuit.
The invention is characterized in that: the neuron simulation device further comprises a second threshold trigger circuit, the input end of the second threshold trigger circuit is connected to the output end of the membrane integration circuit, the output end of the second threshold trigger circuit is connected to a second action potential pulse generation circuit, the output end of the second action potential pulse generation circuit is connected to the output end of the axon, and the output end of the second action potential pulse generation circuit is also connected to the input end of the dendrite through a reverse transmission channel. The trigger threshold V2 set by the second threshold trigger circuit is greater than the trigger threshold V1 set by the first threshold trigger circuit. The difference is preferably set to be 10% to 35% larger than V1, depending on the setting of V1 and the integration setting of the film integration circuit.
When the neuron simulation device works, under the ordinary condition, a signal input by a dendrite input end is output after being integrated and integrated by a membrane integrating circuit, when the voltage of an output signal slowly rises to reach a first threshold trigger circuit, the first threshold trigger circuit triggers to enable a first action potential pulse generating circuit to output action potential pulses, the action potential pulses are output to an axon output end through an output circuit, the integration and reflection functions of the input signal are realized, meanwhile, a capacitor of the membrane integrating circuit discharges through a membrane discharging circuit, the next integration processing of the input signal is waited, and the integral output voltage is pulled down to enable a second threshold trigger circuit not to trigger. When the signal input by the dendrite input end is strong, so that the voltage value of the output signal of the membrane integration circuit rises very fast, the first threshold trigger circuit triggers (or approaches to the same time, so that the first threshold trigger circuit has no time to make the membrane discharge circuit pull down the output voltage of the membrane integration circuit), the second threshold trigger circuit also triggers, so that the second action potential pulse generating circuit outputs action potential pulses, and the action potential pulses are output to the axon output end and are simultaneously transmitted to the dendrite input end in a reverse direction, and a spike signal required by synapse STDP plasticity on the dendrite is formed.
The second threshold trigger circuit is used for simulating the first generation reason and biological significance of the neuron outbreak high-trigger-threshold action potential, namely when an excitation signal input by a cell body or dendrite is very strong, the integrated membrane excitation potential rise slope is very steep, so that the high-trigger-threshold action potential is directly outbreaked in a cell body or AIS near-cell body section. The neuron realizes information reflection by bursting action potentials with a lower trigger threshold at the far section of an axon AIS and realizes information memory by bursting action potentials with a higher trigger threshold at the cell body or the near cell body section of the AIS, but the prior art does not perform more accurate simulation on the aspect because the prior art lacks understanding on the importance of the action potentials of the two different subtypes, particularly on the substantial reason of the action potentials of the two different subtypes bursting by the neuron and lacks understanding on which subtype can burst under what conditions, and is particularly important for explaining and simulating how the same neuron works in two different states of reflection and memory.
As an optimized scheme, a signal delay circuit is arranged between the input end of the first threshold trigger circuit and the output end of the membrane integration circuit. So that the output signal of the membrane integrator circuit is delivered to the input of the first threshold trigger circuit with a short delay compared to the time delivered to the input of the second threshold trigger circuit. The delay time is small, depending on the time parameter of the film integration circuit, and generally, it may be between about 5% and 25% of the integration time constant. The signal delay circuit is arranged such that when a strong signal is input at the dendrite input, (i.e. the first instance of a neuron developing a high threshold action potential), the second threshold trigger circuit can reliably trigger before the first threshold trigger circuit. This protocol, when used to mimic transmission of the AIS distal segment from dendritic import and integrated excitatory signals to axons, requires a brief period of time. This short time delay has not been appreciated and simulated by the prior art because the biological significance of the delay was not understood. The applicant notices that the simulation of the time delay can more accurately simulate the integration and transmission of excitation signals input by dendrites, the close relation between the positions of action potential outbreaks and different subtypes of the action potential outbreaks, and the work condition of the brain neurons for generating memory is more consistent with the real work condition of the brain neurons.
As another optimization, the output end of the second action potential pulse generating circuit is also simultaneously connected to the film discharge circuit. The operation of the membrane discharge circuit can be completed by the output of the first action potential pulse generating circuit, but the output ends of the two pulse generating circuits respectively control the membrane discharge circuit, so that the operation process of two action potentials of a neuron can be more met, and the situation that the two action potential pulses are repeatedly superposed can not occur.
Furthermore, the neuron simulation device is also provided with an attention control end for switching the memory/reflex working state (for directly controlling the neuron simulation device to work in the reflex state or the memory state by an external signal); the second threshold trigger circuit is provided with a threshold adjusting circuit and is used for adjusting the voltage trigger threshold of the second threshold trigger circuit to be lower (so that the trigger voltage V2 of the second threshold trigger circuit is smaller than the trigger voltage V1 of the first threshold trigger circuit); and the input control end of the threshold adjusting circuit is connected to the attention control end. When the neuron analog device works, the attention control end can be connected to axon output ends of other neurons and is modulated by excitation activities of the connected other neurons, or the neuron analog device is directly switched between a high level state and a low level state, namely the neuron analog device is directly switched between two working states of information memory and reflection processing. When the attention control end does not input a control signal, the neuron is switched to a reflection working state and works according to the working mechanism; when an effective control signal appears at the input of the attention control end, the neuron is switched to a memory working state, the voltage trigger threshold of the second threshold trigger circuit is adjusted to be lower than the trigger threshold of the first threshold trigger circuit through the threshold adjusting circuit, and when the output signal of the membrane integration circuit is continuously integrated and rises, the second threshold trigger circuit triggers action before the first threshold trigger circuit, so that the second action potential pulse generating circuit outputs action potential pulses which are output to the axon output end and are also reversely output to the dendrite input end to form a spike potential signal required by synapse STDP plasticity on the dendrite. The technical scheme is used for accurately simulating a second generation reason of action potential of a neuron bursting at a high trigger threshold, and the 'attention control end' adjusts the set voltage threshold of a second threshold trigger circuit, so that when the brain is simulated to carry out 'subconscious memory' (namely high attention), the 'attention control end' simulates activation of neurons of a brain control path, and generates a modulation effect of contact transmission (non-synaptic transmission) on cell membrane Na ion channels of a cell body of related neurons or AIS near-cell body segments, so that the cell body or the AIS near-cell body segments can burst the action potential at the high trigger threshold to generate an action potential reverse transmission phenomenon, and therefore synaptic STDP plasticity is generated, and the information memory function is realized. The prior art lacks relevant analog techniques due to the lack of theoretical understanding of the cause of this formation of an explosive high threshold action potential.
As a further improvement, the attention control terminal is also provided with a delay holding circuit of an operating state, and the delay holding circuit is used for keeping the operating state for a certain time. The improvement is used for simulating the neurons of an attention control path, has a certain time holding effect on the modulation effect of the Na ion channel of the neurons of an information processing path, and is more suitable for the working condition of the brain.
Accordingly, a first method for neuron simulation according to the present invention comprises:
⑴, integrating the signal inputted from the dendrite input terminal, (i.e. integrating the signal inputted from the dendrite input terminal by an integrating circuit corresponding to an analog device), ⑵, detecting an integrated voltage signal, (corresponding to detecting the output terminal of the integrating circuit by using two threshold trigger circuits), ⑶, if the voltage signal is less than a set value 1, the neuron does not act, (corresponding to the output voltage of the integrating circuit is less than the trigger voltage V1 of the first threshold trigger circuit, i.e. set value 1), if the voltage signal is equal to or greater than the set value 1 but its rising slope is less than a set value 2, (k is dv/dt, set value 2 is equal to V2/T, where V2 is the trigger voltage of the second threshold trigger circuit, T is the signal delay time of the signal delay circuit applied to the input terminal of the first threshold trigger circuit, generally T is 5% to 25% of the integration set time of the film integrating circuit, and if the voltage signal reaches a set value 1, the integrated circuit outputs a trigger voltage equal to the set value V5635, and the axon output a trigger voltage is equal to the axon output after the trigger voltage reaches a set value 1, and the axon trigger voltage is equal to a trigger voltage V5636, and the axon trigger voltage is equal to zero, if the trigger voltage signal output by the integrating circuit, the axon trigger circuit is equal to the trigger voltage signal output a trigger voltage is equal to the trigger voltage, the axon output terminal, the axon output when the axon trigger voltage is equal to the trigger voltage is equal to a trigger voltage, the trigger voltage is equal to zero, the trigger voltage is equal to the trigger voltage, the trigger voltage of the trigger voltage, the trigger circuit, the trigger voltage is equal to zero trigger voltage of the trigger circuit, the axon trigger circuit, and the axon is equal to zero, the axon is.
Furthermore, the neuron simulation method of the invention also switches two different working states of memory and reflection through the signal state of an attention control terminal (used for controlling the neuron simulation device to work in a reflection state or a memory state through an external control signal), when the signal state of the attention control terminal is in a reflection state, the neuron works according to the simulation method, when the signal state of the attention control terminal is in a memory state, the ⑶ step is changed into that if the voltage signal is less than a set value 1, the neuron does not act, if the voltage signal is equal to or greater than the set value 1, an action potential pulse is triggered to be output to an axon output terminal and reversely output to a dendrite input terminal, equivalently, the attention control terminal reduces a trigger voltage V2 of a second threshold trigger circuit through a threshold adjusting circuit, so that V2 is equal to or slightly smaller than V1, and when the integral voltage reaches V1, the second threshold trigger circuit triggers the action potential to generate an action potential, and the action potential is transmitted to the axon output terminal and the axon output terminal through an integral channel in a reverse direction, and the axon output voltage value is reset at the same time.
Fig. 6 is a specific circuit for implementing the neuron simulation device shown in fig. 5 by using a single chip microcomputer. Wherein, R601 and C601 form a film integration circuit for inputting signals to the dendrite input end, and C601 is a film integration capacitor; the MCU601 is a singlechip, wherein I/O1 is an input end of the first threshold trigger circuit, R602 and C602 form a delay circuit of the input end of the first threshold trigger circuit, and I/O3 is an output end of the first action potential pulse generating circuit; I/O2 is the input terminal of the second threshold trigger circuit, I/O4 is the output terminal of the second action potential pulse generating circuit; the triode T601 forms a film discharge circuit and discharges the C601 when the triode T601 is conducted; t602 and T603 constitute an output circuit of an operation potential; t604 and T605 receive the output of the I/O4, and output the amplified output to the dendrite input end in an inverted way; c603 and R603 form a delay holding circuit of the input signal of the "attention control end", and input the signal to the I/O5, and when the input reaches a certain level amplitude (effective), the trigger threshold of the second threshold trigger circuit is adjusted by the internal threshold adjusting circuit. The MCU601 realizes the generation of threshold trigger and action potential and logic function according to the working principle of the neuron simulation device of fig. 5 and the neuron simulation method of the present invention through its program, which belongs to the technology that those skilled in the art can realize without creativity. For simplicity of the drawing, fig. 6 also does not show other necessary peripheral circuits of the single chip microcomputer but belonging to the conventional technology.
Fig. 7 is another schematic circuit diagram for implementing the neuron simulation device of fig. 5, which does not require a single-chip microcomputer. Wherein R701, C701 constitute a film integrating circuit for inputting a signal to the dendrite input terminal, and C701 is a film integrating capacitance; r702 and C702 constitute an input delay circuit; the IC701 and the IC702 (voltage comparators) constitute first and second threshold trigger circuits; t703, IC703(555 time base circuit) and T704, IC704 form the first and second action potential pulse generating circuit; t705 and T706 constitute an output circuit of the action potential pulse; t701 constitutes a film discharge circuit; c703 and R703 constitute a delay hold circuit for the input signal of the "attention control terminal", and when there is an input signal, the voltage value of the reference voltage at the inverting input terminal of the IC702, which is the second threshold trigger circuit, is pulled down by turning on T702, that is, the trigger threshold of the IC2 is pulled down.
Fig. 8 is a circuit block diagram of a second neuron simulation device according to the present invention. The neuron simulation device also comprises a dendrite input end (used for simulating dendrites), a signal processing module (used for simulating a part of neurons for integrating and processing signals), and an axon output end (used for simulating axons); as the prior art, the signal processing module includes a membrane integration circuit (for simulating the process of integrating the membrane input excitation potential), a membrane discharge circuit (for simulating the action of depolarization of the membrane potential after the action potential triggers and forming a refractory period), a threshold trigger circuit (for simulating the action of the neuron triggering the action potential when the excitation integration of the membrane potential reaches a threshold, for the purpose of distinction, the first threshold trigger circuit is called in the present invention as a first threshold trigger circuit, the trigger threshold is V1), and a first action potential pulse generating circuit (for simulating the output pulse of the action potential), and generally includes an action potential output circuit for isolating the action potential pulse generated by the amplification pulse generating circuit; the specific connection relationship is as follows: the dendrite input end is connected to the input end of the membrane integration circuit, the output end of the membrane integration circuit is connected to the input end of the first threshold trigger circuit, and the output end of the first threshold trigger circuit is connected to the input end of the first action potential pulse generation circuit; the output end of the first action potential pulse generating circuit is connected with the axon output end; the output end of the first action potential pulse generating circuit is simultaneously connected to the film discharging circuit; the invention is technically characterized in that: the neuron simulation device is also provided with an action potential reverse transmission channel; an output terminal of the first action potential pulse generating circuit connected to the dendrite input terminal through the reverse transmission channel; the on-off of the reverse transmission channel is controlled by a reverse transmission control circuit; the control input terminal of the reverse transmission control circuit is connected to an attention control terminal for switching the memory/reflection operation state.
The operation of the neuron simulation device is that the attention control end is adopted to directly switch and control the neuron simulation device between two working states of information memory and reflection processing, namely when the input of the attention control end is effective, namely in a memory state, a reverse transmission control circuit is directly opened, so that when the neuron bursts an action potential, the action potential can be simultaneously reversely transmitted to a dendrite end through a reverse transmission channel, and the synapse device connected to the dendrite can generate synapse STDP plasticity to realize the memory function of information. When the attention control end is in a reflection state, the reverse transmission control circuit is closed, the action potential is only output to the axon without reverse transmission, and therefore only the integration and reflection functions of the input signal are generated without a memory function.
Preferably, a delay holding circuit of working state is arranged between the attention control end and the control input end of the reverse transmission control circuit, and is used for keeping the working state for a certain time. The scheme is used for simulating the neurons of the attention control channel, has a certain time holding effect on the modulation effect of the Na ion channel of the neurons of the information processing channel.
The second neuron simulation device directly controls the action potential reverse transmission channel of the neuron by paying attention to the control end, and simulates the second situation of action potential reverse transmission generated by the neuron, namely the brain realizes memory action through subconscious memory (high attention). On the basis of the above, it is also possible to simulate another situation of the neuron generating reverse transmission of the action potential, that is, when the excitation signal of the dendrite input is very strong, the neuron directly causes the neuron to burst the action potential with high trigger threshold and to reversely transmit the action potential to the soma and the dendrite. To simulate this operation, the neuron simulation device may further comprise a second threshold trigger circuit, an input terminal of the second threshold trigger circuit being connected to an output terminal of the membrane integrator circuit, and an output terminal of the second threshold trigger circuit being connected to a control input terminal of the inverse transmission control circuit. The second threshold trigger circuit is used for simulating a high-threshold action potential exploded by a cell body or an ISA near-cell body segment, so the trigger threshold V2 set by the second threshold trigger circuit is larger than the trigger threshold V1 set by the first threshold trigger circuit. In general, V2 is preferably 10% to 35% larger than V1.
Also, as an optimization of the above, in this case, it is preferable that a signal delay circuit is provided between the input terminal of the first threshold flip-flop circuit and the output terminal of the film integration circuit. This protocol is used to simulate a short time delay in the transmission of the excitatory signal from the dendrite input to the AIS distal segment of the axon, the technical effect and significance of which have been described above.
As another optimization, a trigger delay holding circuit is further arranged between the output end of the second threshold trigger circuit and the control input end of the reverse transmission control circuit. The work is as follows: when the output end of the second threshold trigger circuit generates an output signal, the trigger delay holding circuit is triggered to output a control signal and keeps the output signal for a certain delay time, so that the reverse transmission control circuit is switched on through the output signal and keeps a conducting state within a certain time. The trigger delay time of the trigger delay holding circuit should be slightly longer than the pulse width of the action potential generated by the action potential pulse circuit, so that the reverse transmission process of the action potential pulse is more complete and reliable.
Accordingly, a second neuron simulation method of the present invention includes:
⑴, integrating the signal inputted from the dendrite input end, (i.e. integrating the signal inputted from the dendrite input end by an integrating circuit corresponding to the analog device), ⑵, detecting the integrated output voltage signal, (corresponding to the detecting of the output end signal of the integrating circuit by a first threshold trigger circuit), if the voltage signal is less than a set value 1, no action is generated, (corresponding to the detecting of the output voltage of the integrating circuit is less than the trigger voltage V1 of the first threshold trigger circuit, at this time, the first threshold trigger circuit does not trigger action), ⑶, if the integrated voltage signal is greater than the set value 1, (corresponding to the detecting of the output voltage of the integrating circuit is greater than the trigger voltage V1 of the first threshold trigger circuit), detecting the signal state of the 'attention control end';
if the signal state of the attention control end is a reflection state (for example, low level 0), the neuron works in a reflection mode, the neuron triggers to generate an action potential pulse and outputs the action potential pulse to an axon output end, (which is equivalent to the triggering of a first threshold trigger circuit, and the first action potential pulse circuit generates an action potential and transmits the action potential to the axon output end), and meanwhile, the integrated voltage signal value is cleared; (corresponding to the operation of the film discharge circuit, the film integration circuit of the capacitor discharge);
if the signal state of the attention control end is a memory state (such as high level 1), the neuron works in a memory mode (corresponding to that the reverse transmission control circuit is opened and conducted), and the neuron triggers to generate an action potential pulse which is output to the axon output end and reversely output to the dendrite input end; (equivalent to the triggering of a first threshold trigger circuit, a first action potential pulse generating circuit generates action potentials which are transmitted to an axon output end and a dendrite input end through a reverse transmission circuit at the same time), and the integrated voltage signal value is cleared; (corresponding to the operation of the film discharge circuit, discharging the film integrator circuit capacitance).
Also as an optimization, the attention control terminal is further provided with a delay holding circuit in an operating state, and the delay holding circuit is used for keeping the operating state for a certain time, and then the signal state of the attention control terminal is changed into the state of the output terminal of the delay holding circuit. The improvement is used for simulating the neuron of an attention control channel, and has a certain time holding effect on the modulation effect of the Na ion channel of the neuron of an information processing channel.
The second neuron simulation method is a working mode of directly controlling the switching neuron through an attention control terminal, and is a second condition of generating action potential reverse transmission of a simulation neuron, namely the brain realizes memory action through subconscious memory (namely high attention). On the basis, another situation that the neuron generates reverse transmission of the action potential can be simulated at the same time, namely when the excitation signal input by the dendrite is very strong, the neuron directly explodes the action potential with a high trigger threshold and reversely transmits the action potential to the soma and the dendrite. Then, the simulation method further comprises the following steps:
⑷, detecting the integrated voltage signal, if the voltage signal is greater than the setting value 1 and the voltage rising slope is greater than the setting value 2, (the voltage rising slope k is dv/dt, the setting value 2 is equal to V2/T, wherein V2 is the trigger threshold of the second threshold trigger circuit, T is the signal delay time of the signal delay circuit applied to the input end of the first threshold trigger circuit, this condition is equivalent to the output voltage of the integration circuit is greater than the trigger voltage V1 of the first threshold trigger circuit, and the trigger voltage V2 of the second threshold trigger circuit is reached or exceeded within the setting time T, the neuron operates in a memory mode, (which is equivalent to the second threshold trigger circuit outputting the trigger signal, making the reverse transmission control circuit open and conduct), the neuron triggers to generate an action potential pulse, which is output to the axon output end and is equivalent to the reverse output to the axon output end, the action potential pulse is equivalent to the axon output end and is also equivalent to the dendrite discharge circuit, (which is equivalent to the action potential pulse circuit generating the action potential to the axon discharge circuit, which is equivalent to the dendrite discharge circuit.
Fig. 9 is a specific circuit for implementing the neuron simulation device shown in fig. 8 by using a single chip microcomputer. Wherein R901, C901 constitute a film integrating circuit for inputting signals to the dendrite input terminal, and C901 is a film integrating capacitance; the MCU901 is a single chip microcomputer, wherein I/O1 is an input terminal of the first threshold trigger circuit, R902 and C902 form a delay circuit of the input thereof, and I/O3 is an output terminal of the first action potential pulse generating circuit; I/O2 is the input of the second threshold trigger circuit, I/O4 is the output of the trigger delay hold circuit; t901 constitutes a film discharge circuit; t905 and T906 constitute an output circuit of the action potential pulse; c903 and R903 form a delay holding circuit of an input signal of an attention control end; t904 constitutes a reverse transmission control circuit for performing on-off control of an action potential signal from a reverse transmission channel of the output circuit; t902 receives control of an attention control terminal, T903 receives output control of I/O4, and on-off of T904 is controlled at the same time.
Fig. 10 is a schematic diagram of another circuit for implementing the simulation apparatus of fig. 8, which does not require a single-chip microcomputer. Wherein R101, C101 constitute a film integration circuit; r102 and C102 form an input delay circuit; the IC101, IC102 (voltage comparator) constitute first and second threshold trigger circuits; t103 and IC103(555 time base circuit) form a first action potential pulse generating circuit; t104 and IC104 form a trigger delay holding circuit; t105 and T106 constitute an output circuit of the action potential pulse; t101 constitutes a film discharge circuit; t107 forms a reverse transmission control circuit; c103 and R103 constitute a delay holding circuit for an input signal of the "attention control terminal", and T107 is turned on by T102 when a signal is input. T102 is also controlled by IC104, and when there is an output, T107 is turned on by T102 to open the reverse transmission channel of the operation potential.
As a further improvement to the above-mentioned two neuron simulation devices or simulation methods of the present invention, the neuron simulation devices are both further provided with a modulated synapse input circuit and a modulated synapse input terminal; the modulating synapse input is connected to an input of a modulating synapse input circuit, an output of which is connected to an output of the membrane integration circuit. The modulating synaptic input circuit includes two aspects: an enhanced synapse input circuit and an enhanced synapse input thereof, and an inhibitory synapse input circuit and an inhibitory synapse input thereof. These modulation input circuits enable the neuron simulation device to have an axon-axon type synaptic input function for modulating information processing, in addition to a dendrite input terminal for inputting an excitatory signal. Note that the input signal of the present invention is not connected to the input terminal of the membrane integrator circuit, so that it does not directly participate in the integration of membrane potential and can directly trigger action potential like the excitatory signal of dendrite input, but is connected to the output terminal of the membrane integrator circuit, and a modulation voltage is formed to enhance or suppress the membrane integration output voltage, and the influence on the membrane integration output voltage is used to modulate whether the excitatory signal input from dendrite and integration can trigger action potential. This function facilitates the construction of a multi-channel multi-information inter-modulated complex neural network to simulate the effects of experience or mood (happiness, fear, treats, addiction, etc.) on the processing of neuronal information.
Fig. 11 is a circuit schematic of a modulatory input circuit. The circuit shows only the added portion of the modulation circuit, i.e., the portion that can be added to the circuit of the neuron simulation device of fig. 6, 7, 9 or 10, where the film integration capacitance CX is also the integration capacitance in the film integration circuit of each circuit, e.g., C601 of fig. 6. A signal at the enhanced modulation input end is subjected to resistance voltage division and then input to an input end of an inverter F111 (a digital gate circuit), when an input signal is effective, the inverter F112 outputs positively, after the voltage division is carried out through resistors R111 and R112, a capacitor C111 is charged through D111, so that two ends of the capacitor reach a certain voltage (generally, the voltage can be one third to one half of a trigger voltage of a first threshold trigger circuit), the voltage is discharged through R113 on one hand (the discharge time is also approximately equal to the effective time of modulation), and on the other hand, the voltage is added to a film integration capacitor CX through R114 and D112, so that the film integration capacitor has a certain initial voltage; when the voltage of the film integrating capacitor exceeds the initial voltage, the voltage of the film integrating capacitor cannot be influenced due to the unidirectional action of the diode D112. Therefore, when a pulse signal is input to the dendritic input end, the voltage on the membrane integrating capacitor can more easily reach the trigger voltage of the threshold trigger circuit, so that the action potential is more easily triggered and generated, and the aim of enhancing modulation is fulfilled. The operation of the inhibitory modulation is similar, but a lower voltage generated on the capacitor C112 does not generate an initial voltage for the film integrating capacitor due to the reverse action of D114, and when the voltage of the film integrating capacitor is higher, a shunt is formed by D114 and R118 instead, so that the voltage of the film integrating capacitor does not easily reach the trigger voltage, and the threshold trigger circuit does not easily trigger, thereby achieving the purpose of the inhibitory modulation.
The synapse simulation device working in accordance with the present invention may employ various simulation devices capable of sufficiently simulating the working characteristics of chemical synapses in the prior art, or may employ synapse simulation techniques disclosed below in the present invention.
Applicants have analyzed that in brain neural networks, there are at least three different types of neurosynaptic: the first is a relatively stable synapse with only short-term synaptic plasticity, including synaptogenic (synaptogenic), synaptogenic suppression (synaptic suppression), posttonic potentiation (PTP), but does not exhibit long-term synaptic plasticity (or it can achieve synaptic plasticity but does not exhibit synaptic plasticity under the current working state), they exist in the incoming and outgoing of various signals and other direct and stable signal transmission paths (such as in unconditional reflex loops), the transmission efficiency is strong and stable, when a pre-synaptic neuron is activated, it is often able to trigger a post-synaptic neuron to generate an action potential by a strong and effective transmission efficiency, (some may also be single-synaptic transmission, i.e. a single synaptic signal is sufficient to activate a post-synaptic neuron), which is referred to herein as "stable synapse". The second is the obvious long-term synaptic Plasticity, including long-term potentiation (LTP) and long-term suppression (LTD), which has the time-Dependent nature of the Spike behind the presynaptic membrane and synapse (Spike Timing-Dependent Plasticity, STDP). The synapses are widely present in hippocampus, striatum, amygdala and partial cortex of brain, and have important significance for realizing information learning and long-term memory, and the simulation technology disclosed for the synapses is the most, and the synapses are called as plastic synapses in the invention. The third type of synapse has not been recognized and fully appreciated, and therefore has no associated simulation techniques. Although the physiological shape with synapses is generated, the synapses have no normal synaptic transmission efficiency temporarily, and need to be stimulated by multiple related neurons before and after the synapses to initiate and form effective synaptic transmission efficiency, (wherein gene transcription and protein synthesis should also be initiated), and the synapses exist at least on cerebral cortex, especially neocortex for processing high-level information, and have important significance for realizing long-term memory of declarative information. Moreover, applicants further speculate from the macroscopic characterization of information memory that even if effective synaptic transmission efficacy has been initiated and developed, if not stimulated for a long time, (without use in thinking or without remembrance), these synapses may still lose some synaptic substances (such as proteins) due to competition by other synapses, resulting in synaptic failure again. This third synapse is referred to herein as the "Preset synapse". With regard to these three synapses, in particular where the "plastic synapses" and the "preset synapses" have different roles and are transformed into each other in memory, long-term memory and permanent memory, reference may be made to the contents of the following "different and transformed" parts of working memory, long-term memory (hippocampal memory) and long-term (permanent) memory.
For the three synapses, the present invention employs three techniques to achieve the simulation of these synapses.
The circuit of the "solidified synapse" simulation device of the present invention is shown in FIG. 12. The solidifying synapse simulating device comprises a front membrane input end and a rear membrane output end, and is characterized in that; a capacitor discharge circuit is connected in series between the front film input end and the rear film output end, and the capacitor discharge circuit is connected with a capacitor discharge circuit in parallel. Therefore, the simplest synaptic transmission channel with fixed synaptic transmission efficiency, namely, the synaptic transmission channel without synaptic plasticity, is formed. As a simplest scheme, the capacitor discharge circuit is composed of a discharge capacitor C801, the front end of the discharge capacitor is connected with the front film input end, and the rear end of the discharge capacitor is connected with the rear film output end through a transfer resistor R801; the capacitance bleeder circuit is used for slowly discharging the charge of the discharge capacitor, and comprises bleeder resistors R802 and R803 and a diode D801; the bleeder resistor R802 is connected between the front end of the discharge capacitor C801 and ground (i.e., the common ground of the circuit); the diode D801 is connected in series with another resistor R803 and then reversely connected between the rear end of the discharge capacitor and the ground. Diode D802 is used to provide unidirectional isolation of the input so that signal changes at synapses do not affect other circuits in front of the front membrane input. The transmission resistance R801 is used to set the magnitude (weight) of the transmission performance of the synapse, which is different in different information processing channels of the brain, for example, the transmission performance of the synapse is larger in the input/output circuit of information, even a single synapse single pulse is enough for the next neuron to generate an action potential burst, and the transmission performance of the synapse in the interneuron is smaller, which generally requires spatial integration of multiple synapses or temporal integration of a single synapse to trigger the next neuron burst action potential. A diode D803 is connected in reverse parallel with the resistor 801, and the diode D803 is used for providing a special path for reversely charging the capacitor C801 for the action potential pulse from the postsynaptic membrane output end. Varying the resistances R802 and R803 may change the rate at which the capacitance discharges, i.e., change the degree to which synapses inhibit low frequency action potential suppression phenomena. When the device works, if low-frequency action potential pulses are input at the input end of the front film, due to the action of the capacitor C801, after each action potential pulse passes through, a period of time is needed for the capacitor to discharge through a bleeder circuit formed by the diode and the resistor, so that the recovery can be realized. If two or more low frequency pulses are continued, the capacitor will be charged and discharged too soon, and will present a larger impedance to the next second pulse, i.e. a phenomenon that synapse transmission will produce synaptic inhibition to the low frequency action potential. If the high-frequency sharp pulse is input at the input end of the front film, the influence is small because the impedance of the capacitor to the high-frequency sharp pulse is small. Particularly, if the high-frequency action potential can cause neuron integration of the postsynaptic membrane to burst a V1.2 subtype action potential with a high threshold, since the action potential is reversely transmitted to the postsynaptic membrane, the capacitor C801 is reversely charged through the diodes D803 and R802, so that the C801 presents a significantly enhanced transmission efficiency to the next action potential pulse, that is, the synapse transmission generates a synapse enhancement phenomenon to the high-frequency action potential.
The solidified synapse simulation device adopts an extremely simple circuit to realize the synapse transmission function of the common synapse, although synapse inhibition and synapse enhancement are only simple and rough simulation, the solidified synapse simulation device has the characteristics of extremely simple circuit, extremely low cost and extremely low volume, can be applied to signal input and output channels, signal feedback channels and other signal direct transmission channels in a simulated neural network, and can obviously save the cost when the scale of the simulated neural network is large.
With respect to synaptic STDP plasticity, the current theory holds that the STDP characteristic of synaptic plasticity, i.e., the efficiency of synaptic transmission, is related to the timing of action potential spikes of pre-and post-synaptic neurons, as shown in FIG. 13, if the pre-synaptic neuron spike Vpre generates a time tpre earlier than the post-synaptic neuron spike Vpost, i.e., △ t ≧ 0, a long-term potentiation (LTP) phenomenon occurs, and the smaller the spike delay, i.e., △ t, the greater the LTP effect of the enhanced LTP effect of synaptic transmission, (for descriptive purposes, we may refer to this as having LTP characteristics for its spike signal), whereas if the pre-synaptic neuron spike is slower than the spike of the synaptic neuron, the smaller the long-term suppression (LTD) phenomenon occurs, and the larger the delay of synaptic transmission of the spike signal, the greater the LTD characteristics of synaptic transmission, the greater the LTD signal of synaptic transmission, and the LTD characteristics of the LTD signal of the post-spike transmission.
A plurality of techniques have been disclosed in the prior art for modeling synapses with plasticity, including the recent use of memory varistor materials to directly fabricate plastic synapses, which is obviously more convenient. The basic circuit for simulating a plastic synapse by using an electronic circuit is shown in fig. 14, and generally includes a front film input end, a rear film output end, an STDP timing identification circuit, an STDP operation circuit, and a synapse transmission performance adjustment circuit, where the STDP timing identification circuit can identify and determine whether a spike signal thereof has an STDP characteristic and belongs to an LTP characteristic or an LTD characteristic according to spike signals appearing at the front film input end and the rear film output end, signals of the two characteristics are output to the STDP operation circuit for addition and subtraction accumulation, an output value after the operation is used for controlling the synapse transmission performance adjustment circuit, and the transmission performance adjustment circuit adjusts a value of the synapse transmission performance (i.e., strength of a synapse output signal) so as to implement a plastic change of the synapse transmission output signal, that is, i.e., implement synapse plasticity. In the prior art, the functions of the STDP timing identification circuit, the STDP operation circuit and the synapse transmission performance adjustment circuit are realized by a program mostly using a microprocessor. The invention discloses another simulation method and device.
Refer to fig. 15. The simulation method of the plastic synapse with the synapse transmitting STDP plasticity function comprises the following steps:
⑴, controlling the output signal of the back membrane output end by the input signal of the pre-synaptic membrane input end to synchronize the output signal with the input signal, ⑵, detecting the spike potential signals of the pre-synaptic membrane input end and the back membrane output end, ⑶, when recognizing that the spike potential signal conforming to the STDP characteristic appears between the front membrane input end and the back membrane output end, charging and discharging a storage device through a charging loop and a discharging loop according to the signal characteristic, if the signal is the LTP characteristic, charging is carried out, if the signal is the LDP characteristic, discharging is carried out, the time width of charging or discharging is determined by the STDP characteristic, ⑷, adjusting the magnitude of the voltage (or current) amplitude of the synaptic output signal by the voltage value of the storage device and outputting the voltage to the back membrane output end, ⑸, and the storage device is set with an initialization voltage with a certain value when starting to work.
As an optimization, when the voltage on the storage device is greater than or less than the initialization voltage, the voltage difference is slowly eliminated by a bidirectional bleeder circuit until the voltage on the storage device is equal to the initialization voltage. (this approach mimics the slow elimination of synaptic LTP and LTD effects, making the synaptic simulation method of the invention more complete).
As in fig. 15. The invention relates to a 'plasticity synapse' simulation device with a synapse transmission STDP plasticity function, which comprises a front membrane input end, a rear membrane output end, an STDP time sequence identification circuit and a transmission efficiency adjusting circuit. The STDP time sequence identification circuit belongs to the prior art, and can identify and judge whether a spike potential signal has STDP characteristics or not according to spike potential signals appearing at a front film input end and a rear film output end, and identify and judge whether the spike potential signal belongs to LTP characteristics or LTD characteristics. In addition, the STDP timing sequence identification circuit detects the voltage value of the signals input by the front membrane input end and the rear membrane output end, and the voltage value of the action potential spike is obviously larger than the voltage value of the signals transmitted by the synapse, so the STDP timing sequence identification circuit only identifies the action potential spike with higher voltage amplitude, and the synapse output signals generated by the synapse and the synapse output signals of other synapse devices transmitted by the rear membrane output end cannot be identified due to lower signal voltage amplitude. The STDP time sequence identification circuit can adopt a CPU or MCU or other microprocessors to perform analog-to-digital conversion on spike potential signals at the input end of the front film and the output end of the rear film, and then identify and output LTP characteristic signals and LTD characteristic signals according to the time sequence and time difference. Or a voltage comparator and a time base circuit can be adopted to identify and output the LTP characteristic signal and the LTD characteristic signal through logic according to the time sequence and time difference of the spike potential signal. This is the prior art, and there is a related art in disclosing synapse simulation techniques implemented with electronic circuits with synapse-transferring STDP plasticity. Moreover, the operational features and implementation techniques described herein with respect to the STDP timing identification circuit are equally applicable in other portions of the present invention.
The method is characterized in that: the STDP time sequence identification circuit is provided with an LTP output end and an LTD output end; (the STDP timing sequence identification circuit controls the output signals of the LTP output end and the LTD output end according to the time sequence of the appearance of the spike potentials at the front film input end and the rear film output end); the LTP output and the LTD output are each connected via a charging circuit and a discharging circuit to an energy storage device for storing electrical energy. When the STDP time sequence identification circuit identifies the LTP characteristics, LTP pulse output appears at an LTP output end, the pulse width of the LTP pulse is in negative correlation with the time interval of two front and back spike potential signals, namely the LTP pulse accords with the STDP characteristics, and the LTP pulse charges the storage device through the charging circuit to enable the voltage at two ends of the storage device to rise (representing the improvement of synapse transmission efficiency); when the STDP time sequence identification circuit identifies the LTD characteristics, LTD pulse output appears at the LTD output end, the pulse width of the LTD pulse is in negative correlation with the time interval of the front spike potential signal and the rear spike potential signal, and the LTD pulse discharges the electric storage device through the discharge circuit to enable the voltage at two ends of the electric storage device to be reduced (representing the reduction of the synaptic transmission efficiency). The storage device may be a capacitor with very low leakage current, or other small capacity storage device.
The device is connected with an initialization charging circuit; (the initialization charging circuit is used to rapidly charge the storage device to an initialization voltage when the circuit starts to work, and has an initial charge amount, so that synapses have an "effective" transmission efficiency in an initial state, and the initialization voltage is a reference voltage of the storage device when no synapse plasticity occurs, and the synapse output is a standard synapse transmission efficiency). As a specific scheme, the initialization charging circuit includes a voltage stabilizing circuit, the charging output voltage of the voltage stabilizing circuit is equal to the initialization voltage of the electric storage device, the voltage stabilizing circuit is connected to the electric storage device through a unidirectional fast charging loop, when the circuit starts to work, the voltage stabilizing circuit charges the electric storage device fast through the fast charging loop, so that the voltage of the electric storage device reaches the initialization voltage, namely the reference voltage, fast, and then the fast charging loop is closed.
The output of the power storage device is connected to the synaptic transmission efficiency adjusting circuit as the reference voltage of the output of the power storage device, and the synaptic transmission efficiency adjusting circuit is synchronously controlled by the input signal of the input end of the front membrane. Thus, the output signal of the transmission efficiency adjusting circuit is modulated by the output voltage of the electric storage device in amplitude, the magnitude of the output voltage of the electric storage device determines the magnitude of the voltage amplitude of the output signal, namely determines the magnitude of synaptic output efficiency, and is synchronously controlled by the input signal of the input end of the front membrane in time; the output signal of the transmission efficiency adjusting circuit is connected to the output end of the posterior membrane as a synaptic signal output. The output terminal of the "solidified synapse" simulation device may further comprise a circuit of the "solidified synapse" simulation device, so that the circuit has the transmission characteristics of synapse enhancement and synapse inhibition.
The simulation method and device of "plastic synapse" of the invention, the transmission characteristic of the chemical synapse with synapse plasticity is simulated, but it is different from the method of the prior art which generally adopts the method of changing the circuit transmission impedance (varistor circuit) to realize the transmission efficiency, but the STDP time sequence identification circuit is used to identify the LTP and LTD characteristics, and the charging circuit and the discharging circuit are used to charge and discharge an accumulator device, so that the voltage on the accumulator device generates high and low changes along with the charging (LTP time) and discharging (LTD time), and is used to modulate the output of the synapse efficiency adjusting circuit, thereby the voltage value of the synapse output pulse generates the corresponding adjustment of high and low, thereby realizing the simulation of the STDP synapse plasticity.
As an optimization, the electric storage device is also connected with a bidirectional bleeder circuit; the bidirectional bleeder circuit is used for slowly eliminating the voltage rising or voltage falling change of the storage device caused by charging and discharging in a certain time until the voltage on the storage device is equal to the initialization voltage. Therefore, the slow elimination of the synapse LTP and LTD effects is simulated, so that the synapse simulation device is more perfect and can be suitable for continuous multi-process simulation work. As a simple and ingenious scheme, the bidirectional bleeder circuit comprises a voltage stabilizing circuit with a set voltage, wherein the set voltage of the voltage stabilizing circuit is equal to the initialization voltage of the electric storage device, namely the reference voltage of the electric storage device when plasticity does not appear, and at the moment, synapse transmission is standard transmission efficiency; when the voltage of the storage device is smaller than the stabilized voltage set voltage, namely the synapse LTD effect occurs, the voltage stabilizing circuit slowly charges the storage device through the resistor, namely the LTD effect is slowly eliminated. After a certain time, namely after the effective period of synapse plasticity, the voltage on the electric storage device is equal to the set voltage of the voltage stabilizing circuit, namely the normal output pulse amplitude when no synapse plasticity occurs.
FIG. 16 is a circuit implementing the "plastic synapse" simulation apparatus of FIG. 15. The MCU1601 is used for identifying the STDP spike and outputting LTP and LTD signals. Signals from the front film input terminal and the rear film output terminal are input to the I/O1 and the I/O2, and the MCU1601 recognizes whether the LTP effect or the STD effect, and the intensity of the effect thereof, are included according to the timing relationship between the two signals from the front film input terminal and the rear film output terminal (as shown in fig. 13), and outputs them through the I/O3 and the I/O4. When LTP effect occurs, the I/O3 outputs a positive level, the output pulse width is in positive correlation with the intensity of the LTP effect, and the D1602 and the R1602 charge a capacitor C1601 which is an electric storage device to enable the voltage of the electric storage device to rise; when the LTD effect occurs, the I/O4 outputs a negative level, the output pulse width is in positive correlation with the intensity of the LTD effect, and the D1601 and the R1601 discharge to a capacitor C1601 which is an electric storage device, so that the voltage of the electric storage device is reduced; while no LTP or STD effects are present, then I/O3 and I/O4 have no active outputs (floating or outputting opposite levels). Thus, the voltage on capacitor C1601 changes with LTP and LTD effects of the front and rear film output signal STDP spikes.
T1601, D1603, C1602, and the like constitute an initialization charging circuit. D1603 forms a voltage stabilizing circuit, and the stabilized output voltage is equal to the initialization voltage of the electric storage device C1601, namely, the reference voltage; t1601, C1602, etc. constitute a unidirectional quick charge circuit, are connected to C1601, and when the circuit starts the energization operation, the quick charge circuit is turned off until the next circuit restart to quickly charge C1601 to a reference voltage. R1604, D1604, R1605 and the like form a bidirectional bleeder circuit; wherein R1604 and D1604 form a voltage stabilizing circuit, the voltage stabilizing value is equal to the reference voltage, and the voltage stabilizing value is connected to the electric storage device C1601 through R1605; when the voltage of the C1601 is larger than the reference voltage, the C1601 slowly discharges to the voltage stabilizing circuit through the R1605, and the LTP effect is slowly eliminated; when the voltage of the C1601 is smaller than the reference voltage, the voltage stabilizing circuit charges the C1601 slowly through the R1605, that is, the LTD effect is eliminated slowly.
The voltage of the storage device C1601 is isolated through an operational amplifier IC1601 forming a follower circuit and then connected to an analog switch K1601, the switch of the K1601 is controlled by a signal of a front film input end, when a pulse signal, namely an action potential signal, appears at the front film input end, the K1601 is synchronously opened to output a synchronous pulse signal, the voltage amplitude of the pulse signal is equal to the voltage amplitude of the C1601, namely a pulse output signal with STDP plasticity effect. In the present embodiment, the output of K1601 is also provided with a network formed by R1606, R1607, R1608, D1605, and C1603 for further simulating the short-term synaptic inhibition effect, and the operation principle thereof can refer to the analysis of the circuit of fig. 12.
The method for simulating the preset synapses comprises ⑴, presetting a synapse transmission channel between a front membrane input end and a rear membrane output end of the synapse, closing the operation of the synapse transmission channel when the synapse transmission channel starts to operate, ⑵, detecting spike potential signals of the front membrane input end and the rear membrane output end, ⑶, calculating the occurrence condition of the signals (including integration or counting) when the spike potential signals meeting the STDP characteristic appear between the front membrane input end and the rear membrane output end, and ⑷, starting the preset synapse transmission channel to operate when the occurrence condition of the spike potential signals meeting the STDP characteristic meets a set rule, so that a transmission channel with the synapse transmission efficiency is established between the front membrane input end and the rear membrane output end of the synapse.
The predetermined synaptic transmission channel is a synaptic transmission channel with synaptic transmission characteristics including one or more of synaptic facilitation, synaptic inhibition, postsynaptic enhancement, synaptic long-term plasticity, especially synaptic plasticity with STDP characteristics, and the like. In other words, the predetermined synapse-transmitting channel of the present invention is essentially a prior art synapse-simulating device with transmitting properties, which may be the above-mentioned "fixed synapse" device, the above-mentioned "plastic synapse" device, or other prior art synapse-simulating devices.
The setting rule is one of the following two types: 1. counting the number of times of signals according with the LTP characteristics in the STDP characteristics, and starting the work of a preset synapse transmission channel if the number of times of the LTP reaches a set value within a set time; or 2, counting the times of the signals according with the LTP characteristics and the LTD characteristics without setting counting time, wherein the times of the signals with the LTP characteristics are added, and the times of the signals with the LTD characteristics are subtracted; and if the total count reaches a set value, starting the work of a preset synapse transmission channel.
In a further improvement, the method for simulating the preset synapse of the present invention further comprises:
⑸, after the preset synapse transmission channel is started, continuously detecting spike potential signals of the pre-synaptic membrane input end and the post-synaptic membrane output end, ⑹, calculating the occurrence condition of the signals when the spike potential signals which accord with the STDP characteristic appear between the current membrane input end and the post-synaptic membrane output end, and closing the preset synapse transmission channel to cut off the transmission channel of the pre-synaptic membrane input end and the post synaptic membrane output end when the occurrence condition of the spike potential signals which accord with the STDP characteristic meets a second set rule.
The second setting rule is one of the following two rules: 1. counting the number of times of signals according with the LTD characteristics, and if the number of times of the LTD reaches a set value within a set time, closing the work of a preset synapse transmission channel; 2. counting the times of the signals according with the LTP characteristics and the LTD characteristics at the same time, wherein the times of the signals with the LTP characteristics are added, and the times of the signals with the LTD characteristics are subtracted; and if the total count is lower than the set value, closing the operation of the synaptic transmission channel. It is obvious that in this latter setting rule, the setting value of the total count for closing the synaptic transmission channel is necessarily smaller than the setting value of the total count for starting the synaptic transmission channel.
As in fig. 17. The invention relates to a simulation device of a preset synapse, which comprises a front membrane input end, a rear membrane output end and a synapse transmission channel with synapse transmission efficiency; the method is characterized in that: the STDP time sequence identification circuit is used for identifying a spike potential signal with STDP characteristics between the front film input end and the rear film input end; the output of the STDP timing sequence identification circuit is connected to an STDP integrating circuit, and the output of the STDP integrating circuit is connected to a threshold control circuit; the output end of the threshold control circuit is connected to a channel switch circuit; the channel switch circuit is used for controlling the connection and disconnection of the synapse transmission channel.
The working principle and the process are as follows: when the STDP integrating circuit works, the STDP integrating circuit accumulates the signals which are identified and output by the STDP timing sequence identification circuit within a certain time according to a set rule and converts the signals into output values of the output signals; the threshold control circuit is used for detecting the output value of the output signal of the integrating circuit, and when the output value of the integrating circuit reaches or is higher than a set threshold 1, an output control signal is generated; and starting to connect the synaptic transmission channel through the channel switch circuit, and establishing the synaptic transmission channel with synaptic transmission efficiency between the front membrane input end and the rear membrane output end.
The working process further comprises the following steps: after the channel switch circuit starts to connect a synapse transmission channel, the threshold control circuit continuously detects the output value of the output signal of the integrating circuit, and when the output value of the integrating circuit is lower than a set threshold 2, the output control signal is closed; and closing the synaptic transmission channel through the channel switching circuit. I.e. to cut off the synaptic transmission channel between the anterior membrane input and the posterior membrane output. Obviously, the set threshold 2 needs to be smaller than the set threshold 1, and as a more reasonable setting, it can generally correspond to 65% to 85% of the value of the set threshold 1.
Similarly, the predetermined synaptic transmission channel is a synaptic transmission channel with synaptic transmission characteristics.
The setting rule of the integration circuit is as follows: the output value of the output signal is increased when the signal of the LTP characteristic occurs, and the output value of the output signal is decreased when the signal of the LTD characteristic occurs. (compared with the simulation method, the simulation device only adopts one mode of the operation rule of the STDP, wherein the operation rule is closer to the brain working characteristic).
Compared with the synapse simulation technology with synapse transmission STDP plasticity in the prior art, the simulation method and the simulation device for the preset synapse have different processing although the technology for detecting and identifying STDP characteristic spike signals between presynaptic and postsynaptic membranes is adopted. The conventional STDP synapse simulation technique initially has synaptic transmission efficiency, and then adjusts the synaptic transmission efficiency according to the detection of the identified spike signal conforming to the STDP characteristic: if the LTP characteristic signal appears, the synaptic transmission efficiency is improved, and if the LTD characteristic signal appears, the synaptic transmission efficiency is reduced, so that the synaptic transmission plasticity is realized. From the perspective of brain architecture, this class of synapses is more localized among neurons in the amygdala, striatum, hippocampus, etc. regions for short-term and long-term memory of declarative information.
The presupposed synapses of the present invention may comprise a synapse-transmitting channel with synapse-transmitting capability, i.e., the presupposed synapses may comprise a synapse-simulating device of the prior art, and may be based on the synapse-simulating device of the prior art, and a technique for identifying, determining, activating or deactivating the synapse-simulating device. When the presupposition synapse transmission channel is in an initial working state, the presupposition synapse transmission channel is closed, so that no synapse transmission efficiency exists at first, and only when spike potential signals which accord with LTP characteristics in STDP characteristics appear between the current membrane input end and the rear membrane output end for many times and are accumulated to a certain degree, the channel switch circuit starts the work of connecting the synapse transmission channel, so that the presupposition synapse pre-membrane input end and the rear membrane output end have effective synapse transmission efficiency. It mimics a synapse between neurons in the brain cortex, etc., which initially does not have synaptic transmission efficiency, and requires multiple long-term co-stimulation of both neurons before and after the synapse is formed, before it is activated into an effective synapse, and once activated, its transmission efficiency is relatively stable. Such synapses are typically found in areas such as the cerebral cortex for long-term memory of declarative information.
The STDP integrator circuit will increase in value until it reaches a maximum value, i.e., the synaptic transmission efficiency will increase until it reaches a maximum value, either by spike signaling or by activation of presynaptic neurons by synaptic transmission through it to generate action potentials (which in practice generate LTP signatures). Only when the LTP characteristic does not appear for a long time and the inhibitory signal of the LTD characteristic appears for a plurality of times, the numerical value of the integrating circuit is slowly reduced and is finally lower than the threshold value, the threshold control circuit closes the output signal, and the channel switch circuit closes the synapse transmission channel to ensure that the synapse fails again. Even if such an operating state is used to simulate the storage of information as long-term memory by neurons in the brain, if such information is not used for a long period of time and there is long-term confusion (competition) with other inhibitory information, the long-term memory is slowly forgotten.
In the preset synapse simulation device, an STDP time sequence identification circuit belongs to the prior art, and how an STDP integration circuit operates LTP and LTD characteristic signals output by the STDP time sequence identification circuit, a microprocessor such as an MCU (microprogrammed control unit) can be generally adopted to count the LTP characteristic signals and the LTD characteristic signals according to the set rule, then the count value is compared with the set value, a control signal is output according to the comparison result, and the on-off of a channel control circuit of a synapse transmission channel is controlled. That is, the same single-chip microcomputer can be used to simultaneously complete the functions of the timing sequence identification circuit, the STDP integration circuit and the threshold control circuit, so that the hardware part is very simple and is not shown here. For the programs of the single chip microcomputer, the technical personnel in the field can conveniently write the programs according to the principle and the operation rule disclosed by the invention.
Referring also to the foregoing simulation technique of "plastic synapses" of FIG. 15, another technique is disclosed for implementing a "preset synapse" simulation apparatus for an STDP integration circuit using a storage device. The circuit block diagram is shown in fig. 18. The STDP integrating circuit is realized by adopting a charging circuit, a discharging circuit and an electric storage device, and an LTP output end and an LTD output end of the STDP timing sequence identification circuit are respectively connected to the electric storage device through the charging circuit and the discharging circuit; the output end of the electric storage device is connected to the input end of the threshold control circuit. When the circuit works, the STDP time sequence identification circuit generates pulse output at the LTP output end when identifying the LTP characteristics, and the storage device is charged through the charging loop; when the STDP timing sequence identification circuit identifies the LTD characteristics, the output end of the LTD generates negative pulse output, and the electric storage device is discharged through the discharge loop; the voltage of the storage device changes along with the STDP effect; the threshold control circuit detects the voltage of the electric storage device, when the output voltage of the electric storage device reaches or exceeds a set threshold value 1, the threshold control circuit outputs a control signal, and a synapse transmission channel is started and connected through a channel switch circuit.
The working process further comprises the following steps: after the channel switching circuit is started to connect a synapse transmission channel, the threshold control circuit continues to detect the output voltage of the electric storage device, and when the output voltage of the electric storage device is lower than a set threshold 2, the output control signal is closed; and closing the synaptic transmission channel through the channel switching circuit. I.e. to cut off the synaptic transmission channel between the anterior membrane input and the posterior membrane output. Obviously, the set threshold 2 is smaller than the set threshold 1. As a more reasonable setting, setting threshold 2 may correspond to 65% to 85% of the value of setting threshold 1.
Fig. 19 is a circuit schematic of an embodiment thereof. Signals at the input end of the front film and the output end of the rear film are input by an I/O1 and an I/O2 of the MCU1801, identified LTP signals and LTD signals are output by an I/O3 and an I/O4 respectively, (positive output and negative output are respectively effective, output pulse width has STDP effect, refer to the working principle of fig. 16), and the capacitor C1801 is charged and generated through R1801 and R1802, so that the voltage on the C1801 changes along with the STDP effect. The voltage value of C1801 is provided again with R1803 and sent to I/O5, the voltage comparison circuit in MCU1801 compares the voltages according to the set rule (or performs analog-to-digital conversion and then voltage comparison), and the comparison result is output from I/O6 to control the on/off of analog switch K1801 as the channel control circuit, thereby realizing the on/off control of the synapse transmission channel.
The synapse transmission channel has synapse transmission characteristics, and can refer to and adopt the existing synapse simulation technology, and also can adopt the simulation technology of the solidified synapse. FIG. 20 is an embodiment of a "Preset synapse" simulation apparatus. The MCU2001, i.e., the MCU1801 in fig. 19, and the analog switch K2001, i.e., the K1801 in fig. 19, have synaptic transmission channels formed by C2002, R2004, R2005, R2006, D2003, etc., and the operation principle thereof can refer to the description of fig. 12.
For the STDP timing identification circuit, the prior art generally adopts an MCU circuit, and completes identification and output by using a program according to the STDP characteristic curve of fig. 13. The invention discloses a technology for realizing STDP identification and output by adopting a common digital gate circuit. The circuit is as shown in figure 21. Action potential peak potential signals from a front film input end and a rear film output end are subjected to voltage division through R2101, R2102, R2103 and R2104 respectively, so that the input peak potentials can effectively trigger the NOT gate circuits F2101 and F2103 only when reaching a sufficient voltage value, interference is avoided, once the input peak potentials effectively trigger the F2101 and the F2103, a monostable circuit formed by the F2102 or the F2104 is triggered to output a rectangular pulse, and the pulse width is about 5-10 times of the action potential pulse width; F2105-F2108 form an interlock circuit, so that both F2107 and F2108 can only have one output, (F2102 or F2104 triggers one side of the output rectangular pulse first, and F2107 or F2108 outputs a positive level and locks the other side as an output low level); when the F2102 and the F2104 output the rectangular pulse at the same time, the output of the and circuit F2112 is positive, and the effective width of the output is the time overlapping part of the rectangular pulse output by the F2102 and the F2104, which is obviously related to the timing of the peak potential signals at the front film input terminal and the rear film output terminal. The outputs of F2112 and the interlock circuit are connected to F2109 and F2110. When the peak potential signal at the input end of the front film is earlier than that at the output end of the rear film, that is, an LTP characteristic signal appears, F2109 outputs a positive level as an LTP output end, and the pulse width output by the output end is inversely related to the time difference of the front peak potential and the rear peak potential (as shown in FIG. 13); when the peak potential signal at the front film input terminal is slower than that at the rear film output terminal, that is, an LTD characteristic signal appears, F2110 outputs a positive level as the LTD output terminal, and the pulse width of the output is negatively related to the time difference between the front and rear peak potentials, and a negative level is output as the LTD output terminal after the inversion of F2111. The diodes D2101 and D2102 function as unidirectional outputs, i.e., the diodes to which the LTP output and the LTD output are connected in FIGS. 16, 19 and 20, as described above. The circuit adopts a common and cheap digital gate circuit, skillfully realizes the detection and the output of the STDP peak potential, has the advantage of extremely low cost although the output precision is not very high, and can work without depending on manual programs.
The parent application of the invention also discloses two simulated neural networks which are constructed by adopting the neuron simulation device and the synapse simulation device and have different working characteristics. Omitted here, and if necessary, see the parent application for details.
It should be noted that, in the circuit diagram disclosed in the present application, only elements related to the working principle are generally drawn and labeled, and peripheral related circuits such as power supply, power voltage stabilization, anti-interference, start-up and reset of a single chip microcomputer and the like belong to the conventional technology in the electronic field, and are not labeled for the sake of simplicity of the drawings.
In the various simulation techniques of the present invention, there are some main parameter settings in addition to the principle design of the circuit. In the actual working of the brain, the time span of the various working time courses is particularly large, such as: the pulse width of the action potential is from several milliseconds to several tens of milliseconds; the process of integration of neuronal membrane potential is on the order of tens to hundreds of milliseconds; the time for a modulatory synapse to undergo modulation may range from a few seconds to tens of minutes; the time for the hippocampal neurons to develop short-term plasticity and long-term plasticity for memory activity can range from minutes to hours to days; whereas, it takes many days or even years for neurons in the cortex to activate a "preset" synapse to develop into an "effective" synapse, or to grow a new effective synapse. For the work of the neural simulation network, especially the work of adopting the neural simulation network to experiment and demonstrate the neuron activity, it is unrealistic to adopt the same time span, so as to be convenient for us to set the time value of each working time interval according to the length relation of various working time intervals according to the working requirement. In addition, the potential change and the signal amplitude in the neural network are mostly voltage values of several millivolts to several tens of millivolts, and if the analog circuit is operated by this order of magnitude, it is difficult to install and is easily interfered by the electromagnetic force and the operation is not normal, so we can only set various signals and voltage values of the change separately.
As an example, the following gives a value of each working time course and each signal voltage, and this example is suitable for making a neuron simulation device and a synapse simulation device as experimental equipment for constructing a neural simulation network, simulating and demonstrating the activity of signal reflection and memory of neurons and synapses, and researching and disclosing more working mechanisms of the brain.
Analog device operating voltage: DC12 volts.
Action potential pulse width: 10 milliseconds.
Action potential pulse peak value: more than or equal to 11 volts.
The first threshold trigger circuit sets a trigger threshold: 3 volts.
The second threshold trigger circuit sets a trigger threshold: 3.7 volts.
Delay time of the signal delay circuit at the input of the first threshold trigger circuit: about 20 milliseconds.
Signal integration trigger condition of the film integration circuit: the excitation signal input within 100 milliseconds causes the output voltage of the membrane integration circuit to reach the first threshold trigger circuit set trigger threshold.
Refractory period after action potential triggering: about 100 milliseconds.
Modulated signal (including enhanced and suppressed) active periods: about 10 seconds.
Standard amplitude of postsynaptic membrane output signal: 8 volts, (without synaptic plasticity).
Maximum amplitude of postsynaptic membrane output signal: 10 volts, (when synaptic plasticity LTP is maximal).
Post-synaptic membrane output signal minimum amplitude: 6 volts, (when synaptic plasticity LDP is maximal).
The effective period of long-term synaptic plasticity of plastic synapses is as follows: about 5 minutes.
Set threshold value 1 of threshold control circuit of "preset synapse": 8 volts.
Set threshold value 2 of threshold control circuit of "preset synapse": 5 volts.
"Preset" synapse activation is a condition for "valid" synapses: the pre-and post-neuronal spike signals that satisfied the LTP effect of the STDP rule occurred 10 times in 10 minutes.
According to the above numerical values and the theory and formula of electricity, the specific numerical values of the RC circuits and the resistance-capacitance elements of the voltage division circuits can be set and calculated. Of course, the above values can be adjusted according to the actual needs of demonstration experiments.
In the parent application, the applicant further analyzes the process of bursting action potentials of different sodium ion channels in neurons, the formation mechanism of memory, the formation and conversion of short-term memory and long-term memory in detail, and the like, and is omitted in the present application for any length.
Claims (10)
1. A method for simulating a plastic synapse, comprising:
⑴, controlling the output signal of the output end of the rear membrane by the input signal of the input end of the presynaptic membrane, and enabling the output signal to be synchronous with the input signal;
⑵, detecting spike potential signals at the input end of the front film and the output end of the back film;
⑶, when identifying the spike potential signal which is in accordance with STDP characteristic between the front film input end and the back film output end, charging and discharging a storage device through a charging loop and a discharging loop according to the signal characteristic, if the signal is LTP characteristic, charging, if the signal is LDP characteristic, discharging;
⑷, adjusting the amplitude of the synapse output signal according to the voltage value of the storage device, and outputting to the posterior membrane output terminal;
⑸, the storage device is set to have an initialization voltage value at the beginning of operation.
2. The method for modeling a "plastic synapse" as claimed in claim 1, wherein: when the voltage on the storage device is greater than or less than the initialization voltage value, the voltage difference is slowly eliminated through a bidirectional bleeder circuit until the voltage on the storage device is equal to the initialization voltage value.
3. A simulation device of plastic synapse comprises a front membrane input end, a rear membrane output end, an STDP time sequence identification circuit and a synapse transmission efficiency adjusting circuit; the method is characterized in that: the STDP time sequence identification circuit is provided with an LTP output end and an LTD output end; the LTP output end and the LTD output end are respectively connected to an electric energy storage device for storing electric energy through a charging loop and a discharging loop; the power storage device is connected with an initialization charging circuit; the output of the power storage device is connected to a synapse transmission efficiency adjusting circuit, and the output end of the synapse transmission efficiency adjusting circuit is connected to the rear membrane output end; the synapse transmission efficiency regulating circuit is synchronously controlled by the input signal of the input end of the front membrane, and the output signal of the synapse transmission efficiency regulating circuit is modulated by the output voltage of the electric storage device in strength and synchronously controlled by the input signal of the input end of the front membrane in time.
4. A device for modelling a "plastic synapse" as claimed in claim 3, wherein: the electric storage device is also connected with a bidirectional bleeder circuit.
5. A device for modelling a "plastic synapse" as claimed in claim 4, wherein: the bidirectional bleeder circuit comprises a voltage stabilizing circuit with a set voltage, and the voltage stabilizing circuit is connected to the electric storage device through a resistor.
6. A device for modelling a "plastic synapse" as claimed in claim 3, wherein: the STDP time sequence identification circuit has threshold detection on signals input by the front film input end and the rear film output end, and only identifies the action potential spike with higher voltage amplitude.
7. A solidifying synapse simulating device comprises a front membrane input end and a rear membrane output end, and is characterized in that: a capacitor discharge circuit is connected in series between the front film input end and the rear film output end, and the capacitor discharge circuit is connected with a capacitor discharge circuit in parallel.
8. A "solidified synapse" simulation device as in claim 7, wherein: the capacitor discharge circuit is composed of a discharge capacitor, the front end of the discharge capacitor is connected with the front film input end, and the rear end of the discharge capacitor is connected with the rear film output end through a transfer resistor for setting transfer efficiency; two ends of the transfer resistor are reversely connected with a charging diode in parallel.
9. A device for modelling a "plastic synapse" as claimed in claim 3, wherein: an electrical circuit comprising a "solidified synapse" simulation device as claimed in claim 7 or 8 between the output of the synapse propagation performance adjusting circuit and the output of the posterior membrane.
10. The apparatus for simulating a "plastic synapse" of claim 9, wherein: and a capacitor discharge circuit is connected in series between the output end of the synapse transmission efficiency adjusting circuit and the output end of the rear membrane, and is also connected with a capacitor discharge circuit in parallel.
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| CN104899640A (en) | 2015-09-09 |
| CN111275178A (en) | 2020-06-12 |
| CN104899640B (en) | 2019-09-10 |
| CN107045649B (en) | 2020-06-02 |
| CN111291873A (en) | 2020-06-16 |
| CN107045649A (en) | 2017-08-15 |
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