CN111352776A - Device and method for capturing BIOS (basic input output System) and BMC (baseboard management controller) serial port data through FPGA (field programmable gate array) - Google Patents
Device and method for capturing BIOS (basic input output System) and BMC (baseboard management controller) serial port data through FPGA (field programmable gate array) Download PDFInfo
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- CN111352776A CN111352776A CN202010094735.0A CN202010094735A CN111352776A CN 111352776 A CN111352776 A CN 111352776A CN 202010094735 A CN202010094735 A CN 202010094735A CN 111352776 A CN111352776 A CN 111352776A
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- 238000007405 data analysis Methods 0.000 claims description 8
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
Abstract
The invention provides a device and a method for capturing BIOS and BMC serial port data through an FPGA (field programmable gate array). A first UART FIFO captures the BIOS serial port data, and a second UART FIFO captures the BMC serial port data; the first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO, and the data captured by the first UART FIFO and the second UART FIFO are sent to the upper computer through the output FIFO. The method does not need to set buttons, does not occupy additional precious space of the front panel of the server, can realize simultaneous capture of serial port data of the BIOS and the BMC, is not limited to capture of only one data at a time, accelerates various exceptions of the positioning server, can improve operation and maintenance efficiency of the server, and further improves operation stability of the server.
Description
Technical Field
The invention relates to the field of BIOS and BMC serial port data capture, in particular to a device and a method for capturing BIOS and BMC serial port data through an FPGA.
Background
At present, serial ports of a BIOS and a BMC are placed on a mainboard, and when the BIOS and the BMC are used, a mainboard case cover needs to be opened and connected with the mainboard case cover through a jig. However, in the practical application process, when the server has some problems and needs to find reasons and solutions, the design has a limitation. For example, when the server is in the rack, if the scene requires uninterrupted access to the serial port, power switching is required to put the whole computer off the rack, and then the box cover of the computer is opened to access the serial port, so that the operation is inconvenient and the efficiency is very low.
In order to solve the inconvenience, it is an advanced practice in the industry to design a serial interface and a button on the front panel of the server, and switch whether the serial interface is to connect the BIOS or the BMC through the button. The front panel space is at a premium and additional space is required to be occupied by the additional 1 button.
Disclosure of Invention
In order to solve the problems, the invention provides a device and a method for capturing serial port data of a BIOS (basic input output System) and a BMC (baseboard management controller) through an FPGA (field programmable gate array), which do not need to additionally place a button and do not occupy space.
The technical scheme of the invention is as follows: a device for capturing serial port data of a BIOS (basic input output System) and a BMC (baseboard management controller) through an FPGA (field programmable gate array), wherein the FPGA, the BIOS and the BMC are arranged on a mainboard; a first UART FIFO, a second UART FIFO and an output FIFO are arranged on the FPGA;
when the serial port of the BIOS is connected with the FPGA, the first UART FIFO captures BIOS serial port data; when the serial port of the BMC is connected with the FPGA, the second UART FIFO captures BMC serial port data;
the first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO, and the data captured by the first UART FIFO and the second UARTFIFO are sent to the upper computer through the output FIFO.
Furthermore, an encoding module is also arranged on the FPGA;
the first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO through the encoding module; the coding module codes the data captured by the first UART FIFO and the second UART FIFO so as to add corresponding identifications.
Further, the output FIFO is a USB FIFO; the output FIFO is communicated with the upper computer through a USB interface.
The technical scheme of the invention also comprises a device for capturing the serial port data of the BIOS and the BMC through the FPGA, which is arranged at an upper computer end and comprises,
a data receiving module: receiving capture data sent by the FPGA;
a data display module: and displaying the received captured data.
Further, the method also comprises the following steps of,
a data analysis module: analyzing the received captured data, and classifying according to the captured data identification;
and the data display module displays different captured data classified by the data analysis module in a classified manner.
The technical scheme of the invention also comprises a method for capturing the serial port data of the BIOS and the BMC through the FPGA, which is operated at an FPGA end and comprises the following steps:
when the serial port of the BIOS is connected with the FPGA, a first UART FIFO on the FPGA captures BIOS serial port data; the output FIFO on the FPGA sends the data captured by the first UART FIFO to an upper computer;
when the serial port of the BMC is connected with the FPGA, a second UART FIFO on the FPGA captures BMC serial port data; and the output FIFO on the FPGA sends the data captured by the second UART FIFO to the upper computer.
Further, the method also comprises the following steps:
when serial ports of the BIOS and the BMC are simultaneously connected with the FPGA, the first UART FIFO captures BIOS serial port data, and the second UART FIFO captures BMC serial port data;
the data captured by the first UART FIFO and the second UART FIFO are encoded by the encoding module, and are transmitted to the upper computer by the output FIFO after corresponding identifications are added.
The technical scheme of the invention also comprises a method for capturing the serial port data of the BIOS and the BMC through the FPGA, which is operated at an upper computer terminal and comprises the following steps:
receiving capture data sent by the FPGA;
and displaying the received captured data.
Further, the method also comprises the following steps:
analyzing the received captured data, and classifying according to the captured data identification;
and displaying the classified different captured data in a classified mode.
According to the device and the method for capturing the serial port data of the BIOS and the BMC through the FPGA, the FIFO is designed in the FPGA, the serial port data of the BIOS and the BMC are collected and sent to the upper computer through the FIFO, a button does not need to be arranged, and the precious space of a front panel of a server is not occupied additionally. The configurable coding module realizes simultaneous capture of BIOS and BMC serial port data, is not limited to capture of only one data at a time, accelerates various exceptions of the positioning server, can improve operation and maintenance efficiency of the server, and further improves operation stability of the server.
Drawings
Fig. 1 is a three-principle structural diagram of the embodiment of the present invention.
Fig. 2 is a schematic flow chart of a fifth method according to an embodiment of the present invention.
FIG. 3 is a schematic flow diagram of a hexagonal process according to an embodiment of the present invention.
Fig. 4 is a flow chart of a seventh method according to an embodiment of the present invention.
Fig. 5 is a schematic flow chart of an eighth method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
Example one
The embodiment provides a device for grabbing serial port data of a BIOS (basic input output System) and a BMC (baseboard management controller) through an FPGA (field programmable gate array), 2 FIFOs are designed in the FPGA, the serial port data of the BIOS and the BMC are collected and cached respectively, then the serial port data are sent to an upper computer through one universal FIFO, the information of the BIOS and the BMC can be grabbed by using adaptive software in the upper computer, a button does not need to be arranged on a front panel, and grabbing of the serial port data of the BIOS and the BMC can be achieved.
The device is provided with a first UART FIFO, a second UART FIFO and an output FIFO on an FPGA.
When the serial port of the BIOS is connected with the FPGA, the first UART FIFO captures BIOS serial port data; when the serial port of the BMC is connected with the FPGA, the second UART FIFO captures BMC serial port data.
The first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO, and the data captured by the first UART FIFO and the second UARTFIFO are sent to the upper computer through the output FIFO.
It should be noted that the serial port of the BIOS is connected from the PCH, the serial port of the BMC is directly connected from the BMC chip, and the serial ports of the BIOS and the BMC are both connected to the FPGA. After the data of the BIOS and the BMC are cached in the FPGA through 2 FIFOs, the data are sent to an upper computer through a general FIFO.
Example two
The embodiment provides a device for capturing serial port data of a BIOS and a BMC through an FPGA, which is configured at an upper computer end, is adapted to the device of the first embodiment, and receives the serial port data of the BIOS and the BMC.
The device comprises a data receiving module and a data display module.
Wherein, the data receiving module: receiving capture data sent by the FPGA; a data display module: and displaying the received captured data.
When the serial port of the BIOS is connected to the FPGA, the data receiving module automatically receives the serial port data of the BIOS, and the data display module displays the serial port data of the BIOS. When the serial port of the BMC is connected with the FPGA, the data receiving module automatically receives the serial port data of the BMC, and the data display module displays the serial port data of the BMC.
EXAMPLE III
As shown in fig. 1, on the basis of the first embodiment, the device for capturing serial port data of the BIOS and the BMC through the FPGA provided in this embodiment further sets a coding module on the FPGA in order to distinguish the serial port data of the BIOS and the BMC and to achieve synchronous transmission of the serial port data of the BIOS and the BMC. The first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO through the encoding module; the coding module codes the data captured by the first UART FIFO and the second UART FIFO so as to add corresponding identifications. Namely, a token identifier is added before each serial byte to identify whether a byte is serial data of the BIOS or the BMC. In this example, the token identifier before the BIOS serial data is 8 'b 10101010, and the token identifier before the BMC serial data is 8' b 01010101.
In this embodiment, a USB FIFO is established inside the FPGA as a general output FIFO, and the output FIFO communicates with the upper computer through a USB interface. The USB FIFO converts the coded data into a USB protocol, the USB interface is positioned on the front panel, and the data of the BIOS and the BMC can be sent to the upper computer through the USB protocol on the front panel.
This embodiment snatchs out BIOS and BMC's serial port data simultaneously through establishing three FIFO in FPGA is inside, sends away through the USB agreement after the coding for various exceptions that appear in the positioning server can improve the operation and maintenance efficiency and the maintenance efficiency of server, and then improves the stability of server operation.
Example four
The device for capturing the serial port data of the BIOS and the BMC through the FPGA provided in this embodiment is configured at an upper computer end, and is adapted to the device described in the third embodiment, so as to receive the serial port data of the BIOS and the BMC.
The device comprises a data receiving module, a data display module and a data analysis module.
Wherein, the data receiving module: receiving capture data sent by the FPGA; a data display module: and displaying the received captured data.
When the serial port of the BIOS is connected to the FPGA, the data receiving module automatically receives the serial port data of the BIOS, and the data display module displays the serial port data of the BIOS. When the serial port of the BMC is connected with the FPGA, the data receiving module automatically receives the serial port data of the BMC, and the data display module displays the serial port data of the BMC.
In order to distinguish the serial port data of the BIOS and the BMC and realize synchronous capture of the serial port data of the BIOS and the BMC, a data analysis module is arranged at the upper computer end and analyzes the received captured data, and classification is carried out according to captured data identification. Correspondingly, the data display module displays different captured data classified by the data analysis module in a classified manner.
When serial ports of the BIOS and the BMC are connected with the FPGA at the same time, serial port data of the BIOS and the BMC are coded and then sent to an upper computer end at the same time, a token identifier is arranged before byte after the serial port data of the BIOS and the BMC are coded, a data analysis module of the upper computer end classifies the data according to the identifier, and the data are classified and displayed, so that the BIOS or the BMC serial port data can be distinguished.
EXAMPLE five
As shown in fig. 2, the embodiment provides a method for capturing serial port data of a BIOS and a BMC through an FPGA, which runs on an FPGA side, and includes the following steps:
when the serial port of the BIOS is connected with the FPGA, a first UART FIFO on the FPGA captures BIOS serial port data; the output FIFO on the FPGA sends the data captured by the first UART FIFO to an upper computer;
when the serial port of the BMC is connected with the FPGA, a second UART FIFO on the FPGA captures BMC serial port data; and the output FIFO on the FPGA sends the data captured by the second UART FIFO to the upper computer.
According to the method, after the data of the BIOS and the BMC are cached in the FPGA through 2 FIFOs, the data are sent to the upper computer through a general FIFO, a button does not need to be arranged on a front panel, and the BIOS and BMC serial port data can be captured.
EXAMPLE six
The embodiment is adapted to the fifth embodiment, and provides a method for capturing serial port data of the BIOS and the BMC through the FPGA, which is run at an upper computer end.
As shown in fig. 3, the method comprises the steps of:
receiving capture data sent by the FPGA;
and displaying the received captured data.
It should be noted that, when the serial port of the BIOS is connected to the FPGA, the upper computer terminal automatically receives and displays the serial port data of the BIOS. When the serial port of the BMC is connected with the FPGA, the upper computer terminal automatically receives and displays the serial port data of the BMC.
EXAMPLE seven
On the basis of the fifth embodiment, in order to distinguish the serial port data of the BIOS and the BMC and achieve synchronous capture of the serial port data of the BIOS and the BMC, the embodiment provides a method for capturing the serial port data of the BIOS and the BMC through the FPGA. As shown in fig. 4, the method comprises the steps of:
when serial ports of the BIOS and the BMC are simultaneously connected with the FPGA, the first UART FIFO captures BIOS serial port data, and the second UART FIFO captures BMC serial port data;
the data captured by the first UART FIFO and the second UART FIFO are encoded by the encoding module, and are transmitted to the upper computer by the output FIFO after corresponding identifications are added.
It should be noted that a USB FIFO may be established inside the FPGA as a general output FIFO, and the USB FIFO communicates with the upper computer through a USB interface.
This embodiment snatchs out BIOS and BMC's serial port data simultaneously through establishing three FIFO in FPGA is inside, sends away through the USB agreement after the coding for various exceptions that appear in the positioning server can improve the operation and maintenance efficiency and the maintenance efficiency of server, and then improves the stability of server operation.
Example eight
The embodiment provides a method for capturing serial port data of a BIOS and a BMC through an FPGA, which is operated at an upper computer end and is adapted to the method of the seventh embodiment.
As shown in fig. 5, the method comprises the following steps:
receiving capture data sent by the FPGA;
analyzing the received captured data, and classifying according to the captured data identification;
and displaying the classified different captured data in a classified mode.
It should be noted that the capture data sent by the FPGA includes BIOS serial data and BMC serial data, but the front ends of the two data set corresponding identifiers for identifying whether the serial data is BIOS serial data or BMC serial data.
The upper computer end classifies the data according to the identification, and displays the data in a classified manner, so that the BIOS or BMC serial port data can be distinguished.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.
Claims (9)
1. A device for capturing serial port data of a BIOS (basic input output System) and a BMC (baseboard management controller) through an FPGA (field programmable gate array), wherein the FPGA, the BIOS and the BMC are arranged on a mainboard; the FPGA is characterized in that a first UART FIFO, a second UART FIFO and an output FIFO are arranged on the FPGA;
when the serial port of the BIOS is connected with the FPGA, the first UART FIFO captures BIOS serial port data; when the serial port of the BMC is connected with the FPGA, the second UART FIFO captures BMC serial port data;
the first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO, and the data captured by the first UART FIFO and the second UARTFIFO are sent to the upper computer through the output FIFO.
2. The device for capturing the serial port data of the BIOS and the BMC through the FPGA according to claim 1, wherein a coding module is further arranged on the FPGA;
the first UART FIFO and the second UART FIFO are respectively communicated with the output FIFO through the encoding module; the coding module codes the data captured by the first UART FIFO and the second UART FIFO so as to add corresponding identifications.
3. The device for capturing the serial port data of the BIOS and the BMC through the FPGA according to claim 1 or 2, wherein the output FIFO is a USB FIFO; the output FIFO is communicated with the upper computer through a USB interface.
4. A device for capturing serial port data of BIOS and BMC through FPGA is characterized in that the device is configured at an upper computer end and comprises,
a data receiving module: receiving capture data sent by the FPGA;
a data display module: and displaying the received captured data.
5. The device for capturing serial port data of BIOS and BMC through FPGA as claimed in claim 4, further comprising,
a data analysis module: analyzing the received captured data, and classifying according to the captured data identification;
and the data display module displays different captured data classified by the data analysis module in a classified manner.
6. A method for capturing serial port data of a BIOS and a BMC through an FPGA is characterized by operating at an FPGA end and comprising the following steps:
when the serial port of the BIOS is connected with the FPGA, a first UART FIFO on the FPGA captures BIOS serial port data;
the output FIFO on the FPGA sends the data captured by the first UART FIFO to an upper computer;
when the serial port of the BMC is connected with the FPGA, a second UART FIFO on the FPGA captures BMC serial port data;
and the output FIFO on the FPGA sends the data captured by the second UART FIFO to the upper computer.
7. The method for capturing the serial port data of the BIOS and the BMC through the FPGA according to claim 6, further comprising the steps of:
when serial ports of the BIOS and the BMC are simultaneously connected with the FPGA, the first UART FIFO captures BIOS serial port data, and the second UARTFIFO captures BMC serial port data;
the data captured by the first UART FIFO and the second UART FIFO are encoded by the encoding module, and are transmitted to the upper computer by the output FIFO after corresponding identifications are added.
8. A method for capturing serial port data of a BIOS and a BMC through an FPGA is characterized by operating at an upper computer end and comprising the following steps:
receiving capture data sent by the FPGA;
and displaying the received captured data.
9. The method for capturing the serial port data of the BIOS and the BMC through the FPGA according to claim 8, further comprising the steps of:
analyzing the received captured data, and classifying according to the captured data identification;
and displaying the classified different captured data in a classified mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010094735.0A CN111352776A (en) | 2020-02-16 | 2020-02-16 | Device and method for capturing BIOS (basic input output System) and BMC (baseboard management controller) serial port data through FPGA (field programmable gate array) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010094735.0A CN111352776A (en) | 2020-02-16 | 2020-02-16 | Device and method for capturing BIOS (basic input output System) and BMC (baseboard management controller) serial port data through FPGA (field programmable gate array) |
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| CN111352776A true CN111352776A (en) | 2020-06-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113065048A (en) * | 2021-02-26 | 2021-07-02 | 山东英信计算机技术有限公司 | BMC Web automatic detection method, system and medium based on Web crawler |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113065048A (en) * | 2021-02-26 | 2021-07-02 | 山东英信计算机技术有限公司 | BMC Web automatic detection method, system and medium based on Web crawler |
| CN113065048B (en) * | 2021-02-26 | 2023-03-21 | 山东英信计算机技术有限公司 | BMC Web automatic detection method, system and medium based on Web crawler |
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