CN111343148A - FGPA communication data processing method, system and device - Google Patents
FGPA communication data processing method, system and device Download PDFInfo
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Abstract
The invention discloses a processing method of FGPA communication data, which can receive a data packet through a network interface after encapsulating the data packet by using a preset protocol, wherein a frame type and a frame content are defined in the preset protocol, namely, the data packet can be analyzed according to the preset protocol after receiving the data packet, the frame type and the frame content are determined, and corresponding operation is carried out on data in the frame content according to the frame type. The application also provides a processing system, a device and a computer readable storage medium of FGPA communication data, which can also achieve the above effects.
Description
Technical Field
The invention relates to the field of Field Programmable Gate Array (FPGA) technology, in particular to a method, a system and a device for processing FGPA communication data.
Background
The FPGA (Field-Programmable Gate Array) heterogeneous accelerator card can perform accelerated calculation on source operation data sent by a CPU (Central Processing Unit) and return a calculation result to the CPU, thereby implementing high-performance calculation capability and completing functions with high requirements on calculation capability, such as video encoding and decoding, deep learning, scientific calculation, graphic Processing, and the like.
With the expansion of the application of the FPGA heterogeneous accelerator card in the cloud data center, the FPGA accelerator card starts to be deployed in a large scale, the existing deployment mode generally adopts a machine-card binding mode, namely, each FPGA accelerator card is directly plugged into a standard bus interface of a server through a PCI-E slot, when a user applies for using an FPGA instance, the user generally allocates a set of environment of a virtual machine to the user, and the user uses the virtual machine to access and use the FPGA board card.
At present, the deployment modes of the FPGA heterogeneous accelerator card mainly comprise a single-computer single-card mode and a single-computer multi-card mode, namely one card is inserted into one server or a plurality of cards are inserted into one server. In the machine-card binding mode, the FPGA heterogeneous accelerator card is tightly coupled with a CPU of the server, namely the use of the FPGA heterogeneous accelerator card depends on the CPU, and a user can only access and use the FPGA heterogeneous accelerator card through the CPU of the server.
Therefore, how to reduce the dependence of the FPGA communication data processing process on the server CPU and improve the data processing efficiency is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a processing method, a system and a device of FGPA communication data, so as to reduce the expansion cost of an FPGA heterogeneous accelerator card.
In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
a processing method of FGPA communication data comprises the following steps:
receiving a data packet encapsulated by a data sender by using a preset protocol by using a network interface; the data packet comprises a frame type and frame contents, and the frame contents comprise FPGA communication data information;
analyzing the data packet to obtain the frame type and the frame content;
and determining data processing operation corresponding to the frame type, and executing the data processing operation on the FPGA communication data in the frame content.
Optionally, when the frame type includes a data transfer type, the data processing operation is performed on the FPGA communication data in the frame content, and the data processing operation includes:
and moving the FPGA communication data in the frame content according to the frame type.
Optionally, the frame type includes an RDMA type, and the FPGA communication data information includes a source address for storing FPGA communication data, a data length for storing the FPGA communication data, and a destination address for storing the FPGA communication data;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and moving the FPGA communication data with the data length to the source address to the destination address.
Optionally, the frame type includes a file programming type, and the FPGA communication data information includes a content of a file to be programmed;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and programming the content of the file to be programmed to the FPGA.
Optionally, the frame type includes an instruction type, the FPGA communication data information includes read-write identifiers, command numbers and command information of the command numbers, and each command information includes an FPGA register address and to-be-written data or null data corresponding to the FPGA register address;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and sequentially executing register writing or register reading operation on the FPGA register address in each command message according to the read-write identification.
Optionally, the frame type includes a reply type, and the FPGA communication data information includes a reply identifier;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and determining the processing result of the FPGA communication data by using the reply identifier.
Optionally, the data packet further includes a frame sequence number, and after receiving, by using the network interface, the data packet encapsulated by the data sender using the preset protocol, the method further includes:
analyzing the data packet to obtain the frame sequence number;
and determining whether the data packet is lost or not by using the frame sequence numbers and the frame sequence numbers of all the currently received data packets.
Optionally, the FPGA communication data letter is packet data obtained by dividing original data into preset packet numbers;
the data packet also comprises a packet sequence number;
after receiving the data packet encapsulated by the data sender by using the preset protocol by using the network interface, the method further comprises the following steps:
and analyzing the data packet to obtain the packet sequence number so as to package the communication data by using the packet sequence number.
To achieve the above object, the present application further provides a FGPA communication data processing system, including:
the data packet receiving module is used for receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information;
the analysis module is used for analyzing the data packet to obtain the frame type and the frame content;
and the data processing module is used for determining the data processing operation corresponding to the frame type and executing the data processing operation on the FPGA communication data in the frame content.
To achieve the above object, the present application further provides a FGPA communication data processing apparatus, including:
a memory for storing a computer program;
a processor for implementing the steps of the method of processing FGPA communication data according to any of the above when executing the computer program.
As can be seen from the above solutions, the method for processing FGPA communication data according to the present invention includes: receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and frame contents, and the frame contents comprise FPGA communication data information; analyzing the data packet to obtain the frame type and the frame content; and determining data processing operation corresponding to the frame type, and executing the data processing operation on the FPGA communication data in the frame content.
Therefore, according to the processing method for the FGPA communication data, provided by the application, after the data packet is encapsulated by using the preset protocol, the data packet can be received through the network interface, the frame type and the frame content are defined in the preset protocol, namely, the data packet can be analyzed according to the preset protocol after the data packet is received, the frame type and the frame content are determined, and corresponding operation is performed on the data in the frame content according to the frame type. The application also provides a processing system, a device and a computer readable storage medium of FGPA communication data, which can also achieve the above effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a processing method of FGPA communication data according to an embodiment of the present invention;
fig. 2 is a flowchart of a specific FGPA communication data processing method according to an embodiment of the present invention;
fig. 3 is a flowchart of a specific FGPA communication data processing method according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a FGPA communication data processing system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a processing method, a system and a device of FGPA communication data, which are used for reducing the expansion cost of an FPGA heterogeneous accelerator card.
Referring to fig. 1, a method for processing FGPA communication data provided in the embodiment of the present invention specifically includes:
s101, receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information.
Different from the prior art, the FPGA board card in the scheme can not receive data only through the PCIE interface any more, but can receive a data packet through the network interface.
Specifically, a network interface is used to receive a data packet, where the data packet is a data packet encapsulated by a data sender using a preset encapsulation protocol. It should be noted that, because the data transmission mode is changed, in the present solution, the encapsulation mode of the data packet also needs to be adjusted, so that the data can be transmitted in the network and can be recognized and processed by both communication parties. According to the scheme, the FPGA communication data information is packaged by using a preset protocol so as to realize transmission of the FPGA communication data through a network.
In the scheme, the content of the preset protocol at least comprises a frame type and frame content. The frame type is used for setting a processing operation type of the FPGA communication data, the frame content comprises FPGA communication data information, the FPGA communication data information is operation content corresponding to the processing operation type, for example, the frame type is data moving, and the FPGA communication data information is FPGA communication data to be moved.
It should be noted that, in this scheme, the data sender may be a CPU or an FPGA, and the data receiver may also be a CPU or an FPGA, where when the data sender or the data receiver is a CPU, the opposite end is an FPGA, and when the data sender or the data receiver is an FPGA, the opposite end is an FPGA or a CPU.
It should also be noted that the data packet may be transmitted in a local area network or a public network, when the data packet is transmitted in the local area network, the data packet encapsulated by the preset protocol may be directly transmitted, and when the data packet is transmitted in the public network, the data packet needs to be encapsulated by the preset protocol on the basis of the protocol of the transport layer or the MAC layer. Taking the transport layer protocol UDP as an example, the encapsulation result is shown in table 1 below, where FCS is a frame check sequence.
TABLE 1
| Source address | Destination address | Type (B) | IP packet header | UDP message header | Data packet encapsulated by preset protocol | FCS |
S102, analyzing the data packet to obtain the frame type and the frame content.
After receiving the data packet, the data packet needs to be analyzed according to a preset protocol, so as to obtain the frame type and the frame content therein.
S103, determining data processing operation corresponding to the frame type, and executing the data processing operation on the FPGA communication data in the frame content.
It should be noted that different frame types correspond to different data processing operations, and after the frame types and the frame contents are analyzed, the processing operations are determined according to the frame types, and the FPGA communication data in the real contents is correspondingly processed.
Therefore, according to the processing method for the FGPA communication data, provided by the application, after the data packet is encapsulated by using the preset protocol, the data packet can be received through the network interface, the frame type and the frame content are defined in the preset protocol, namely, the data packet can be analyzed according to the preset protocol after the data packet is received, the frame type and the frame content are determined, and corresponding operation is performed on the data in the frame content according to the frame type.
The following describes different frame types and corresponding processing operations in a processing method of FGPA communication data provided by an embodiment of the present application.
The frame type may specifically include 5 types, that is, a data transfer type, an RDMA (Remote Direct memory access) type, a file write type, an instruction type, and a reply type.
Referring to table 2, table 2 illustrates each frame type by way of specific example, wherein the encoding may be adjusted according to actual situations, and the scheme is not limited. In this example, X is a variable and can be modified according to different types, for example, for the data movement type 0X01, when the data movement operation is specifically from HOST to FPGA movement, X is 0, i.e. the code is 0X 0101. HOST is the server HOST terminal, and FPGA is the heterogeneous acceleration card terminal of FPGA.
In the table, the data movement type and the RDMA type both include three types, each representing a different data transmission direction; the file programming type specifically comprises 2 programming modes, namely programming a Bit file to the FPGA and programming a Bit file to the FLASH; the instruction type specifically comprises a plurality of instructions, the specific content of the instruction is not introduced in the scheme, and the instruction can be selected and set according to the actual situation, for example, the instruction can be a remote updating program instruction, a temperature reading instruction and the like; the reply type corresponds to the frame type in 4 described above, and is an operation type for replying to the processing result of the frame type in 4 described above.
The codes reserved in the table, i.e. the codes that are temporarily not used, can be defined according to actual needs.
TABLE 2
In a specific embodiment, the frame type includes a data transfer type, and the FPGA communication data information is FPGA communication data;
correspondingly, the processing the FPGA communication data in the frame content according to the frame type includes:
and moving the FPGA communication data in the frame content according to the frame type.
In the scheme, if the frame type is the data transfer type, the corresponding frame content includes FPGA communication data, that is, data to be transferred, that is, if the frame type is the data transfer type, the actual data to be transferred needs to be stored along with a data packet and sent to a data receiving party, and after receiving the data packet, the data receiving party obtains the FPGA communication data to be transferred from the frame content and transfers the FPGA communication data to a local target address when analyzing that the frame type is the data transfer type. It should be noted that the destination address may also be set by data transmission and defined in the data packet by using a preset protocol.
In a specific embodiment, the frame type includes an RDMA type, and the FPGA communication data information includes a source address for storing FPGA communication data, a data length for storing the FPGA communication data, and a destination address for storing the FPGA communication data;
correspondingly, the processing the FPGA communication data in the frame content according to the frame type includes:
and moving the FPGA communication data with the data length to the source address to the destination address.
In the scheme, the frame type is an RDMA type, and in the RDMA type, a data receiving party needs to actively find the data to be moved to a source address of the data to be moved and move the data. Therefore, in the scheme, when the frame type is the RDMA type, the FPGA communication data information is not the data to be moved any more, but the source address, the destination address and the data length of the data to be moved, and when the data receiver receives the data packet and analyzes that the frame type is the RDMA type, the data receiver determines three parameters of the source address, the destination address and the data length in the FPGA communication data information, and actively acquires the FPGA communication data to be moved from the source address.
In a specific implementation manner, the frame type includes an instruction type, the FPGA communication data information includes a read-write identifier, a number of commands, and a number of command information of the number of commands, and each command information includes an FPGA register address and to-be-written data or null data corresponding to the FPGA register address;
correspondingly, the processing the FPGA communication data in the frame content according to the frame type includes:
and sequentially executing register writing or register reading operation on the FPGA register address in each command message according to the read-write identification.
In the present solution, the frame type is an instruction type, for the instruction type, the corresponding FPGA communication data information is at least one command information, it should be noted that, in the FPGA, different registers correspond to different functions, for example, one register is a register for authorization management, when the register is written with 1, a certain authority is granted to the current user, and when the register is written with 0, the authority of the current user is cancelled. In the scheme, the command is in a form of reading or writing a register, and the register command information comprises an FPGA register address and data to be written or null data. It should be noted that, if the register is written, a data field in the FPGA communication data information includes a value to be specifically written into the register, and if the register is read, the data field in the FPGA communication data information is a reserved field, and the field is not filled with any data.
Referring to table 3, table 3 shows the specific content of the FPGA communication data information when the frame type is the instruction type. The method can transmit a plurality of commands at one time, the command number field fills in the specific command number, the message body is command information of the command number, and each command information comprises an FPGA register address, a Data field (Data) and a reserved field.
TABLE 3
In a specific embodiment, the frame type includes a reply type, and the FPGA communication data information includes a reply identifier;
correspondingly, the processing the FPGA communication data in the frame content according to the frame type includes:
and determining the processing result of the FPGA communication data by using the reply identifier.
In this embodiment, the reply type corresponds to the frame type, and is used to identify the operation processing result of the frame type. The reply types specifically include 4 types, namely data transfer reply, RDMA reply, Bit file programming reply, instruction reply and reply types.
See tables 4 to 7 for specific contents of the FPGA communication data information corresponding to the 4 reply types. The type of the reply may be specifically included in the packet header, that is, the type of the reply is identified, so that after receiving the FPGA communication data information, the type of the reply may be directly determined from the packet header.
TABLE 4
TABLE 5
TABLE 6
TABLE 7
A specific FGPA communication data processing method provided in the embodiments of the present application is described below, and the specific FGPA communication data processing method described below and any of the embodiments described above may be referred to with each other.
Referring to fig. 2, a specific processing method for FGPA communication data provided in the embodiment of the present application specifically includes:
s201, receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information.
S202, analyzing the data packet to obtain a frame sequence number.
In this scheme, the data packets further include a frame sequence number, where the frame sequence number is used to identify each data packet, for example, if data transmission needs to send 5 data packets, each data packet may be identified by using 5 sequence numbers.
S203, determining whether the lost data packet exists or not by using the frame sequence number and the frame sequence numbers of all the currently received data packets.
After receiving the data packet, the frame number is obtained by analysis, so that whether the data packet which is not received exists can be determined by using the frame number, that is, whether packet loss exists can be determined.
S204, analyzing the data packet to obtain the frame type and the frame content.
And S205, processing the FPGA communication data in the frame content according to the frame type.
Therefore, the frame number is added to the data packet, so that the frame number in the data packet can be analyzed after the data packet is received, the problem of packet loss is determined by using the frame number, and the packet loss can be timely found and the information of the lost data packet can be accurately determined.
A specific FGPA communication data processing method provided in the embodiments of the present application is described below, and the specific FGPA communication data processing method described below and any of the embodiments described above may be referred to with each other.
Referring to fig. 3, a specific processing method for FGPA communication data provided in the embodiment of the present application specifically includes:
a specific FGPA communication data processing method provided in the embodiments of the present application is described below, and the specific FGPA communication data processing method described below and any of the embodiments described above may be referred to with each other.
Referring to fig. 3, a specific processing method for FGPA communication data provided in the embodiment of the present application specifically includes:
s301, a network interface is used for receiving a data packet which is encapsulated by a data sender by using a preset protocol, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information.
S302, analyzing the data packet to obtain the packet sequence number, and packaging the communication data by using the packet sequence number.
It should be noted that, when the amount of the FPGA communication data to be transmitted is large, the time delay for transmitting the FPGA communication data at one time is large, which affects the quality of data transmission. Therefore, the FPGA communication data is subjected to sub-packaging in the scheme, namely, the big data is divided into a plurality of small data, each small data is sub-packaged data, and a sub-packaging sequence number is determined for each sub-packaged data and is used for identifying the sub-packaged data. And after receiving all data packets corresponding to one data, the data receiving party can package the data packets according to the sub-packet sequence numbers to obtain complete FPGA communication data.
S303, analyzing the data packet to obtain the frame type and the frame content.
S304, processing the FPGA communication data in the frame content according to the frame type.
Therefore, according to the processing method of the FGPA communication data provided by the embodiment of the application, the data volume of each data transmission can be reduced through a sub-packet mode, so that the data transmission quality is prevented from being influenced by too much data, and the data receiving party can package the data through the sub-packet sequence number through a mode of packaging the sub-packet sequence number in the data packet, so that complete FPGA communication data is obtained.
The following describes a processing system for FGPA communication data provided in an embodiment of the present application, and the following description of the processing system for FGPA communication data may be mutually referred to any of the above embodiments.
Referring to fig. 4, the system for processing FGPA communication data provided in the embodiment of the present application specifically includes:
a data packet receiving module 401, configured to receive, by using a network interface, a data packet that is encapsulated by a data sender by using a preset protocol, where the data packet includes a frame type and a frame content, and the frame content includes FPGA communication data information;
an analyzing module 402, configured to analyze the data packet to obtain the frame type and the frame content;
a data processing module 403, configured to determine a data processing operation corresponding to the frame type, and execute the data processing operation on the FPGA communication data in the frame content.
The processing system of the FGPA communication data of this embodiment is used for implementing the foregoing processing method of the FGPA communication data, and therefore, the specific implementation in the processing system of the FGPA communication data may be found in the foregoing embodiments of the processing method of the FGPA communication data, for example, the packet receiving module 401, the parsing module 402, and the data processing module 403 are respectively used for implementing steps S101, S102, and S103 in the processing method of the FGPA communication data, so that the specific implementation thereof may refer to the description of the corresponding embodiments of each part, and is not described herein again.
The present application further provides a FGPA communication data processing apparatus, including:
a memory for storing a computer program;
a processor, configured to execute the computer program, and implement the steps provided in any of the above-mentioned embodiments of FGPA communication data processing method.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for processing FGPA communication data, comprising:
receiving a data packet encapsulated by a data sender by using a preset protocol by using a network interface; the data packet comprises a frame type and frame contents, and the frame contents comprise FPGA communication data information;
analyzing the data packet to obtain the frame type and the frame content;
and determining data processing operation corresponding to the frame type, and executing the data processing operation on the FPGA communication data in the frame content.
2. The method of claim 1, wherein when the frame type comprises a data movement type, performing the data processing operation on the FPGA communication data in the frame content comprises:
and moving the FPGA communication data in the frame content according to the frame type.
3. The method of claim 1, wherein the frame type comprises an RDMA type, wherein the FPGA communication data information comprises a source address where FPGA communication data is stored, a data length of the FPGA communication data, and a destination address where the FPGA communication data is stored;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and moving the FPGA communication data with the data length to the source address to the destination address.
4. The method according to claim 1, wherein the frame type comprises a file programming type, and the FPGA communication data information comprises file contents to be programmed;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and programming the content of the file to be programmed to the FPGA.
5. The method according to claim 1, wherein the frame type includes an instruction type, the FPGA communication data information includes a read-write identifier, command number and command information of the command number, and each command information includes an FPGA register address and data to be written or null data corresponding to the FPGA register address;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and sequentially executing register writing or register reading operation on the FPGA register address in each command message according to the read-write identification.
6. The method of claim 1, wherein the frame type comprises a reply type, and wherein the FPGA communication data information comprises a reply identification;
correspondingly, the data processing operation is performed on the FPGA communication data in the frame content, and includes:
and determining the processing result of the FPGA communication data by using the reply identifier.
7. The method according to claim 1, wherein the data packet further includes a frame sequence number, and after receiving, by the network interface, the data packet encapsulated by the data sender using the predetermined protocol, the method further includes:
analyzing the data packet to obtain the frame sequence number;
and determining whether the data packet is lost or not by using the frame sequence numbers and the frame sequence numbers of all the currently received data packets.
8. The method according to claim 1, wherein the FPGA communication data message is packetized data dividing original data into a preset number of packets;
the data packet also comprises a packet sequence number;
after receiving the data packet encapsulated by the data sender by using the preset protocol by using the network interface, the method further comprises the following steps:
and analyzing the data packet to obtain the packet sequence number so as to package the communication data by using the packet sequence number.
9. A system for processing FGPA communication data, comprising:
the data packet receiving module is used for receiving a data packet which is encapsulated by a data sender by using a preset protocol by using a network interface, wherein the data packet comprises a frame type and a frame content, and the frame content comprises FPGA communication data information;
the analysis module is used for analyzing the data packet to obtain the frame type and the frame content;
and the data processing module is used for determining the data processing operation corresponding to the frame type and executing the data processing operation on the FPGA communication data in the frame content.
10. An apparatus for processing FGPA communication data, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method of processing FGPA communication data according to any of claims 1 to 8 when executing the computer program.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111711968A (en) * | 2020-06-10 | 2020-09-25 | 京信通信系统（中国）有限公司 | Message processing method, device, communication equipment and communication system |
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| CN111711968A (en) * | 2020-06-10 | 2020-09-25 | 京信通信系统（中国）有限公司 | Message processing method, device, communication equipment and communication system |
| CN111711968B (en) * | 2020-06-10 | 2022-02-01 | 京信网络系统股份有限公司 | Message processing method, device, communication equipment and communication system |
| CN112214264A (en) * | 2020-10-10 | 2021-01-12 | 交通运输部规划研究院 | AIS interactive operation processing method and device |
| CN112416840A (en) * | 2020-11-06 | 2021-02-26 | 浪潮(北京)电子信息产业有限公司 | Remote mapping method, device and equipment of computing resources and storage medium |
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| US11960430B2 (en) | 2020-11-06 | 2024-04-16 | Inspur (Beijing) Electronic Information Industry Co., Ltd. | Remote mapping method, apparatus and device for computing resources, and storage medium |
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| CN113065642B (en) * | 2021-04-09 | 2023-04-07 | 中电科数字科技(集团)有限公司 | Artificial intelligence acceleration method and system based on heterogeneous computing |
| WO2023206787A1 (en) * | 2022-04-29 | 2023-11-02 | 苏州元脑智能科技有限公司 | Heterogeneous acceleration method, apparatus and system and computer readable storage medium |
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