CN111343106B

CN111343106B - Multi-channel intermediate frequency digital signal processing device and method

Info

Publication number: CN111343106B
Application number: CN202010116033.8A
Authority: CN
Inventors: 母国标
Original assignee: Individual
Current assignee: Chengdu Chaomaitong Technology Co ltd
Priority date: 2020-02-25
Filing date: 2020-02-25
Publication date: 2023-03-24
Anticipated expiration: 2040-02-25
Also published as: CN111343106A

Abstract

The application relates to a multipath intermediate frequency digital signal processing device and a method, wherein the device comprises: the sending channel comprises a group of first processors which can be programmed by software and is used for carrying out time division multiplexing on m paths of data acquired through m first data interfaces into 1 path of data, carrying out intermediate frequency operation processing on the 1 path of data by adopting the group of first processors which can be programmed by software in a segmented mode, and carrying out time division demultiplexing on the 1 path of data after the operation processing into data of m second data interfaces so as to realize the sending processing of the data; and the receiving channel comprises a group of second processors which can be programmed by software and is used for time division multiplexing the k paths of data acquired through the k third data interfaces into 1 path of data, carrying out intermediate frequency operation processing on the 1 path of data by sections by adopting the group of second processors which can be programmed by software, and carrying out time division demultiplexing on the 1 path of data after operation processing into data of k fourth data interfaces so as to realize the receiving processing of the data.

Description

Multi-channel intermediate frequency digital signal processing device and method

Technical Field

The present application relates to the field of digital signal processing technologies, and in particular, to a multi-channel intermediate frequency digital signal processing apparatus and method.

Background

Intermediate frequency digital signal processing has unique advantages over analog signal processing and is now also widely used in the field of wireless communications.

In the related art, there are various circuit structures for realizing multi-channel intermediate frequency digital signal processing, one of them is to adopt a Digital Signal Processing (DSP) chip, and because of aiming at multi-channel data, each channel needs to be realized by adopting a group of DSP chip arrays, the structure is relatively complex, and the power consumption is large.

Disclosure of Invention

In view of the above, the present application is directed to overcoming the deficiencies of the prior art and providing a multi-channel if digital signal processing apparatus and method.

In order to achieve the purpose, the following technical scheme is adopted in the application:

a multi-channel intermediate frequency digital signal processing apparatus, comprising: a transmitting channel and a receiving channel;

the sending channel is provided with m first data interfaces and m second data interfaces, comprises a group of first processors capable of being programmed by software, and is used for carrying out time division multiplexing on m paths of data acquired through the m first data interfaces into 1 path of data, carrying out intermediate frequency operation processing on the 1 path of data by sections by adopting the group of first processors capable of being programmed by software, carrying out time division demultiplexing on the 1 path of data after the operation processing into data of the m second data interfaces, and realizing the sending processing of the data;

the receiving channel is provided with k third data interfaces and k fourth data interfaces, and comprises a group of second processors which can be programmed by software and are used for time division multiplexing k paths of data acquired through the k third data interfaces into 1 path of data, the group of second processors which can be programmed by software is adopted to carry out intermediate frequency operation processing on the 1 path of data in a segmentation mode, and the 1 path of data after operation processing is subjected to time division demultiplexing into data of the k fourth data interfaces, so that the receiving processing of the data is realized.

A multi-channel intermediate frequency digital signal processing method applied to a multi-channel intermediate frequency digital signal processing device according to any one of the above, the method comprising:

the sending channel time-division multiplexes m paths of data acquired through m first data interfaces into 1 path of data, a group of first processors which can be programmed by software are adopted to perform intermediate frequency operation processing on the 1 path of data in a segmented mode, and the 1 path of data after operation processing is time-division demultiplexed into data of m second data interfaces, so that the sending processing of the data is realized;

the receiving channel time-division multiplexes k paths of data acquired through k third data interfaces into 1 path of data, a group of second processors which can be programmed by software is adopted to perform intermediate frequency operation processing on the 1 path of data in a segmented mode, and the 1 path of data after operation processing is time-division demultiplexed into data of k fourth data interfaces, so that data receiving processing is achieved.

The technical scheme provided by the application can comprise the following beneficial effects: in the scheme provided by the application, when data is transmitted, m paths of data acquired through m first data interfaces can be subjected to time division multiplexing processing based on a group of hardware circuits of a transmitting channel, m paths of data can be subjected to time division multiplexing intermediate frequency operation processing by adopting a group of DSP processors capable of being programmed by software, 1 path of data of a transmitting and reading interface can be subjected to time division multiplexing processing into data of m third data interfaces, and data transmitting processing is realized. Furthermore, only one group of programmable first processors of software are adopted to realize the digital signal arithmetic operation of the multi-path high-speed data flow, and the software modification of the first processors can be used for modifying and upgrading the arithmetic operation, so that compared with the mode that only 1 path of high-speed data flow can be processed and modified in the related technology, the processing capability of the data flow is improved, the scale of the algorithm path capable of being modified and upgraded is enlarged, and the flexibility of a hardware circuit is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a multi-channel if digital signal processing apparatus according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of a transmission channel according to another embodiment of the present application.

Fig. 3 is a schematic partial structural diagram of a transmission channel according to another embodiment of the present application.

Fig. 4 is a schematic partial structural diagram of a transmission channel according to another embodiment of the present application.

Fig. 5 is a schematic structural diagram of a receiving channel according to another embodiment of the present application.

Fig. 6 is a partial structural schematic diagram of a receiving channel according to another embodiment of the present application.

Fig. 7 is a partial structural schematic diagram of a receiving channel according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a multi-channel if digital signal processing apparatus according to an embodiment of the present application.

As shown in fig. 1, the multi-channel if digital signal processing apparatus 100 provided in this embodiment includes: a transmit channel 110 and a receive channel 120;

the sending channel 110 has m first data interfaces and m second data interfaces, and includes a group of first processors programmable by software, and is configured to time-division multiplex m channels of data acquired through the m first data interfaces into 1 channel of data, perform intermediate frequency operation on 1 channel of data by segments by using the group of first processors programmable by software, and time-division demultiplex 1 channel of data after the operation into data of the m second data interfaces, thereby implementing sending processing of data;

the receiving channel 120 has k third data interfaces and k fourth data interfaces, and includes a set of second processors programmable by software, and is configured to time-division multiplex k channels of data acquired through the k third data interfaces into 1 channel of data, perform intermediate frequency operation on the 1 channel of data segments by using the set of second processors programmable by software, and time-division demultiplex the 1 channel of data after the operation processing into data of the k fourth data interfaces, thereby implementing the receiving processing of data.

The received and transmitted data may be, but is not limited to, IQ data of an intermediate frequency digital signal, I is in-phase, q is quadrature, and the IQ data is data divided into two paths, where the two paths of carriers are orthogonal to each other.

Wherein, m and k are positive integers, and the specific number of paths can be set according to actual needs.

The step of performing intermediate frequency operation in a segmented manner means that only a certain number of data are cached and processed each time, and the number of the data in each time is set according to actual needs.

Time division multiplexing is the transmission of different signals in different time periods of the same physical connection, and can also achieve the purpose of multiplex transmission. The applicant provides a scheme of the present application by skillfully utilizing the characteristic of time division multiplexing in combination with a software programmable processor, wherein when data is transmitted, m paths of data are acquired through m first data interfaces and subjected to time division multiplexing processing, a set of software programmable DSP processors are used for performing time division multiplexing intermediate frequency operation processing on the m paths of data, 1 path of data of a transmitting and reading interface is subjected to time division demultiplexing into data of m second data interfaces, and similarly, when data is received, k paths of data acquired through k third data interfaces can be subjected to time division multiplexing processing based on the set of hardware circuits of a receiving channel, the k paths of data are subjected to time division multiplexing intermediate frequency operation processing by using the set of software programmable DSP processors, the k paths of data are subjected to time division demultiplexing into data of k fourth data interfaces based on the set of hardware circuits of the receiving channel, and received data is received, that the received data is processed, that hardware logic control circuit and the first set of hardware processors are used for performing time division multiplexing intermediate frequency operation processing on the k paths of data, and the hardware logic control circuit are applicable to a plurality of hardware processing.

There are various specific implementations of the sending channel and the receiving channel, and the specific implementations of the sending channel and the receiving channel are illustrated below.

A sending channel:

in some embodiments, as shown in fig. 2, the transmission channel 110 further includes a first Double Data Rate (DDR) controller 111, a first cache module 112 and a first load module 113 connected to the first DDR controller 111, and an N + 1-way first DDR memory 115; the group of first processors programmable by software includes N paths of the first processors 114, where N is a positive integer greater than 1;

the first DDR controller 111 is also connected to the N first processors 114; the nth path of the first processor 114 corresponds to the nth path and the (N + 1) th path of the first DDR memory 115, and the value of N is 1,2, \8230;, N;

each path of the first DDR memory 115 is provided with m paths of DDR memory areas (which may also be referred to as memory areas for short, and are represented by different fills in the figure), wherein the xth path of DDR memory areas is used for storing a certain number of processing data corresponding to the xth path of data, and the value of x is 1,2, \ 8230;, m;

the first DDR controller 111 is configured to write data of the xth cache area in the first cache module into the xth DDR storage area in the 1 st DDR memory; aiming at a plurality of processing links required by m-path data, polling and gating channels of a first processor and a first DDR memory required by each processing link; after the channels of the 1 st path of first processor and the 1 st path of first DDR memory required by the first processing link are gated, the channels of the 1 st path of first processor and the 2 nd path of first DDR memory are gated, so that the 1 st path of first processor reads and processes the 1 st path and the 2 nd path of data in the 1 st path of first DDR memory in turn, wherein the 8230is formed by reading a certain number of data in the mth path of memory area and writing a certain number of data in the processed xth path of memory area into the xth path of DDR memory area in the 2 nd path of first DDR memory; starting from the second processing link, after the channel of the nth path of first processor and the nth path of first DDR memory required by the current processing link is gated, the channel of the nth path of first processor and the channel of the n +1 path of first DDR memory are gated, so that the nth path of first processor reads and processes the 1 st path, the 2 nd path, the 8230, the m path of storage area with a certain number of data in the nth path of first DDR memory in turn, and then the processed data of the xth path of storage area with a certain number of data is written into the xth path of DDR storage area in the n +1 path of first DDR memory;

the first loading module 113 is provided with m loading areas for loading m ways of data with a certain number in the first DDR memory (i.e., the N +1 way first DDR memory) written in at the last processing link, where the x way loading area is used for loading the x way data, aligning the loaded m ways of data, and then sending the aligned data.

Each DDR storage area in the first DDR memory may be a hardware memory, or may be a different storage space of a hardware memory.

Each first processor has different intermediate frequency Digital signal operation processing (i.e., intermediate frequency operation processing) functions, and can perform different operation processing on data, and specific operation processing functions can be set according to actual needs, for example, the functions may include Root Raised Cosine roll-off (RRC) filtering, interpolation (inter) filtering, frequency point Correction (frequency Correction, FC) and Crest Factor Reduction (CFR) processing, digital predistortion (Digital Pre-Distortion, DPD), modulation enhancement processing (enhanced modulation Process, EMP) and Quadrature Modulation Correction (QMC) IQ signal Correction and cable noise compensation (SINC). In this embodiment, each first processor reads each path of data with a certain number in a time-sharing manner for processing, writes the processed data into the corresponding storage area for temporary storage, and performs the processing of the next data with a certain number, and this is repeated.

In some embodiments, optionally, the first DDR controller is specifically configured to:

after the data writing of the x-th path of DDR storage area in the n-th path of first DDR storage is finished, outputting read [ x ] =1 to mark that the data reading of the x-th path of storage area in the n-th path of first DDR storage is effective, so that when the n-th path of first processor detects the read [ x ] =1 of the n-th path of first DDR storage, sending a read request to the first DDR controller;

when a read request of the nth path of first processor is received, gating the nth path of first DDR memory and the nth path of channel of the first processor so that the nth path of first processor can read and process a certain number of data of the xth path of DDR memory area of the nth path of first DDR memory;

when a certain number of data in the x-th path of DDR storage area in the n-th path of first DDR memory is read, outputting write ready [ x ] =1 to mark that write data in the x-th path of storage area in the n-th path of first DDR memory is valid, so that the first cache module sends a write request to the first DDR controller when detecting that the write ready [ x ] =1 of the 1-th path of first DDR memory is detected by the first processor or when detecting that the write ready [ x ] =1 of the n + 1-th path of first DDR memory is detected by the first processor;

when a write request of a first cache module is received, writing a certain number of data of an x-way cache area into an x-way DDR storage area in a 1-way first DDR memory according to the x-way write request;

when a write request of the nth path of first processor is received, gating the (n + 1) th path of first DDR memory and the nth path of channel of first processor, so that the nth path of first processor writes the processed xth path of data with a certain number into the xth path of storage area of the (n + 1) th path of first DDR memory; when the data writing of the x-th DDR storage area in the N + 1-th DDR memory is finished, outputting read [ x ] =1 to the N + 1-th first processor or the first loading module to mark the x-th storage area in the N + 1-th DDR memory to read data effectively, so that when the N + 1-th first processor detects the read ready [ x ] =1 of the N + 1-th DDR memory, sending a read request to the first DDR controller, and when the first loading module detects the read ready [ x ] =1 of the N + 1-th DDR memory, sending a read request to the first DDR controller;

and when a read request of the first loading module is received, reading the xth path of data with a certain number in the (N + 1) th path of first DDR memory according to the xth path of read request and outputting the xth path of data to the first loading module so as to write the xth path of data into the loading area.

For example, it is assumed that there are 5 first DDR memories, where after the first DDR memory in the 1 st way finishes writing data, read [ x ] =1 is output to the first cache module, after the first DDR memory in the 2 nd way finishes writing data, read [ x ] =1 is output to the first processor in the 2 nd way, after the first DDR memory in the 3 rd way finishes writing data, read [ x ] =1 is output to the first processor in the 3 rd way, after the first DDR memory in the 4 th way finishes writing data, read [ x ] =1 is output to the first processor in the 4 th way, and after the first DDR memory in the 5 th way finishes writing data, read [ x ] =1 is output to the first load module.

In some embodiments, as shown in fig. 3, the first cache module 112 includes a cache 1121 provided with m-way cache queues FIFO and a FIFO controller 1122 corresponding to the cache, where one FIFO occupies one cache region (the m-way cache regions are represented by different fills in fig. 3), and an x-th way FIFO in the m-way cache queues FIFO is used for caching an x-th way data in the m-way data;

when the difference value between the writing address and the reading address of the Xth-path FIFO in the buffer is larger than a first preset value level1, rd _ valid [ x ] =1 is output to mark the validity of the Xth-path FIFO reading data, and the preset value level1 is required to be larger than or equal to 1 and smaller than the depth of the FIFO;

when the FIFO controller corresponding to the buffer detects that the write ready [ x ] =1 output by the first DDR controller aiming at the 1 st path of first DDR memory is used for marking that the write data of the xth storage area in the 1 st path of first DDR memory is valid, and RD _ valid [ x ] =1 of the xth path of FIFO, the read module FIFO RD of the xth path of FIFO outputs RD =1 to mark that the read request of the xth path of FIFO is valid, the FIFO controller corresponding to the buffer reads a certain number of data of the xth path of FIFO, and then multiplexes the low-speed data time sequence read by the m paths of buffer queue FIFO into 1 path of high-speed data time sequence, converts the data time sequence into the write data time sequence, and outputs the write request to the first DDR controller;

correspondingly, when the cached data is read and written into the DDR memory, the first DDR controller is specifically configured to, if a write request of the FIFO controller corresponding to the buffer is received, write ready [ x ] =1 corresponding to the first DDR memory in the 1 st way and read rd _ valid [ x ] =1 of the FIFO in the x way in the buffer, write a certain number of data in the FIFO in the x way in the buffer into the DDR storage area in the x way of the first DDR memory; if a write request of the FIFO controller corresponding to the buffer is received, and a read request of the 1 st path of first processor to the 1 st path of first DDR memory is received, and the read ready =1 corresponding to any one path of memory area of the 1 st path of first DDR memory is received, the write ready =0 of all paths of memory areas of the 1 st path of first DDR memory is set to mark that write data is invalid to represent that the 1 st path of first DDR memory cannot write data at the moment, so as to inform the FIFO controller corresponding to the buffer to suspend writing data, and the counter-pressure FIFO RD =0 is output to mark that the current x path of FIFO cannot read data to suspend reading FIFO data, and after the read operation of the 1 st path of first DDR memory by the 1 st path of first processor is completed, the FIFO controller corresponding to the buffer is informed to resume writing data according to the write ready [ x ] state of each path of memory area of the 1 st path of first DDR memory.

In some embodiments, as shown in fig. 4, the first loading module 113 includes a loader 1131 provided with m loading queue FIFOs and a FIFO controller 1132 corresponding to the loader, where one FIFO occupies one loading area (the m loading areas are represented by different fills in fig. 4), and an xth FIFO in the m loading queue FIFOs is used for loading xth data in the m data;

when the difference value between the write address and the read address of each path of FIFO in the loader is greater than a first preset value full1, each path of output RD _ valid [ x ] =1 to mark that the read data of each path of FIFO is valid, and when each path of FIFO outputs the moment that the read data is valid, the FIFO controller corresponding to the loader controls the read module FIFO RD of each path of FIFO to output RD =1 to mark that the read command to the x path of FIFO is valid, so that each path of FIFO aligns the read data and transmits the read data at the same time; when the difference value of the write address and the read address of each path of FIFO in the loader is less than a second preset value empty1, outputting wr _ valid [ x ] =1 by each path to mark that each path of FIFO write data is valid, full1 is greater than or equal to the preset value empty1, and full1 is less than the depth of the FIFO;

when the FIFO controller corresponding to the loader detects that the read ready [ x ] =1 output by the first DDR controller aiming at the (N + 1) th path of first DDR memory is used for marking that the read data of the x-th storage area in the (N + 1) th path of first DDR memory is valid, and the WR _ valid [ x ] =1 of the x-th path of FIFO is used, the WR of the write module of the x-th path of FIFO outputs WR =1 to mark that the write request to the x-th path of FIFO is valid, the FIFO controller corresponding to the loader outputs the read request to the first DDR controller and reads a certain number of data in the x-th path of storage area of the (N + 1) path of first DDR memory, demultiplexes the 1-path high-speed read data time sequence from the first DDR controller into the m-path low-speed data time sequence, converts the m-path low-speed data time sequence into the write data time sequence, outputs the write data sequence to each path of FIFO, and writes the read data into each path of FIFO;

correspondingly, when a certain number of data of the first DDR memory is read and written into the FIFO, the first DDR controller is specifically configured to read and output a certain number of data in the xth path storage area of the N +1 th path first DDR memory to the FIFO controller corresponding to the loader if a read request of the FIFO controller corresponding to the loader for the (N + 1) th path first DDR memory is received, and the read ready [ x ] corresponding to the (N + 1) th path first DDR memory and the wr _ valid [ x ] write of the xth path FIFO of the loader are not= 1; if a write request of the N-th first processor to the N + 1-th first DDR memory is received when a read request of the FIFO controller corresponding to the loader to the N + 1-th first DDR memory is received, and the write ready =1 of any one storage area of the N + 1-th first DDR memory is received, the read ready =0 of all storage areas of the N + 1-th first DDR memory is set to mark that the read data is invalid to represent that the N + 1-th first DDR memory cannot read data at the moment, the FIFO controller corresponding to the loader is informed to suspend reading the data, the WR of the write module outputs WR =0 to mark that the x-th FIFO cannot write the data at the moment, the writing of the data to the x-th first memory is suspended, and after the write operation of the N-th first processor to the N + 1-th first DDR memory is completed, the FIFO controller corresponding to the loader is informed to resume reading the data according to the read ready [ x ] state of each storage area of the N + 1-th first DDR memory.

In an embodiment of the transmit channel, level1> t,1< = t < = d, d is the FIFO depth, t = r is the number of beats of a clock cycle for writing data into the DDR memory, and r is the number of data lanes (i.e., the number of lanes currently strobed by the DDR controller). And each way RD _ valid [ x ] =1 is valid at the same time, and each way of FIFO RD outputs RD =1 at the same time, so that each way of FIFO RD is guaranteed to align output data at the same time.

full1 is a full waterline, and the write address wr > = full1 represents an exception.

The clock for reading data from the first DDR memory is clk _ out, and is a high-speed clock; the FIFO write data clock is clk _ in, the FIFO read data clock is clk _ rd, and the clocks are all low speed clocks.

Wherein the frequency of clk _ out is greater than or equal to the frequency of N clk _ in.

Wherein the frequency of clk _ in is greater than or equal to the frequency of z × clk _ rd.

Z is greater than or equal to N (the first processor reads 1 path of data with a certain number from the first DDR memory and writes in the DDR memory with a certain number of data period value +1 path of data with a certain number of data period value + margin period value)/1 path of data with a certain number of data period value 1 beat clock period value, that is, the write module WR writes in the FIFO data at a rate greater than or equal to the FIFO RD read FIFO data rate, so the beat number of the clock period in which the FIFO controller reads 1 path of data and writes in the DDR memory is less than or equal to the beat number of the clock period in which the first processor finishes processing 1 path of data + the beat number (N-1) of the clock period in which the first processor reads and writes in 1 path of data to the first DDR memory.

In the above embodiments, a detailed description is given to a specific control strategy for cooperation of the first DDR controller, the first processor, the first loading module, and the first cache module.

The first processor may be implemented by, but not limited to, a Digital Signal Processing (DSP) chip, for example, a DSP chip of a model TMS320C 7768.

In the related art, an Application Specific Integrated Circuit (ASIC) digital chip is used to implement a digital intermediate frequency processing function of wireless or microwave communication, multiple carriers need to be implemented by using multiple sets of the same digital circuits, and once the ASIC chip is put into production, the carrier cannot be modified, so that the flexibility and expansibility are insufficient, the channel and the medium radio frequency channel cannot be adapted to change, only a new generation of chip can be invested, and time and money are wasted. In addition, the related art also uses a Field Programmable Gate Array (FPGA) chip to implement the wireless or microwave communication digital intermediate frequency processing function, although modifications can be made, the multi-path digital intermediate frequency logic circuit has a large scale, the cost and power consumption of the required FPGA chip are increased very high, and at the same time, the related art is limited by the existing FPGA technology level, the clock frequency and part of the key modules such as Serdes, ARM, ADC/DAC, etc. are limited, and the specification of some high-speed data stream processing is difficult to implement. Although there is a method for realizing wireless or microwave communication digital intermediate frequency processing function by using DSP chip, each channel needs to be realized by using a group of DSP chip array, and the DSP chip has a large number, large power consumption, high cost and large circuit single board area.

In the scheme of the application, the single-group DSP chip array is adopted, the advantage of DSP chip processing performance is utilized, and the scheme of a peripheral hardware logic control circuit and a multi-DDR controller circuit is combined in a time division multiplexing mode to realize multi-path or multi-carrier wireless or microwave communication digital intermediate frequency processing. On one hand, the DSP chip is adopted to realize programmable logic function, modifiable and upgradable, the DSP chip can flexibly deal with the change of a transmission channel and a physical channel, the redevelopment of the chip caused by design error and requirement change can not occur, on the other hand, a plurality of intermediate frequency processing can be realized according to the operation processing performance of the DSP chip, a plurality of fixed hardware logic circuits are not required to be designed, the realization difficulty of the chip is reduced, the chip cost and the power consumption are reduced, the design of an algorithm and the logic circuit are separated and developed simultaneously, the development period of the chip is shortened, on the other hand, a single-group DSP chip array time division multiplexing control method is adopted, compared with the method that a plurality of groups of DSP chip arrays are directly adopted for parallel processing, the number of the DSP chips is reduced, and the total realization cost is reduced.

Receiving a channel:

in some embodiments, as shown in fig. 5, optionally, the receiving channel 120 further includes a second DDR controller 121, a second cache module 122 and a second loading module 123 connected to the second DDR controller, and a P + 1-way second DDR memory 125; the set of second processors that can be programmed by software includes a P-way second processor 124, where P is a positive integer greater than 1;

the second DDR controller is also connected with the P path second processor 124; the second processor of the P-th path corresponds to the second DDR memories of the P-th path and the P + 1-th path, and the value of P is 1,2, \ 8230;, P;

each path of second DDR memory is provided with k paths of DDR memory areas (shown by different fillings in the figure), wherein the y path of DDR memory areas are used for storing processing data corresponding to the y path of data, and the value of y is 1,2, \8230;, k;

the second DDR controller 121 is configured to write a certain number of data in the y-th cache area in the second cache module into the y-th DDR storage area in the 1 st DDR memory; aiming at a plurality of processing links required by k paths of data, polling and gating channels of a second processor and a second DDR memory required by each processing link; after the channels of the 1 st path of second processor and the 1 st path of second DDR memory required by the first processing link are gated, the channels of the 1 st path of second processor and the 2 nd path of second DDR memory are gated, so that the 1 st path of second processor reads and processes the 1 st path and the 2 nd path of data in the 1 st path of second DDR memory in turn, wherein, the 8230is provided, the kth path has a certain number of data of a storage area, and then the processed yth path has a certain number of data of a storage area of the yth path and is written into the yth path of DDR storage area in the 2 nd path of second DDR memory; starting from the second processing link, after gating the channels of the p-th path of second processor and the p-th path of second DDR memory required by the current processing link, gating the channels of the p-th path of second processor and the p + 1-th path of second DDR memory so that the p-th path of second processor reads and processes the 1 st path, the 2 nd path, the 8230, the k-th path of storage area with a certain number of data in the p-th path of second DDR memory in turn, and then writing the processed y-th path of storage area with a certain number of data into the y-th path of DDR storage area in the p + 1-th path of second DDR memory;

the second loading module 123 is provided with k loading areas for loading k ways of data with a certain number in the second DDR memory (i.e., the P +1 th way second DDR memory) written in when the last two processing links are performed, where the y loading area is used for loading the y way of data, aligning each way of loaded k ways of data, and then sending the aligned way of data.

In some embodiments, the second DDR controller is specifically configured to:

when data writing of a certain number of data in the y-th DDR storage area in the p-th second DDR memory is finished, reading y [ y ] =1 is output to mark that the data reading of the y-th storage area in the p-th second DDR memory is valid, so that a reading request is sent to the second DDR controller when the p-th second processor detects that the reading y [ y ] =1 of the p-th second DDR memory is detected;

when a reading request of the p path of second processor is received, gating the p path of second DDR memory and the p path of channel of second processor, so that the p path of second processor reads and processes a certain number of data of the y path of DDR memory area of the p path of second DDR memory;

when a certain number of data in the y-th path of DDR storage area in the p-th path of the second DDR memory is read, outputting write ready [ y ] =1 to mark that the y-th path of storage area in the p-th path of the second DDR memory is valid for writing data, so that the second cache module sends a write request to the second DDR controller when detecting that write ready [ x ] =1 of the 1-th path of second DDR memory is detected or that the p-th path of second processor detects that write ready [ y ] =1 of the p + 1-th path of second DDR memory is detected;

when a write request of a second cache module is received, writing a certain number of data of a y-th cache area into a y-th DDR storage area in a 1-th second DDR memory according to a y-th write request;

when a write request of the p path of second processor is received, gating the p +1 path of second DDR memory and the p path of second processor, so that the p path of second processor writes the processed y path of data with a certain number into the y path of storage area of the p +1 path of second DDR memory;

after the data writing of the y-th DDR storage area in the P + 1-th second DDR memory is finished, outputting read [ y ] =1 to the P + 1-th second processor or a second loading module to mark that the y-th storage area in the P + 1-th second DDR memory is read effectively, so that the P + 1-th second processor sends a read request to a second DDR controller when detecting that the read [ y ] =1 of the P + 1-th second DDR memory is detected, and the second loading module sends a read request to the second DDR controller when detecting that the read [ y ] =1 of the P + 1-th second DDR memory is detected;

and when a read request of the second loading module is received, reading a certain number of the y-th path of data of the P + 1-th path of second DDR memory according to the y-th path of read request, and outputting the data to the second loading module so as to write the data into the y-th path of loading area.

For example, it is assumed that there are 5 ways of second DDR memories, where after the data writing of the 1 st way of second DDR memory is completed, read [ x ] =1 is output to the second cache module, after the data writing of the 2 nd way of second DDR memory is completed, read [ x ] =1 is output to the 2 nd way of second processor, after the data writing of the 3 rd way of second DDR memory is completed, read [ x ] =1 is output to the 3 rd way of second processor, after the data writing of the 4 th way of second DDR memory is completed, read [ x ] =1 is output to the 4 th way of second processor, and after the data writing of the 5 th way of second DDR memory is completed, read [ x ] =1 is output to the second load module.

In some embodiments, as shown in fig. 6, optionally, the second buffer module 122 includes a buffer 1221 provided with k-way buffer queues, and a corresponding FIFO controller 1222 for the buffer, where one FIFO occupies one buffer (the k-way buffer is represented by different fills in fig. 6), and the y-th way FIFO in the k-way buffer queues is used for buffering the y-th way data in the k-way data;

when the difference value of the write address and the read address of the y-way FIFO in the buffer is greater than a second preset value level2, outputting rd _ valid [ y ] =1 to mark that the y-way FIFO reads data effectively, wherein the level2 is required to be greater than or equal to 1 and is less than the depth of the FIFO;

when the FIFO controller corresponding to the buffer detects that the write ready [ y ] =1 output by the second DDR controller aiming at the 1 st path of second DDR memory is used for marking that the write data of the yth storage area in the 1 st path of second DDR memory is valid, and RD _ valid [ y ] =1 of the yth path of FIFO, the read module FIFO RD of the yth path of FIFO outputs RD =1 to mark that the read request of the yth path of FIFO is valid, the FIFO controller corresponding to the buffer reads a certain number of data of the yth path of FIFO, multiplexes the time sequence of the low-speed data read from the k path of cache queue FIFO into the time sequence of the 1 path of high-speed data, converts the data sequence into the time sequence of the write data, and outputs the write request to the second DDR controller;

correspondingly, when a certain number of data in the read cache is written into the DDR memory, the second DDR controller is specifically configured to, if a write request of the FIFO controller corresponding to the cache is received, write ready [ y ] =1 corresponding to the second DDR memory in the 1 st way and read rd _ valid [ y ] =1 of the FIFO in the y way in the cache, write a certain number of data in the FIFO in the y way in the cache into the DDR storage area in the y way of the second DDR memory; if a write request of the FIFO controller corresponding to the buffer is received, and a read request of the 1 st path of second processor to the 1 st path of second DDR memory is received, and the read ready =1 corresponding to any path of storage area of the 1 st path of second DDR memory is received, the write ready =0 of all paths of storage areas of the 1 st path of second DDR memory is set to mark that write data is invalid to represent that the 1 st path of second DDR memory cannot write data at the moment so as to inform the FIFO controller corresponding to the buffer to suspend writing data, the backpressure FIFO RD =0 is output to mark that the current y path of FIFO cannot read data so as to suspend reading the FIFO data, and after the read operation of the 1 st path of second DDR memory by the 1 st path of second processor is completed, the FIFO controller corresponding to the buffer is informed to resume writing data according to the write ready [ y ] state of each path of storage area of the 1 st path of second DDR memory.

In some embodiments, as shown in fig. 7, optionally, the second loading module 123 includes a loader 1231 provided with k loading queues FIFO and a FIFO controller 1232 corresponding to the loader, where one FIFO occupies one loading area (in fig. 7, the k loading areas are embodied by different fills), and the y-th FIFO in the k loading queues is used to load the y-th data in the k data;

when the difference value between the write address and the read address of each path of FIFO in the loader is greater than a third preset value full2, each path of output RD _ valid [ y ] =1 to mark that the read data of each path of FIFO is valid, and when each path of FIFO outputs the moment that the read data is valid, the FIFO controller corresponding to the loader controls the read module FIFO RD of each path of FIFO to output RD =1 to mark that the read command to the y path of FIFO is valid, so that each path of FIFO aligns the read data and transmits the read data at the same time; when the difference value of the write address and the read address of each path of FIFO in the loader is less than a fourth preset value empty2, outputting wr _ valid [ y ] =1 by each path to mark that each path of FIFO write data is valid, full2 needs to be greater than or equal to empty2, and full2 needs to be less than the depth of the FIFO;

when the FIFO controller corresponding to the loader detects that the read ready [ y ] =1 output by the second DDR controller aiming at the P +1 th path of second DDR memory is used for marking that the read data of the y storage area in the P +1 th path of second DDR memory is valid, and the WR _ valid [ y ] =1 of the y path of FIFO is used, the write module FIFO WR of the y path of FIFO outputs WR =1 to mark that the write request to the y path of FIFO is valid, the FIFO controller corresponding to the loader outputs the read request to the second DDR controller and reads a certain number of data of the y storage area of the P +1 path of second DDR memory, then demultiplexes the 1 path high speed read data time sequence from the second DDR controller into the k path low speed data time sequence, converts the write data time sequence to be output to each path of FIFO, and writes the read data to each path of FIFO;

correspondingly, when a certain number of data of the second DDR memory is read and written into the FIFO, the second DDR controller is specifically configured to read and output a certain number of data of the y-th storage area of the P + 1-th path second DDR memory to the FIFO controller corresponding to the loader if a read request of the FIFO controller corresponding to the loader for the P + 1-th path second DDR memory is received, and when the read ready [ y ] = 1-th path FIFO write wr _ valid [ y ] = 1-th path of the second loader is written; if a read request of the FIFO controller corresponding to the loader for the P +1 th path of second DDR memory is received, a write request of the P +1 th path of second DDR memory from the second processor is received, and the write ready =1 of any one path of storage area of the P +1 th path of second DDR memory is set, the read ready =0 of all storage areas of the P +1 th path of second DDR memory is set to mark that the read data is invalid to represent that the P +1 th path of second DDR memory is unreadable at the moment, the FIFO controller is informed to suspend reading data, the WR output WR =0 of the write module marks that the y path of FIFO is not writable at the moment, writing of data into the y path of FIFO is suspended, and after the write operation of the P +1 th path of second DDR memory from the P +1 th path of second processor is completed, the FIFO controller is informed to resume reading data according to the read ready [ y ] state of each path of storage area of the P +1 th path of second DDR memory.

Similarly, in the embodiment of the receiving channel, level2> t,1< = t < = d, d is the depth of the FIFO, t = r is the number of beats per clock cycle of writing data into the second DDR memory, and r is the number of data lanes (i.e., the number of lanes currently strobed by the DDR controller). And each way RD _ valid [ y ] =1 is valid at the same time, and each way of FIFO RD outputs RD =1 at the same time, so that each way of FIFO RD is guaranteed to align output data at the same time.

Full2 is Full waterline, and the write address wr > = Full1 represents exception. The clock for reading data from the second DDR memory is clk _ out, and is a high-speed clock; the FIFO write data clock is clk _ in, the FIFO read data clock is clk _ rd, and the clocks are low-speed clocks.

Wherein the frequency of clk _ out is greater than or equal to the frequency of P clk _ in.

Wherein, z is greater than or equal to P (the second processor reads 1 path of data with a certain number from the second DDR memory and writes into the DDR memory the required clock period value +1 path of data with a certain number the number of data 1 beat clock period value + margin period value)/1 path of data with a certain number the number of data 1 beat clock period value, that is, the write module WR writes in the FIFO data at a rate greater than the FIFO RD read FIFO data rate, so the number of beats of the clock period at which the FIFO controller reads 1 path of data and writes into the DDR memory is less than or equal to the number of beats of the clock period at which the second processor has finished processing 1 path of data P + the number of beats of the clock period at which the second processor reads and writes 1 path of data into the second DDR memory (P-1).

In the above embodiments, a detailed description is given to a specific control strategy for cooperation of the second DDR controller, the second processor, the second loading module, and the second cache module. In addition, the specific implementation may be implemented with reference to the above transmission channel, and is not described in detail here.

The following may exemplify the scheme of the present application through a specific application scenario.

In the scenario of this embodiment, a single group of 5 pieces of DSP chips with a model of TMS320C7768 are used as 5 first processors in a transmission channel, and 5 pieces of DSP chips are allocated to respectively complete RRC filtering, inter filtering, FC and CFR processing, DPD, EMP, QMC IQ signal correction, and SINC functions. That is, the value of N in the transmission channel is 5, and correspondingly, the number of the first DDR memory ways in the transmission channel is 6.

Data can be acquired through a plurality of MAP constellation mapping modules, and if MAP1 and MAP2 output two paths of IQ data to a first cache module, that is, the value of m is 2, correspondingly, FIFO1 and FIFO2 are arranged in the first cache module as cache regions, FIFO1 and FIFO2 are arranged in a first loading module as loading regions, and each path of first DDR memory is provided with a DDR storage region 1 and a DDR storage region 2.

The clock cycle of 16-bit I and Q data output by the logic circuit MAP constellation mapping module is 25ns, the rate of corresponding data is 40Mbps, the read and write data clock cycle of RRC filtering is 25ns, the write data clock cycle of inter filtering is 25ns, the read data clock cycle is 12.5ns, and the read and write clock cycles of subsequent processing starting from FC are both 12.5ns. The method comprises the following steps of completing writing and reading of 1 channel 64-beat data and performing RRC filtering by matching with a first DDR controller every time, completing writing and reading of 1 channel 64-beat data and performing Interp filtering on a DSP chip 1, completing writing and reading of 1 channel 128-beat data and performing FC and CFR processing on the DSP chip 3, completing reading and writing of 1 channel 128-beat data and performing DPD on a DSP chip 4, completing writing and reading of 1 channel 128-beat data and performing EMP and QMC IQ signal correction and SINC on the DSP chip 5, and completing access operation of dual-channel data from a DSP to a first DDR memory and from the first DDR memory to the DSP chip, computing operation of 64-beat or 128-beat data on a DSP digital signal, and caching and loading operation of 64-beat or 128-beat data in 64-beat or 128-beat data clock cycles.

Based on this, the data flow of the transmission channel goes as follows: the first DDR controller multiplexes the 1 st path of data cached by the FIFO1 in the first cache module and the 2 nd path of data, and writes the multiplexed 1 st path of data and the multiplexed 2 nd path of data cached by the FIFO1 in the first cache module into a DDR storage area 1 and a DDR storage area 2 of a 1 st path of first DDR memory; the DSP chip 1 reads and processes the data of the DDR storage area 1 of the first DDR memory of the 1 st path, and then writes the data into the DDR storage area 1 of the first DDR memory of the 2 nd path, and the DSP chip 1 reads and processes the data of the DDR storage area 2 of the first DDR memory of the 1 st path, and then writes the data into the DDR storage area 2 of the first DDR memory of the 2 nd path; the DSP chip 2 reads and processes data of a DDR storage area 1 of the first DDR memory of the 2 nd path, and writes the data into a DDR storage area 1 of the first DDR memory of the 3 rd path, and the DSP chip 2 reads and processes data of a DDR storage area 2 of the first DDR memory of the 2 nd path, and writes the data into a DDR storage area 2 of the first DDR memory of the 3 rd path; the DSP chip 3 reads and processes data of a DDR storage area 1 of the first DDR memory of the 3 rd path, and writes the data into a DDR storage area 1 of the first DDR memory of the 4 th path, and the DSP chip 3 reads and processes data of a DDR storage area 2 of the first DDR memory of the 3 rd path, and writes the data into a DDR storage area 2 of the first DDR memory of the 4 th path; the DSP chip 4 reads and processes the data of the DDR storage area 1 of the first DDR memory of the 4 th path, and then writes the data into the DDR storage area 1 of the first DDR memory of the 5 th path, and the DSP chip 4 reads and processes the data of the DDR storage area 2 of the first DDR memory of the 4 th path, and then writes the data into the DDR storage area 2 of the first DDR memory of the 5 th path; the DSP chip 5 reads and processes the data of the DDR storage area 1 of the first DDR memory of the 5 th path, and then writes the data into the DDR storage area 1 of the first DDR memory of the 6 th path, and the DSP chip 5 reads and processes the data of the DDR storage area 2 of the first DDR memory of the 5 th path, and then writes the data into the DDR storage area 2 of the first DDR memory of the 6 th path; the first loading module reads data of a DDR storage area 1 and a DDR storage area 2 of a 6 th path of first DDR memory in the first DDR controller, and writes the data into a loading area 1 and a loading area 2 in the first loading module after demultiplexing. The specific implementation is not described herein again, and reference may be made to the above related embodiments of the sending channel.

The receiving channel adopts a single group of 4 DSP chips with the model of TMS320C7768, and 4 DSP chips are distributed to respectively finish the IQ signal correction of FC and QMC, the anti-aliasing filter (AAF), the inter-p filtering, the Automatic Gain Control (AGC) and the RRC processing function. The clock period of the input 16-bit I and Q data is 12.5ns, and the clock period of the data after the inter filtering is 25ns. One DSP chip realizes FC and QMC IQ signal correction and AAF processing functions, one DSP chip realizes inter filtering, one DSP chip realizes AGC, and one DSP chip realizes RRC processing functions. The specific implementation is similar to the transmission channel and will not be described in detail here.

The DSP chip internally allocates an input data cache ChlsRAM, an output data cache ChlsRAM and an intermediate result cache ChlsRsulRAM for each channel, the DSPcore reads data corresponding to external DDR of each channel according to Ready instructions and updates the read instructions to be effective, the DSPcore reads the input data in the cache and parameters in a coefficient RAM, caches the output data in the output ChlsRAM corresponding to the channel after finishing a channel data fixed-point operation such as FIR filtering, multiplication and addition operation, simultaneously stores the intermediate result data in the intermediate result data RAM of the channel, namely Chl1-nRsulRAM, and finally the DSPcore writes the result data in DDR of the external corresponding channel from the output ChlsRAM and updates the write instructions to be effective. And then the DSPcore performs the processing of the next channel according to the change of the ready signal until all the channels finish polling in sequence, and repeats the polling processing operation according to the ready instruction.

Another embodiment of the present application further provides a multi-channel if digital signal processing method, which is applied to the multi-channel if digital signal processing apparatus according to any of the above embodiments, where the method includes:

If the sending channel comprises N paths of first processors and N +1 paths of first DDR memories, serial stream processing is carried out on the 1 st to N paths of first processors and the 1 st to N paths of first DDR memories, time division multiplexing is carried out on the 1 path of data of the N +1 path of DDR memories to m third data interfaces, and parallel sending of the data of the multiple paths of data channels is achieved;

if the receiving channel comprises P paths of first processors and P +1 paths of first DDR memories, serial stream processing is carried out on the 1 st to P paths of second processors and the 1 st to P paths of second DDR memories, time division multiplexing is carried out on the 1 path of data of the P +1 path of DDR memories to k fourth data interfaces, and parallel data receiving of the multiple paths of data channels is achieved.

Aiming at a first processor of a sending channel and a second processor of a receiving channel, the number of the single channel data stored in the buffer at each time is set, so that the time value stored in the buffer is larger than the product value of the sum of the time of the processor for reading the corresponding number of data from the DDR memory, the time of the processor for operating and processing the corresponding number of data and the time of the processor for writing the corresponding number of data into the DDR memory and the number of all data channels, and the smooth data reading and writing is ensured.

The specific implementation of this embodiment may refer to the above embodiments of the multi-channel if digital signal processing apparatus to obtain the same technical effects, which are not described herein again.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried out in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

1. A multi-channel if digital signal processing apparatus, comprising: a transmitting channel and a receiving channel;

the sending channel is provided with m first data interfaces and m second data interfaces, and comprises a group of first processors which can be programmed by software and are used for carrying out time division multiplexing on m paths of data acquired through the m first data interfaces into 1 path of data, carrying out intermediate frequency operation processing on the 1 path of data by adopting the group of first processors which can be programmed by software, and carrying out time division demultiplexing on the 1 path of data which is subjected to the operation processing into data of the m second data interfaces so as to realize the sending processing of the data;

the receiving channel is provided with k third data interfaces and k fourth data interfaces, and comprises a group of second processors which can be programmed by software and are used for time division multiplexing k paths of data acquired through the k third data interfaces into 1 path of data, carrying out intermediate frequency operation processing on the 1 path of data by sections by adopting the group of second processors which can be programmed by software, and carrying out time division demultiplexing on the 1 path of data which is subjected to operation processing into data of the k fourth data interfaces so as to realize the receiving processing of the data;

the group of first processors capable of being programmed by software comprises N paths of first processors, wherein the value of N is a positive integer greater than 1; the sending channel further comprises a first DDR controller, a first cache module and a first loading module which are connected with the first DDR controller, and an N +1 path of first DDR memory;

the first DDR controller is also connected with the N paths of first processors; the nth path of first processor corresponds to the nth path of first DDR memory and the (N + 1) th path of first DDR memory, and the value of N is 1,2, \8230;

each path of the first DDR memory is provided with m paths of DDR storage areas, wherein the x path of DDR storage areas are used for storing processing data corresponding to the x path of data, and the value of x is 1,2, \ 8230;, m;

the first DDR controller is used for writing data of an x-th path cache area in the first cache module into an x-th path DDR storage area in the 1 st path DDR memory; polling and gating channels of the first processor and the first DDR memory required by each processing link aiming at a plurality of processing links required by the m-path data; after the channel of the 1 st path of the first processor and the 1 st path of the first DDR memory required by the first processing link is gated, the channel of the 1 st path of the first processor and the channel of the 2 nd path of the first DDR memory are gated, so that the 1 st path of the first processor reads and processes the 1 st path, the 2 nd path, the 8230in the 1 st path of the first DDR memory in turn, the data of the m path of storage area is \8230, and then the data of the processed x path of storage area is written into the x path of DDR storage area in the 2 nd path of the first DDR memory; starting from the second processing link, after gating the channel of the nth path of the first processor and the nth path of the first DDR memory required by the current processing link, gating the channel of the nth path of the first processor and the n +1 path of the first DDR memory so that the nth path of the first processor reads and processes the 1 st path, the 2 nd path, the 8230, the m path of the first DDR memory in turn, and then writing the processed data of the x path of the storage area into the x path of the DDR storage area in the n +1 path of the first DDR memory;

the first loading module is provided with m loading areas and is used for loading m paths of data written in the (N + 1) th path of the first DDR memory when the last processing link is processed, wherein the x path of loading area is used for loading and sending the x path of data;

the group of second processors capable of being programmed by software comprises a P path of second processors, and the value of P is a positive integer greater than 1; the receiving channel further comprises a second DDR controller, a second cache module and a second loading module which are connected with the second DDR controller, and a P +1 path second DDR memory;

the second DDR controller is also connected with a P path of second processor; the second processor of the P-th path corresponds to the second DDR memories of the P-th path and the P + 1-th path, and the value of P is 1,2, \ 8230;, P;

each path of the second DDR memory is provided with k paths of DDR storage areas, wherein the y path of DDR storage areas are used for storing processing data corresponding to the y path of data, and the value of y is 1,2, \ 8230;, k;

the second DDR controller is used for writing data of a y-th path cache area in the second cache module into a y-th path DDR storage area in the 1 st path DDR memory; polling and gating channels of the second processor and the second DDR memory required by each processing link aiming at a plurality of processing links required by the k-path data; after the channel of the 1 st path of the second processor and the 1 st path of the second DDR memory required by the first processing link are gated, the channel of the 1 st path of the second processor and the channel of the 2 nd path of the second DDR memory are gated, so that the 1 st path of the second processor reads and processes the 1 st path, the 2 nd path, the 8230, the y 8230, the data of the k path of the storage area in the 1 st path of the second DDR memory in turn, and then the processed data of the y path of the storage area is written into the y path of the DDR storage area in the 2 nd path of the second DDR memory; starting from the second processing link, after gating the channel of the second processor of the p-th path and the second DDR memory of the p-th path required by the current processing link, gating the channel of the second processor of the p-th path and the channel of the second DDR memory of the p + 1-th path, so that the second processor of the p-th path reads and processes the data of the storage area of the 1 st path, the 2 nd path, the 8230, the k path and the y path in the second DDR memory in turn, and then writing the processed data of the storage area of the y path into the DDR storage area of the y path in the second DDR memory of the p + 1-th path;

and the second loading module is provided with k paths of loading areas and is used for loading k paths of data written in the P +1 path of second DDR memory during the last two processing loops, wherein the y path of loading areas are used for loading and sending the y path of data.

2. The apparatus of claim 1, wherein the first DDR controller is specifically configured to:

when the data writing of the x-th path of DDR storage area in the n-th path of first DDR memory is finished, outputting read [ x ] =1 to mark that the x-th path of storage area in the n-th path of first DDR memory is valid to enable the n-th path of first processor to send a read request to the first DDR controller when detecting that the read [ x ] =1 of the n-th path of first DDR memory is detected;

when a read request of the nth path of the first processor is received, gating the nth path of the first DDR memory and the nth path of the channel of the first processor so that the nth path of the first processor reads and processes data of the xth path of DDR storage area of the nth path of the first DDR memory;

when data in the x-th path of DDR storage area in the n-th path of first DDR memory is read completely, outputting write ready [ x ] =1 to mark that write data in the x-th path of storage area in the n-th path of first DDR memory is valid, so that when the first cache module detects that the 1-th path of write ready [ x ] =1 of the first DDR memory is detected or the n-th path of first processor detects that the n + 1-th path of write ready [ x ] =1 of the first DDR memory is detected, sending a write request to the first DDR controller;

when a write request of the first cache module is received, writing data of an x-way cache area into an x-way DDR storage area in a 1 st-way DDR memory according to the x-way write request;

when a write request of the nth path of the first processor is received, gating the (n + 1) th path of the first DDR memory and the nth path of the channel of the first processor so that the nth path of the first processor writes processed data of the x path into the (n + 1) th path of storage area of the first DDR memory; when the data writing of the x-th DDR storage area in the N + 1-th DDR memory is finished, outputting read [ x ] =1 to the N + 1-th first processor or the first loading module to mark the x-th storage area in the N + 1-th DDR memory to read data effectively, so that when the N + 1-th first processor detects the read ready [ x ] =1 of the N + 1-th DDR memory, sending a read request to the first DDR controller, and when the first loading module detects the read ready [ x ] =1 of the N + 1-th DDR memory, sending a read request to the first DDR controller;

and when the read request of the first loading module is received, reading the x path of data in the (N + 1) th path of the first DDR memory according to the x path of read request and outputting the x path of data to the first loading module.

3. The device according to claim 1, wherein the first buffer module comprises a buffer provided with m-way buffer queues and a FIFO controller corresponding to the buffer, wherein one FIFO occupies one buffer area, and the x-th way FIFO in the m-way buffer queues is used for buffering the x-th way data in the m-way data;

when the difference value between the write address and the read address of the xth path FIFO in the buffer is greater than a first preset value level1, rd _ valid [ x ] =1 is output to mark that the xth path FIFO reads effective data, and the level1 is greater than or equal to 1 and is less than the depth of the FIFO;

when the FIFO controller corresponding to the buffer detects that the write ready [ x ] =1 output by the first DDR controller for the 1 st path of the first DDR memory is used for marking that the write data of the xth storage area in the 1 st path of the first DDR memory is valid, and RD _ valid [ x ] =1 of the xth path of the FIFO, the read module FIFO RD of the xth path of the FIFO outputs RD =1 to mark that the read request of the xth path of the FIFO is valid, the FIFO controller corresponding to the buffer reads the data of the xth path of the FIFO, multiplexes the low-speed data time sequence read by the m paths of buffer queue FIFO into the 1 path of high-speed data time sequence, converts the data into the write data time sequence, and outputs the write request to the first DDR controller;

correspondingly, when the cached data is read and written into the DDR memory, the first DDR controller is specifically configured to, if a write request of the FIFO controller corresponding to the buffer is received, write ready [ x ] =1 corresponding to the first DDR memory in the 1 st way and read rd _ valid [ x ] =1 of the FIFO in the x way in the buffer, write the data of the FIFO in the x way in the buffer into the DDR storage area in the x way of the first DDR memory; if a write request of the FIFO controller corresponding to the buffer is received, and a 1 st read request of the first processor to the 1 st DDR memory is received, and the 1 st read =1 corresponding to any one of the first DDR memory storage areas, the write ready =0 of the 1 st storage area of the first DDR memory is set to mark that the write data is invalid to represent that the 1 st DDR memory cannot write data at the moment, so as to inform the FIFO controller corresponding to the buffer to suspend writing data, and the backpressure FIFO RD outputs RD =0 to mark that the current x-th FIFO cannot read data to suspend reading the FIFO data, and after the 1 st read operation of the first processor to the 1 st DDR memory is completed, the FIFO controller corresponding to the buffer is informed to resume writing data continuously according to the write ready [ x ] state of each storage area of the first DDR memory of the 1 st path.

4. The device according to claim 1, wherein the first loading module includes a loader provided with m-way loading queue FIFOs and a FIFO controller corresponding to the loader, wherein one FIFO occupies one loading area, and an x-th way FIFO in the m-way loading queue FIFOs is used for loading an x-th way data in the m-way data;

when the difference value between the writing address and the reading address of each path of FIFO in the loader is greater than a first preset value full1, each path of output RD _ valid [ x ] =1 to mark that each path of FIFO reading data is valid, and when each path of FIFO outputs the moment that the reading data is valid, the FIFO controller corresponding to the loader controls the reading module FIFO RD of each path of FIFO to output RD =1 to mark that a reading command for the xth path of FIFO is valid, so that each path of FIFO aligns and reads the data at the same time and sends the data; when the difference value of the write address and the read address of each path of FIFO in the loader is smaller than a second preset value empty1, outputting wr _ valid [ x ] =1 by each path to mark that each path of FIFO write data is valid, full1 is larger than or equal to empty1, and full1 is smaller than the depth of the FIFO;

when the FIFO controller corresponding to the loader detects that the read ready [ x ] =1 output by the first DDR controller for the (N + 1) th path of the first DDR memory is used for marking that the read data of the xth storage area in the (N + 1) th path of the first DDR memory is valid, and WR _ valid [ x ] =1 of the xth FIFO is used, the write module FIFO WR output WR =1 of the xth FIFO is used for marking that the write request of the xth FIFO is valid, the FIFO controller corresponding to the loader outputs a read request to the first DDR controller and reads the data of the (N + 1) th path of the xth storage area of the first DDR memory, then demultiplexes the 1-path high-speed read data time sequence from the first DDR controller into the m-path low-speed data time sequence, converts the m-path high-speed read data time sequence into a write data time sequence, outputs the write data sequence to each path of the FIFO, and writes the read data into each path of the FIFO;

correspondingly, when data of the first DDR memory is read and written into the FIFO, the first DDR controller is specifically configured to, if a read request of the FIFO controller corresponding to the loader for the N +1 th DDR memory is received, and the N +1 th read [ x ] corresponding to the first DDR memory is not equal to 1 and the xr _ valid [ x ] of the x th FIFO write of the loader is not equal to 1, read and output data of the x th storage area of the N +1 th DDR memory to the FIFO controller corresponding to the loader; if a read request of the FIFO controller corresponding to the loader to the (N + 1) th DDR memory is received, a write request of the first processor to the (N + 1) th DDR memory is received, and the write ready =1 of any storage area of the (N + 1) th DDR memory is received, the read ready =0 of all storage areas of the (N + 1) th DDR memory is set to mark that read data is invalid to represent that the (N + 1) th DDR memory is unreadable at this time, the FIFO controller corresponding to the loader is notified to suspend reading data, the FIFO WR of the write module outputs WR =0 to mark that the (x) th FIFO is unwritable at this time, writing of FIFO data to the x th path is suspended, and after the write operation of the first processor to the (N + 1) th DDR memory at the N th path is completed, the FIFO controller corresponding to the loader is notified to continue reading data according to the read ready [ x ] state of each storage area of the first memory at the (N + 1) th path according to the (N + 1) th path of the FIFO controller corresponding to resume reading data.

5. The apparatus of claim 1, wherein the second DDR controller is to:

when the data writing of the y-th path DDR memory area in the p-th path second DDR memory is finished, outputting read [ y ] =1 to mark that the data reading of the y-th path memory area in the p-th path second DDR memory is valid, so that the p-th path second processor sends a read request to the second DDR controller when detecting that the read [ y ] =1 of the p-th path second DDR memory is detected;

when a reading request of the p path of the second processor is received, gating the p path of the second DDR memory and the p path of the channel of the second processor, so that the p path of the second processor reads and processes data of the y path of DDR storage area of the p path of the second DDR memory;

when the data in the y-th path of DDR storage area in the p-th path of second DDR memory is completely read, outputting write ready [ y ] =1 to mark that the y-th path of storage area in the p-th path of second DDR memory is valid to enable the second cache module to detect that the write ready [ x ] =1 of the 1-th path of second DDR memory is detected or the p-th path of second processor detects that the write ready [ y ] =1 of the p + 1-th path of second DDR memory is detected, and sending a write request to the second DDR controller;

when a write request of the second cache module is received, writing data of a y-th cache area into a y-th DDR storage area in a 1 st DDR memory according to a y-th write request;

when a write request of the p path of the second processor is received, gating the p +1 path of the second DDR memory and the p path of the channel of the second processor, so that the p path of the second processor writes the processed y path of data into the y path of storage area of the p +1 path of the second DDR memory;

when the data writing of the y-th DDR memory area in the P + 1-th DDR memory is finished, outputting read [ y ] =1 to the P + 1-th second processor or the second loading module to mark that the data reading of the y-th storage area in the P + 1-th DDR memory is valid, so that the P + 1-th second processor sends a read request to the second DDR controller when detecting that the read [ y ] =1 of the P + 1-th second DDR memory is detected, and sends a read request to the second DDR controller when the second loading module detects that the read [ y ] =1 of the P + 1-th second DDR memory is detected;

and when the read request of the second loading module is received, reading the ith path of data in the P +1 th path of the second DDR memory according to the ith path of read request and outputting the ith path of data to the second loading module.

6. The device according to claim 5, wherein the second buffer module comprises a buffer provided with k-way buffer queues and a FIFO controller corresponding to the buffer, wherein one FIFO occupies one buffer area, and a y-th way FIFO in the k-way buffer queues is used for buffering a y-th way data in the k-way data;

when the difference value of the write address and the read address of the y-way FIFO in the buffer is greater than a second preset value level2, outputting rd _ valid [ y ] =1 to mark the validity of the y-way FIFO read data, wherein the level2 is greater than or equal to 1 and is less than the depth of the FIFO;

when the FIFO controller corresponding to the buffer detects that the write ready [ y ] =1 output by the second DDR controller for the 1 st path of the second DDR memory is used for marking that the write data of the yth storage area in the 1 st path of the second DDR memory is valid, and RD _ valid [ y ] =1 of the yth path of the FIFO, the read module FIFO RD of the yth path of the FIFO outputs RD =1 to mark that the read request for the yth path of the FIFO is valid, the FIFO controller corresponding to the buffer reads the data of the yth path of the FIFO, multiplexes the low-speed data time sequence read from the k path of cache queue FIFO into the 1 path of high-speed data time sequence, converts the data into the write data time sequence, and outputs the write request to the second DDR controller;

correspondingly, when the data of the read cache is written into the DDR memory, the second DDR controller is specifically configured to, if a write request of the FIFO controller corresponding to the cache is received, write ready [ y ] =1 corresponding to the second DDR memory in the 1 st way and read rd _ valid [ y ] =1 of the FIFO in the y way in the cache, write the data of the FIFO in the y way in the cache into the DDR storage area in the y way of the second DDR memory; if a write request of the FIFO controller corresponding to the buffer is received, and a 1 st read request of the second processor to the 1 st DDR memory is received, and the 1 st read =1 corresponding to any one of the storage areas of the second DDR memory is set, the write ready =0 of the 1 st storage area of the second DDR memory is set to mark that the write data is invalid to represent that the 1 st DDR memory cannot write data at the moment, so as to inform the FIFO controller corresponding to the buffer to suspend writing data, the backpressure FIFO RD outputs RD =0 to mark that the current y th FIFO cannot read data to suspend reading the FIFO data, and after the 1 st read operation of the second processor to the 1 st DDR memory is completed, the FIFO controller corresponding to the buffer is informed to resume writing data according to the write ready [ y ] state of each storage area of the 1 st DDR memory.

7. The device according to claim 5, wherein the second loading module includes a loader provided with k-way loading queue FIFOs and a FIFO controller corresponding to the loader, wherein one FIFO occupies one loading area, and the y-th way FIFO in the k-way loading queue FIFOs is used for loading the y-th way data in the k-way data;

when the difference value between the write address and the read address of each path of FIFO in the loader is greater than a third preset value full2, each path of output RD _ valid [ y ] =1 to mark that each path of FIFO read data is valid, and when each path of FIFO outputs the moment that the read data is valid, the FIFO controller corresponding to the loader controls the read module FIFO RD of each path of FIFO to output RD =1 to mark that a read command to the y path of FIFO is valid, so that each path of FIFO aligns and reads the data at the same time and sends the data; when the difference value of the write address and the read address of each path of FIFO in the loader is smaller than a fourth preset value empty2, outputting wr _ valid [ y ] =1 by each path to mark that each path of FIFO write data is valid, full2 is larger than or equal to empty2, and full2 is smaller than the depth of the FIFO;

when the FIFO controller corresponding to the loader detects that the read [ y ] =1 output by the second DDR controller for the P +1 th way of the second DDR memory to mark that the read data of the y storage area in the P +1 th way of the second DDR memory is valid, and WR _ valid [ y ] =1 of the y FIFO, the write module FIFO WR of the y way of the FIFO outputs WR =1 to mark that the write request to the y way of the FIFO is valid, the FIFO controller corresponding to the loader outputs the read request to the second DDR controller and reads the data of the P +1 way of the y storage area of the second DDR memory, and then demultiplexes the 1 way of high-speed read data timing from the second DDR controller into k ways of low-speed data timing, converts the k ways of high-speed read data timing into write data timing, outputs the write data timing to each way of the FIFO, and writes the read data to each way of the FIFO;

correspondingly, when data of the second DDR memory is read and written into the FIFO, the second DDR controller is specifically configured to, if a read ready [ y ] =1 corresponding to the P +1 th DDR memory and a FIFO write wr _ valid [ y ] =1 corresponding to the y-th DDR memory of the second loader are received when a read request of the FIFO controller corresponding to the loader for the P +1 th DDR memory is received, read data of the y-th storage area of the P +1 th DDR memory is read and output to the FIFO controller corresponding to the loader; if a write request of the P +1 th path of the second DDR memory from the second processor to the P +1 th path of the second DDR memory is received, and the write ready =1 of any storage area of the P +1 th path of the second DDR memory is received, setting the read ready =0 of all storage areas of the P +1 th path of the second DDR memory to mark that the read data is invalid to indicate that the P +1 th path of the second DDR memory is unreadable at this time, notifying the FIFO controller to suspend reading the data, outputting WR =0 by a write module FIFO to mark that the y th path of the FIFO is unwritable at this time, suspending writing the data into the y th path of the FIFO, and after the write operation of the P +1 th path of the second DDR memory from the second processor to the P +1 th path of the second DDR memory is completed, notifying the FIFO controller to resume reading the data according to the read ready [ y ] state of each storage area of the P +1 th path of the second DDR memory.

8. A multi-channel if digital signal processing method applied to the multi-channel if digital signal processing apparatus according to any one of claims 1 to 7, the method comprising: