CN111342835A - SERDES module for JESD204B interface - Google Patents
SERDES module for JESD204B interface Download PDFInfo
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Abstract
The invention discloses an SERDES module for a JESD204B interface, which comprises a sending end component and a receiving end component, wherein the sending end component comprises an input register, an 8b/10b encoder, a parallel-serial converter and a sender; the receiving end assembly comprises an output register, an 8b/10b decoder, a Comma detector, a serial-parallel converter, a clock data restorer and a receiver; the SERDES module further comprises a PLL frequency synthesizer for performing PLL frequency synthesis on an externally input reference clock signal, generating clock signals required by a transmitting end component and a receiving end component, and providing a clock basis for the transmitting end component and the receiving end component. The SerDes module of the invention adopts a differential mode to transmit data, thus effectively reducing interference noise in the data transmission process; the equalizer based on the tuning function can increase or reduce the values of the capacitor and the resistor at the same time, give consideration to zero and gain, and realize the tuning of the equalizing filter unit.
Description
Technical Field
The invention relates to a JESD204B interface of a high-speed ADC, in particular to a SERDES module for the JESD204B interface.
Background
As the conversion rate of digital-to-analog converters gets higher, the JESD204B serial interface has become more widely used on digital-to-analog converters. JESD204 is a SerDes-based serial interface standard, mainly used for data transmission between digital-to-analog converters and logic devices, and its earliest version was JESD204A, now JESD204B subclass0, subclass1, and subclass2 differ mainly in their measurement of synchronization and inter-link fixed time difference. A relatively large number of digital-to-analog converter interfaces are currently on the market JESD204B subclass 1. The maximum transmission rate can reach 12.5Gbps, and the measurement of multi-link and multi-device synchronization and fixed time difference is supported.
Before the JESD204 interface appeared, the digital interface of the digital-to-analog converter was mostly the interface of the differential LVDS, which caused the difficulty of laying out the board, and when the density of the PCB was large, the board layer was required to be increased, which caused the cost of the printed board to rise.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a SERDES module for a JESD204B interface, which effectively reduces differential pairs of data output and effectively reduces interference noise in the data transmission process.
The purpose of the invention is realized by the following technical scheme: a SERDES module for use in a JESD204B interface, comprising: the device comprises a sending end component and a receiving end component, wherein the sending end component comprises an input register, an 8b/10b encoder, a parallel-serial converter and a transmitter; the receiving end assembly comprises an output register, an 8b/10b decoder, a Comma detector, a serial-parallel converter, a clock data restorer and a receiver;
in the sending end component:
the 8b/10b encoder is used for receiving byte signals sent by an upper layer protocol chip through an input register, mapping the byte signals into 10-bit 8b/10b codes with direct current balance and transmitting the codes to the parallel-serial converter;
the parallel-serial converter is used for serializing the 10-bit coding result to obtain a high-speed serial code stream of a CMOS level and transmitting the high-speed serial code stream to the transmitter;
the transmitter is used for converting the high-speed serial code stream of the CMOS level into a differential signal with strong anti-noise capability and transmitting the differential signal to the outside;
in the receiving end assembly:
the receiver is used for reducing the received differential signal into a serial signal of a CMOS level and transmitting the serial signal to the clock data restorer;
the clock data restorer is used for extracting clock information from the serial signals and finishing the optimal sampling of the serial data;
the serial-to-parallel converter is used for converting the serial signals into parallel data with 10 bits by using the clock recovered by the CDR;
the Comma detector is used for detecting special Comma characters and adjusting word boundaries to obtain parallel data with correct word boundaries;
the 8b/10b decoder is used for carrying out 8b/10b decoding on the parallel data with correct word boundary, reducing the parallel data into byte signals and transmitting the byte signals to an upper layer protocol chip through an output register.
The SERDES module further comprises a PLL frequency synthesizer for performing PLL frequency synthesis on an externally input reference clock signal, generating clock signals required by a transmitting end component and a receiving end component, and providing a clock basis for the transmitting end component and the receiving end component.
Preferably, the transmitter includes a single-ended to differential module and a transmitting-end equalizer, an input end of the single-ended to differential module is connected to the parallel-to-serial converter, and an output end of the single-ended to differential module outputs signals to the outside after passing through the transmitting-end equalizer. The receiver comprises a differential-to-single-ended module and a receiving end equalizer, wherein the receiving end equalizer receives external differential signals, and the output end of the receiving end equalizer is connected with the clock data restorer through the differential-to-single-ended module.
Preferably, the transmitting-end equalizer and the receiving-end equalizer each include an equalizing filter circuit, and the equalizing filter circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a first load resistor R1, a second load resistor R2, a first inductor L1, and a second inductor L2;
the grid electrode of the first MOS tube M1 is connected to a differential input port, the drain electrode of the first MOS tube M1 is connected to a differential output port, and the drain electrode of the first MOS tube M1 is further connected with a voltage source through a first load resistor R1 and a first inductor L1 in sequence; the source electrode of the first MOS transistor M1 is connected to the drain electrode of a sixth MOS transistor M6, and the source electrode of the sixth MOS transistor M6 is grounded; the grid electrode of the second MOS transistor M2 is connected to the other path of differential input port, the drain electrode of the second MOS transistor M2 is connected to the other path of differential output port, and the drain electrode of the second MOS transistor M2 is further connected to a voltage source through a second load resistor R2 and a second inductor in sequence; the source electrode of the second MOS tube M2 is connected to the drain electrode of a seventh MOS tube, and the source electrode of the seventh MOS tube is grounded; the grid electrodes of the sixth MOS tube and the seventh MOS tube are connected to the input end of bias voltage Vbias;
the grid electrode of the fifth MOS tube is connected to the input end of a control voltage Vctrl, the source electrode of the fifth MOS tube is connected to the source electrode of the first MOS tube, and the drain electrode of the fifth MOS tube is connected to the source electrode of the second MOS tube M2;
the source, the drain and the substrate of the third MOS transistor M3 and the source, the drain and the substrate of the fourth MOS transistor M3 are connected together and then connected with the input end of a control voltage Vctrl; a resistor RS is also connected between the source electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor; the third MOS transistor M3 and the fourth MOS transistor M4 are both MOS varactors; : the equalizing filter unit further comprises a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected with the gate of the first MOS transistor M1, and the other end of the first capacitor C1 is connected between the second load resistor R2 and the second inductor L2; one end of the second capacitor C2 is connected to the gate of the second MOS transistor M2, and the other end of the second capacitor C2 is connected between the first load resistor R1 and the first inductor L1.
The invention has the beneficial effects that: compared with the prior LVDS technology, the SerDes module has the advantages that the same data is transmitted, and the number of adopted lines is small; meanwhile, the data are sent and received in a differential mode, so that the interference noise in the data transmission process can be effectively reduced; based on the balanced filter circuit, the values of the capacitor and the resistor can be increased or reduced simultaneously, zero and gain are considered, and tuning of the balanced filter unit is achieved.
Drawings
FIG. 1 is a schematic structural view of the present invention;
fig. 2 is a schematic diagram of an equalization filter circuit.
Detailed Description
The technical solutions of the present invention are further described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.
As shown in fig. 1, a SERDES module for JESD204B interface is characterized in that: the device comprises a sending end component and a receiving end component, wherein the sending end component comprises an input register, an 8b/10b encoder, a parallel-serial converter and a transmitter; the receiving end assembly comprises an output register, an 8b/10b decoder, a Comma detector, a serial-parallel converter, a clock data restorer and a receiver;
in the sending end component:
the 8b/10b encoder is used for receiving byte signals sent by an upper layer protocol chip through an input register, mapping the byte signals into 10-bit 8b/10b codes with direct current balance and transmitting the codes to the parallel-serial converter;
the parallel-serial converter is used for serializing the 10-bit coding result to obtain a high-speed serial code stream of a CMOS level and transmitting the high-speed serial code stream to the transmitter;
the transmitter is used for converting the high-speed serial code stream of the CMOS level into a differential signal with strong anti-noise capability and transmitting the differential signal to the outside;
in the receiving end assembly:
the receiver is used for reducing the received differential signal into a serial signal of a CMOS level and transmitting the serial signal to the clock data restorer;
the clock data restorer is used for extracting clock information from the serial signals and finishing the optimal sampling of the serial data;
the serial-to-parallel converter is used for converting the serial signals into parallel data with 10 bits by using the clock recovered by the CDR;
the Comma detector is used for detecting special Comma characters and adjusting word boundaries to obtain parallel data with correct word boundaries;
the 8b/10b decoder is used for carrying out 8b/10b decoding on the parallel data with correct word boundary, reducing the parallel data into byte signals and transmitting the byte signals to an upper layer protocol chip through an output register.
The SERDES module further comprises a PLL frequency synthesizer for performing PLL frequency synthesis on an externally input reference clock signal, generating clock signals required by a transmitting end component and a receiving end component, and providing a clock basis for the transmitting end component and the receiving end component.
In an embodiment of the application, the transmitter includes a single-ended to differential module and a transmitting end equalizer, an input end of the single-ended to differential module is connected to the parallel-to-serial converter, and an output end of the single-ended to differential module outputs signals to the outside after passing through the transmitting end equalizer. The receiver comprises a differential-to-single-ended module and a receiving end equalizer, wherein the receiving end equalizer receives external differential signals, and the output end of the receiving end equalizer is connected with the clock data restorer through the differential-to-single-ended module; the sending end equalizer and the receiving end equalizer both comprise an equalization filter circuit.
As shown in fig. 2, the balanced filter circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a first load resistor R1, a second load resistor R2, a first inductor L1, and a second inductor L2;
the grid electrode of the first MOS tube M1 is connected to a differential input port, the drain electrode of the first MOS tube M1 is connected to a differential output port, and the drain electrode of the first MOS tube M1 is further connected with a voltage source through a first load resistor R1 and a first inductor L1 in sequence; the source electrode of the first MOS transistor M1 is connected to the drain electrode of a sixth MOS transistor M6, and the source electrode of the sixth MOS transistor M6 is grounded; the grid electrode of the second MOS transistor M2 is connected to the other path of differential input port, the drain electrode of the second MOS transistor M2 is connected to the other path of differential output port, and the drain electrode of the second MOS transistor M2 is further connected to a voltage source through a second load resistor R2 and a second inductor in sequence; the source electrode of the second MOS tube M2 is connected to the drain electrode of a seventh MOS tube, and the source electrode of the seventh MOS tube is grounded; the grid electrodes of the sixth MOS tube and the seventh MOS tube are connected to the input end of bias voltage Vbias; the bias voltage Vbias input by the port is a fixed value and is used for providing the starting voltage of the sixth MOS transistor M6 and the seventh MOS transistor M7;
the grid electrode of the fifth MOS tube is connected to the input end of a control voltage Vctrl, the source electrode of the fifth MOS tube is connected to the source electrode of the first MOS tube, and the drain electrode of the fifth MOS tube is connected to the source electrode of the second MOS tube M2;
the source, the drain and the substrate of the third MOS transistor M3 and the source, the drain and the substrate of the fourth MOS transistor M3 are connected together and then connected with the input end of a control voltage Vctrl; a resistor RS is also connected between the source electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor; the third MOS transistor M3 and the fourth MOS transistor M4 are both MOS varactors; : the equalizing filter unit further comprises a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected with the gate of the first MOS transistor M1, and the other end of the first capacitor C1 is connected between the second load resistor R2 and the second inductor L2; one end of the second capacitor C2 is connected to the gate of the second MOS transistor M2, and the other end of the second capacitor C2 is connected between the first load resistor R1 and the first inductor L1.
In the balanced filter circuit, an inductor is connected in series with drain loads R1 and R2, so that an inductive peaking technology is introduced. In order to further expand the bandwidth, capacitors C1 and C2 are connected between the drain and the gate of the pseudo differential pair transistor in a cross mode, and according to the Miller effect, the capacitors generate a negative capacitance value on the gate, so that a part of gate parasitic capacitance is offset, and the load capacitance of the previous stage is reduced. As shown in fig. 1, in implementing the tuning function, the values of the capacitance and the resistance are simultaneously increased or decreased under the control of the voltage, i.e. a variable resistance and a variable capacitance are required, and specifically, under the standard CMOS process, the variable resistance can be implemented by a MOS transistor M5 operating in a deep linear region, i.e. the gate of the MOS transistor is connected with the control voltage to control the transistor to be turned on and off, and the thickness of the channel inversion layer after the transistor is turned on to change the resistance. As the gate-source voltage increases, the channel resistance decreases. The variable capacitance may employ a voltage controlled MOS varactor. When the control voltage Vctrl is low, the M5 transistor is turned off, the resistance value of the variable resistor is equal to Rs, the capacitance value of the varactor is maximum, which is expressed in that the transmission equation is zero point minimum, the gain boost factor is maximum, and the low frequency part is attenuated. As the control voltage Vctrl increases, the resistance of the variable resistor decreases, and the capacitance values of the varactors M3 and M4 also decrease, which is expressed in the transmission equation as an increase in zero and a decrease in gain boost factor. When the control voltage Vctrl exceeds the tuning range of the varactor, the capacitance value of the varactor is not reduced along with the increase of Vctrl, and the size of the variable resistor is not reduced, so that the zero point is not increased any more, but the gain of the low-frequency part is improved due to the reduction of the variable resistor, and the gain improvement factor is reduced due to the two factors. Therefore, the invention can simultaneously increase or reduce the values of the capacitor and the resistor, give consideration to zero and gain, and realize the tuning of the equalizing filter unit.
Compared with the existing LVDS technology, the Serdes module is mainly used in a JESD204B interface of a digital-to-analog conversion module, and has the advantages that the same data is transmitted, the number of lines used is small, for example, the data rate is 10Gbps, because the highest support rate of LVDS is about 1Gbps, 10 pairs of parallel devices are needed, and the Serdes transmission is adopted, and the Serdes of JESD204B protocol clocks 1 supports the highest 12.5Gbps, only 1 pair is needed. In the embodiment of the present application, serdes is used in a 14-bit ADC, and may replace the original LVDS interface, and if LVDS output is used, 14 pairs are required. And moreover, the data are sent and received in a differential mode, so that the interference noise in the data transmission process can be effectively reduced, meanwhile, the values of the capacitor and the resistor can be increased or reduced simultaneously based on the equalizing filter circuit, the zero point and the gain are considered, and the tuning of the equalizing filter unit is realized.
The foregoing is a preferred embodiment of the present invention, it is to be understood that the invention is not limited to the form disclosed herein, but is not to be construed as excluding other embodiments, and is capable of other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A SERDES module for use in a JESD204B interface, comprising: the device comprises a sending end component and a receiving end component, wherein the sending end component comprises an input register, an 8b/10b encoder, a parallel-serial converter and a transmitter; the receiving end assembly comprises an output register, an 8b/10b decoder, a Comma detector, a serial-parallel converter, a clock data restorer and a receiver;
in the sending end component:
the 8b/10b encoder is used for receiving byte signals sent by an upper layer protocol chip through an input register, mapping the byte signals into 10-bit 8b/10b codes with direct current balance and transmitting the codes to the parallel-serial converter;
the parallel-serial converter is used for serializing the 10-bit coding result to obtain a high-speed serial code stream of a CMOS level and transmitting the high-speed serial code stream to the transmitter;
the transmitter is used for converting the high-speed serial code stream of the CMOS level into a differential signal with strong anti-noise capability and transmitting the differential signal to the outside;
in the receiving end assembly:
the receiver is used for reducing the received differential signal into a serial signal of a CMOS level and transmitting the serial signal to the clock data restorer;
the clock data restorer is used for extracting clock information from the serial signals and finishing the optimal sampling of the serial data;
the serial-to-parallel converter is used for converting the serial signals into parallel data with 10 bits by using the clock recovered by the CDR;
the Comma detector is used for detecting special Comma characters and adjusting word boundaries to obtain parallel data with correct word boundaries;
the 8b/10b decoder is used for carrying out 8b/10b decoding on the parallel data with correct word boundary, reducing the parallel data into byte signals and transmitting the byte signals to an upper layer protocol chip through an output register.
2. A SERDES module for a JESD204B interface as claimed in claim 1, wherein: the SERDES module further comprises a PLL frequency synthesizer for performing PLL frequency synthesis on an externally input reference clock signal, generating clock signals required by a transmitting end component and a receiving end component, and providing a clock basis for the transmitting end component and the receiving end component.
3. A SERDES module for a JESD204B interface as claimed in claim 1, wherein: the transmitter comprises a single-end to differential conversion module and a transmitting end equalizer, wherein the input end of the single-end to differential conversion module is connected with the parallel-serial converter, and the output end of the single-end to differential conversion module outputs signals to the outside after passing through the transmitting end equalizer.
4. A SERDES module for a JESD204B interface as claimed in claim 3, wherein: the receiver comprises a differential-to-single-ended module and a receiving end equalizer, wherein the receiving end equalizer receives external differential signals, and the output end of the receiving end equalizer is connected with the clock data restorer through the differential-to-single-ended module.
5. A SERDES module for a JESD204B interface as claimed in claim 4, wherein: the transmitting end equalizer and the receiving end equalizer both comprise equalizing filter circuits, and each equalizing filter circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a first load resistor R1, a second load resistor R2, a first inductor L1 and a second inductor L2;
the grid electrode of the first MOS tube M1 is connected to a differential input port, the drain electrode of the first MOS tube M1 is connected to a differential output port, and the drain electrode of the first MOS tube M1 is further connected with a voltage source through a first load resistor R1 and a first inductor L1 in sequence; the source electrode of the first MOS transistor M1 is connected to the drain electrode of a sixth MOS transistor M6, and the source electrode of the sixth MOS transistor M6 is grounded; the grid electrode of the second MOS transistor M2 is connected to the other path of differential input port, the drain electrode of the second MOS transistor M2 is connected to the other path of differential output port, and the drain electrode of the second MOS transistor M2 is further connected to a voltage source through a second load resistor R2 and a second inductor in sequence; the source electrode of the second MOS tube M2 is connected to the drain electrode of a seventh MOS tube, and the source electrode of the seventh MOS tube is grounded; the grid electrodes of the sixth MOS tube and the seventh MOS tube are connected to the input end of bias voltage Vbias;
the grid electrode of the fifth MOS tube is connected to the input end of a control voltage Vctrl, the source electrode of the fifth MOS tube is connected to the source electrode of the first MOS tube, and the drain electrode of the fifth MOS tube is connected to the source electrode of the second MOS tube M2;
the source, the drain and the substrate of the third MOS transistor M3 and the source, the drain and the substrate of the fourth MOS transistor M3 are connected together and then connected with the input end of a control voltage Vctrl; a resistor RS is also connected between the source electrode of the first MOS transistor M1 and the source electrode of the second MOS transistor; the third MOS transistor M3 and the fourth MOS transistor M4 are both MOS varactors; : the equalizing filter unit further comprises a first capacitor C1 and a second capacitor C2, one end of the first capacitor C1 is connected with the gate of the first MOS transistor M1, and the other end of the first capacitor C1 is connected between the second load resistor R2 and the second inductor L2; one end of the second capacitor C2 is connected to the gate of the second MOS transistor M2, and the other end of the second capacitor C2 is connected between the first load resistor R1 and the first inductor L1.
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| CN112559427A (en) * | 2020-12-18 | 2021-03-26 | 深圳市紫光同创电子有限公司 | Lvds multi-pair receiving device and Lvds multi-pair transmitting device |
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| 井钢: "JESD204B高速串行接口的模块设计" * |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111726166A (en) * | 2020-07-03 | 2020-09-29 | 北京航天发射技术研究所 | EPA star networking optical communication network switch and forwarding method |
| CN112559427A (en) * | 2020-12-18 | 2021-03-26 | 深圳市紫光同创电子有限公司 | Lvds multi-pair receiving device and Lvds multi-pair transmitting device |
| CN112559427B (en) * | 2020-12-18 | 2023-11-28 | 深圳市紫光同创电子有限公司 | Lvds pairs of receiving devices and Lvds pairs of transmitting devices |
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Application publication date: 20200626 |