CN111342650A - Power factor correction circuit and electronic equipment - Google Patents
Power factor correction circuit and electronic equipment Download PDFInfo
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- CN111342650A CN111342650A CN202010244357.XA CN202010244357A CN111342650A CN 111342650 A CN111342650 A CN 111342650A CN 202010244357 A CN202010244357 A CN 202010244357A CN 111342650 A CN111342650 A CN 111342650A
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- 238000010521 absorption reaction Methods 0.000 claims abstract description 16
- 230000003071 parasitic effect Effects 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 11
- 230000000740 bleeding effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000007599 discharging Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to the technical field of electronic circuits, and discloses a power factor correction circuit and electronic equipment, wherein the power factor correction circuit comprises a driving circuit, a booster circuit, a switching circuit and an absorption circuit, a main switching tube in the booster circuit works in a conducting state or a switching-off state according to a driving signal generated by the driving circuit, when the main switching tube is switched from the conducting state to the switching-off state, parasitic capacitance of the main switching tube discharges to close the switching circuit, the main switching tube cannot be conducted again when the switching circuit is closed, and the absorption circuit absorbs electric energy released by the parasitic capacitance of the main switching tube and releases the electric energy through the switching circuit to maintain the closing state of the switching circuit. Through the mode, the hidden trouble of secondary switching-on existing when the main switching tube in the power factor correction circuit is switched off can be fundamentally eliminated.
Description
Technical Field
The present invention relates to the field of power electronics technologies, and in particular, to a power factor correction circuit and an electronic device.
Background
At present, in the power electronic technology field, generally, the power factor of an electrical product is improved by connecting a power factor correction circuit (PFC) in series at a power input end, in actual work, because when the power of the electrical product is very large, a circuit on a circuit board can pass through rapidly changing current, so that voltage is generated on the circuit, the voltage can enable a main switching tube on the PFC to be conducted again at the turn-off time, that is, the main switching tube has a hidden trouble of secondary conduction, the loss of the main switching tube can be increased, the main switching tube can be damaged seriously, and then the circuit fails.
Aiming at the technical problem, the method adopted in the prior art is to reduce the risk of secondary conduction of the main switching tube by reducing the turn-off speed of the main switching tube, but the method only plays a role in reducing interference, cannot completely eliminate the hidden danger of secondary conduction of the main switching tube, and additionally increases the loss of the main switching tube, so that the heat generation of the main switching tube is increased, the heat dissipation area of a radiator is inevitably increased for heat dissipation of the main switching tube, and the cost is also increased, therefore, the method is not beneficial to popularization and application.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a power factor correction circuit and an electronic device, which can solve the technical problem that a main switching tube on a PFC is turned on again within an off time in the prior art.
The embodiment of the invention provides the following technical scheme for solving the technical problems:
in a first aspect, an embodiment of the present invention provides a power factor correction circuit, including: a drive circuit for generating a drive signal; the boost circuit comprises a main switching tube, the main switching tube comprises a first end, a second end and a third end, the second end of the main switching tube is connected with the driving circuit, and the main switching tube works in a conducting state or a switching-off state according to the driving signal so that the boost circuit finishes the boost process; the switch circuit is connected between the second end of the main switch tube and the third end of the main switch tube, when the main switch tube is switched from a conducting state to a switching-off state, the parasitic capacitance of the main switch tube discharges to close the switch circuit, and when the switch circuit is closed, the voltage of the second end of the main switch tube is pulled down, so that the voltage between the second end of the main switch tube and the third end of the main switch tube is smaller than the conducting threshold voltage of the main switch tube; and the absorption circuit is respectively connected with the second end of the main switching tube and the switching circuit and is used for absorbing the electric energy released by the parasitic capacitor of the main switching tube when the main switching tube is switched from a conducting state to a switching-off state, and releasing the electric energy through the switching circuit so as to maintain the closing state of the switching circuit.
Optionally, the boost circuit further includes a first inductor, a first diode, and a first capacitor, where one end of the first inductor is used to be connected to a positive electrode of a power supply, the other end of the first inductor is connected to a first end of the main switch tube, and an anode of the first diode is connected to the first end of the main switch tube; the positive end of the first capacitor is connected with the cathode of the first diode, and the negative end of the first capacitor is connected with the second end of the main switch tube.
Optionally, the switching circuit includes a first triode, an emitter of the first triode is connected to the second end of the main switching tube, a base of the first triode is connected to the absorption circuit, and a collector of the first triode is connected to the third end of the main switching tube.
Optionally, the switching circuit further comprises a first bleeder circuit, and the first bleeder circuit is connected between the collector of the first triode and the third end of the main switching tube.
Optionally, the first bleeder circuit includes a first resistor, one end of the first resistor is connected to a collector of the first triode, and the other end of the first resistor is connected to a third end of the main switching tube.
Optionally, the absorption circuit includes a second capacitor, the second capacitor includes a positive terminal and a negative terminal, the positive terminal of the second capacitor is connected to the base of the first transistor, and the negative terminal of the second capacitor is connected to the second terminal of the main switching tube.
Optionally, the absorption circuit further includes a second diode, an anode of the second diode is connected to the positive terminal of the second capacitor, and a cathode of the second diode is used for being connected to the driving circuit.
Optionally, the switch further comprises a second bleeder circuit, one end of the second bleeder circuit is connected to the positive terminal of the second capacitor and the anode of the second diode, and the other end of the second bleeder circuit is connected to the base of the first triode.
Optionally, the second bleeder circuit includes a second resistor, one end of the second resistor is connected to the positive terminal of the second capacitor and the anode of the second diode, and the other end of the second resistor is connected to the base of the first triode.
In a second aspect, an embodiment of the present invention provides an electronic device, including the power factor correction circuit as described above.
The embodiment of the invention has the beneficial effects that: the power factor correction circuit comprises a driving circuit, a booster circuit, a switching circuit and an absorption circuit, wherein a main switching tube in the booster circuit works in a conducting state or a switching-off state according to a driving signal generated by the driving circuit, when the main switching tube is switched from the conducting state to the switching-off state, parasitic capacitance of the main switching tube discharges to close the switching circuit, the main switching tube cannot be conducted again when the switching circuit is closed, and the absorption circuit absorbs electric energy released by the parasitic capacitance of the main switching tube and releases the electric energy through the switching circuit to maintain the closed state of the switching circuit. Through the mode, the hidden trouble of secondary switching-on existing when the main switching tube in the power factor correction circuit is switched off can be fundamentally eliminated.
Drawings
The embodiments are illustrated by way of example only in the accompanying drawings, in which like reference numerals refer to similar elements and which are not to be construed as limiting the embodiments, and in which the figures are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a circuit structure of a boost circuit provided in the prior art;
FIG. 2 is a schematic diagram of an operating waveform of a boost circuit provided by the prior art;
FIG. 3 is a schematic diagram of a power factor correction circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a power factor correction circuit according to another embodiment of the present invention;
fig. 5 is a schematic diagram of an operating waveform of a power factor correction circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
For convenience and a thorough understanding of the embodiments provided below, an additional description of the embodiments referred to herein is provided herein in connection with FIG. 1.
Referring to fig. 1, fig. 1 is a circuit diagram of a boosting circuit in the prior art. As shown in fig. 1, the boost circuit mainly comprises an inductor L1, a main switching tube Q1, and a diode D1, and the working process thereof can be divided into two parts, i.e., charging and discharging, and the working principle thereof is as follows:
and (3) charging process: during charging, the main switch Q1 is turned on, and at this time, the input current flows through the positive electrode of the power supply, the inductor L1, the node a, the node D and the negative electrode of the power supply in sequence, the current on the inductor increases linearly at a certain rate, and the inductor stores a certain amount of energy. In the process, the diode D1 is reversely biased to be off, and the capacitor C1 supplies energy to the load to maintain the load RL to work.
And (3) discharging: the main switch tube Q1 is turned off, at this time, because the inductor L1 has the function of the back electromotive force, the current of the inductor L1 cannot suddenly change instantaneously, but slowly and gradually discharges, the inductor L1, the diode D1, the load RL and the capacitor C1 form a discharge loop, the inductor L1 charges the capacitor C1, the voltage at the two ends of the capacitor C1 rises, and the voltage at the two ends of the capacitor C1 is higher than the input voltage, so that the boosting process is completed.
When the main switching tube Q1 is switched from the on state to the off state, no current flows to current flows between the node C and the node D, the rate of change of the current is di/dt, and since inductance exists on the line, it can be known from V ═ L di/dt that a voltage VCD (as shown in fig. 2) positive to C negative is generated on the line between the node C and the node D, and the voltage of the node D is pulled down by the generation of the voltage, so that a certain voltage difference exists between the node E and the node D, at this time, when the voltage VED is greater than the on threshold voltage of the main switching tube Q1, the main switching tube Q1 is turned on again, so that there is a risk of secondary turn-on during turn-off of the main switching tube Q1, which not only increases the loss of the main switching tube Q1, but also increases the heat generation amount of the main switching tube Q1.
As shown in fig. 1, the conventional solution is to increase the resistance of the turn-off resistor R to decrease the turn-off speed of the main switching transistor Q1, so as to decrease the current change rate di/dt, as mentioned above, because VCD is L di/dt, di/dt decreases, VCD decreases, and thus VED decreases, however, if the voltage VED is still greater than the turn-on threshold voltage of the main switching transistor Q1, the main switching transistor Q1 is turned on again. Since the physical inductance existing on the line is fixed, reducing the current change rate di/dt only reduces the voltage VCD, so that this approach can only reduce the interference by reducing the voltage VED, but cannot completely eliminate the hidden danger of the secondary turn-on of the main switching transistor Q1 during the turn-off process. Meanwhile, as the switching speed is reduced, the crossing time of the voltage and the current in the turn-off process of the main switching tube Q1 is lengthened, and it can be known from the loss calculation formula W-V I t that if the crossing time of the voltage and the current is longer, the loss of the main switching tube Q1 is larger, which leads to the increase of the heat generation of the main switching tube Q1, and in order to dissipate the heat, the heat dissipation area of the heat sink is inevitably increased, and the cost is also increased. Therefore, the prior art is not suitable for popularization and application, especially for application in power factor correction circuits.
In view of the above, in a first aspect, the embodiment of the invention provides a power factor correction circuit, as shown in fig. 3, the power factor correction circuit 100 includes a driving circuit 10, a voltage boosting circuit 20 (not shown), a switching circuit 30 and an absorption circuit 40, the driving circuit 10 is configured to generate a driving signal, the voltage boosting circuit 20 includes a main switch Q1, the main switch Q1 includes a first end, a second end and a third end, the second end of the main switch Q1 is connected to the driving circuit 10, and the main switch Q1 operates in an on state or an off state according to the driving signal.
The switch circuit 30 is connected between the second terminal of the main switch tube Q1 and the third terminal of the main switch tube Q1, when the main switch tube Q1 is switched from the on state to the off state, the parasitic capacitance of the main switch tube Q1 discharges to close the switch circuit 30, and when the switch circuit 30 is closed, the voltage at the second terminal of the main switch tube Q1 is pulled low, so that the voltage between the second terminal of the main switch tube Q1 and the third terminal of the main switch tube Q1 is smaller than the on threshold voltage of the main switch tube Q1.
The absorption circuit 40 is respectively connected to the second terminal of the main switch Q1 and the switch circuit 30, and is configured to absorb the electric energy released by the parasitic capacitor of the main switch Q1 when the main switch Q1 is switched from the on state to the off state, and release the electric energy through the switch circuit 30, so as to maintain the on state of the switch circuit 30.
In this embodiment, when the main switch Q1 is switched from the on state to the off state, the absorption circuit 40 absorbs the electric energy stored in the parasitic capacitor of the main switch Q1 and discharges the electric energy through the switch circuit 30, the discharge of the electric energy can maintain the switch circuit 30 closed, and when the switch circuit 30 is closed, the voltage at the second terminal of the main switch Q1 is pulled low, so that the voltage between the second terminal of the main switch Q1 and the third terminal of the main switch Q1 is smaller than the on threshold voltage of the main switch Q1. Therefore, the secondary turn-on hidden danger of the main switching tube Q1 in the turn-off process can be completely eliminated through the mode, the circuit structure is simple, the cost is low, and the power factor correction circuit can be applied to power factor correction circuits for power factor correction.
In some embodiments, the boost circuit 20 further includes a first inductor L1, a first diode D1, and a first capacitor C1, one end of the first inductor L1 is configured to be connected to the positive terminal of the power supply, the other end of the first inductor L1 is connected to the first terminal of the main switch Q1, and the anode of the first diode D1 is connected to the first terminal of the main switch Q1; the positive terminal of the first capacitor C1 is connected to the cathode of the first diode D1, and the negative terminal of the first capacitor C1 is connected to the second terminal of the main switch Q1.
The main switch Q1 may be any power switch device, such as a metal oxide semiconductor field effect transistor MOSFET, an insulated gate bipolar transistor IGBT, and the like, and the main switch Q1 may be configured as an N-type MOSFET or an N-type IGBT, corresponding to the circuit structure provided in the embodiment of the present invention. Taking an NMOS transistor as an example, the first terminal, the second terminal, and the third terminal of the main switching transistor correspond to the drain, the gate, and the source of the NMOS transistor, respectively. It is understood that the main switching tube Q1 can be adaptively adjusted for specific situations under the concept of the present invention.
It should be noted that, for convenience of description, the main switching transistor Q1 is replaced by an NMOS transistor.
As shown in fig. 4, the switching circuit 30 includes a first transistor Q2, an emitter of the first transistor Q2 is connected to the gate of the NMOS transistor Q1, a base of the first transistor Q2 is connected to the snubber circuit 40, and a collector of the first transistor Q1 is connected to the source of the NMOS transistor Q1.
The pfc circuit 100 further includes a first bleeder circuit 50, the first bleeder circuit 50 being connected between the collector of the first transistor Q1 and the source of the NMOS transistor Q1.
The first bleeder circuit 50 comprises a first resistor R1, one end of the first resistor R1 is connected to the collector of the first transistor Q2, and the other end of the first resistor R1 is connected to the source of the NMOS transistor Q1.
In this embodiment, when the NMOS transistor Q1 is turned off, a voltage VCD is generated between the node C and the node D due to the action of the line inductance, and compared with when the NMOS transistor Q1 is turned on, the voltage VCD is generated to pull down the voltage of the node D, so that a certain voltage difference VGS (or VED) exists between the gate and the source of the NMOS transistor Q1, in this embodiment, when the NMOS transistor Q1 is turned off, the first transistor Q2 absorbs the electric energy stored in the parasitic capacitor inside the NMOS transistor Q1, and releases the electric energy to maintain the on state of the first transistor Q2, as shown in fig. 4, the first resistor R1 is used as a bleeder resistor, and when the first transistor Q2 is configured to have a low resistance value, the voltage of the node E can be pulled down to an extremely low level, so that the gate-source voltage VGS of the NMOS transistor Q1 is greatly reduced.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating an operating waveform of a power factor correction circuit according to an embodiment of the present invention. As shown in fig. 5, the voltage VDS is the voltage between the drain and the source of the NMOS Q1, the voltage VGS is the voltage between the gate and the source of the NMOS Q1, and when the NMOS Q1 is turned off, as mentioned above, the gate-source voltage VGS of the NMOS Q1 is greatly reduced, so that the voltage VGS is always smaller than the threshold of the on voltage of the NMOS Q1 when the NMOS Q1 is turned off, thereby effectively preventing the NMOS Q1 from being turned on again during the turn-off process.
Referring to fig. 4, the absorption circuit 40 includes a second capacitor C2, the second capacitor C2 includes a positive terminal and a negative terminal, the positive terminal of the second capacitor C2 is connected to the base of the first transistor Q1, and the negative terminal of the second capacitor C2 is connected to the gate of the NMOS transistor Q1.
In the present embodiment, the second capacitor C2 is used for absorbing the electric energy stored in the parasitic capacitor inside the NMOS transistor Q1 when the NMOS transistor Q1 switches from the on state to the off state, so as to charge itself with the electric energy.
The absorption circuit 40 further comprises a second diode D2, an anode of the second diode D2 is connected to the positive terminal of the second capacitor C2, and a cathode of the second diode D2 is used for connecting to the driving circuit 40.
The second diode D2 is used to prevent the second capacitor C2 from discharging electric energy in advance, and prevent the interference voltage from adversely affecting the discharge capacitor C2.
The power factor correction circuit 100 further includes a second bleeder circuit 60, one end of the second bleeder circuit 60 is connected to the positive terminal of the second capacitor C2 and the anode of the second diode D2, and the other end of the second bleeder circuit 60 is connected to the base of the first transistor Q2.
The second bleeder circuit 60 comprises a second resistor R2, one end of the second resistor R2 is connected to the positive terminal of the second capacitor C2 and the anode of the second diode D2, and the other end of the second resistor R2 is connected to the base of the first transistor Q2.
In this embodiment, when the second capacitor C2 discharges, the second capacitor C2, the emitter of the first transistor Q2, the base of the first transistor Q2, and the second resistor R2 form a discharge loop, and the second resistor R2 is a bleeder resistor. During the discharging process of the second capacitor C2, the first transistor Q2 is operated in a conducting state.
In a second aspect, embodiments of the present invention provide an electronic device including the power factor correction circuit as described above.
Finally, it is to be understood that the present invention may be embodied in many different forms and is not limited to the embodiments described in the present specification, which are provided as additional limitations to the present disclosure, and which are provided for the purpose of providing a more thorough understanding of the present disclosure. In the light of the above, the above features are combined with each other and many other variations of the different aspects of the invention described above are considered to be within the scope of the present description; further, modifications and variations will occur to those skilled in the art in light of the foregoing description, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A power factor correction circuit, comprising:
a drive circuit for generating a drive signal;
the boost circuit comprises a main switching tube, the main switching tube comprises a first end, a second end and a third end, the second end of the main switching tube is connected with the driving circuit, and the main switching tube works in a conducting state or a switching-off state according to the driving signal so that the boost circuit finishes the boost process;
the switch circuit is connected between the second end of the main switch tube and the third end of the main switch tube, when the main switch tube is switched from a conducting state to a switching-off state, the parasitic capacitance of the main switch tube discharges to close the switch circuit, and when the switch circuit is closed, the voltage of the second end of the main switch tube is pulled down, so that the voltage between the second end of the main switch tube and the third end of the main switch tube is smaller than the conducting threshold voltage of the main switch tube;
and the absorption circuit is respectively connected with the second end of the main switching tube and the switching circuit and is used for absorbing the electric energy released by the parasitic capacitor of the main switching tube when the main switching tube is switched from a conducting state to a switching-off state, and releasing the electric energy through the switching circuit so as to maintain the closing state of the switching circuit.
2. The pfc circuit of claim 1, wherein the boost circuit further comprises a first inductor, a first diode and a first capacitor, wherein one end of the first inductor is connected to the positive terminal of the power supply, the other end of the first inductor is connected to the first terminal of the main switch transistor, and the anode of the first diode is connected to the first terminal of the main switch transistor; the positive end of the first capacitor is connected with the cathode of the first diode, and the negative end of the first capacitor is connected with the second end of the main switch tube.
3. The pfc circuit of claim 2 wherein the switching circuit comprises a first transistor, an emitter of the first transistor is coupled to the second terminal of the main switching transistor, a base of the first transistor is coupled to the absorption circuit, and a collector of the first transistor is coupled to the third terminal of the main switching transistor.
4. The pfc circuit of claim 3, further comprising a first bleeder circuit coupled between the collector of the first transistor and the third terminal of the main switching tube.
5. The PFC circuit of claim 4, wherein the first bleeding circuit comprises a first resistor, one end of the first resistor is connected to a collector of the first triode, and the other end of the first resistor is connected to a third end of the main switching tube.
6. The power factor correction circuit of claim 3, wherein the absorption circuit comprises a second capacitor, the second capacitor comprises a positive terminal and a negative terminal, the positive terminal of the second capacitor is connected to the base of the first transistor, and the negative terminal of the second capacitor is connected to the second terminal of the main switching tube.
7. The pfc circuit of claim 6 wherein the snubber circuit further comprises a second diode, an anode of the second diode being coupled to the positive terminal of the second capacitor, and a cathode of the second diode being adapted to be coupled to the driver circuit.
8. The power factor correction circuit of claim 6, further comprising a second bleeder circuit, wherein one end of the second bleeder circuit is connected to the positive terminal of the second capacitor and the anode of the second diode, and the other end of the second bleeder circuit is connected to the base of the first triode.
9. The pfc circuit of claim 8, wherein the second bleeder circuit comprises a second resistor, one end of the second resistor is connected to the positive terminal of the second capacitor and the anode of the second diode, and the other end of the second resistor is connected to the base of the first transistor.
10. An electronic device comprising the power factor correction circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010244357.XA CN111342650B (en) | 2020-03-31 | 2020-03-31 | Power factor correction circuit and electronic equipment |
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| CN202010244357.XA CN111342650B (en) | 2020-03-31 | 2020-03-31 | Power factor correction circuit and electronic equipment |
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| CN111342650A true CN111342650A (en) | 2020-06-26 |
| CN111342650B CN111342650B (en) | 2024-08-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022000596A1 (en) * | 2020-06-29 | 2022-01-06 | 深圳市华思旭科技有限公司 | Switch circuit and electric apparatus |
| CN113938120A (en) * | 2020-06-29 | 2022-01-14 | 深圳市华思旭科技有限公司 | Switch circuit and electric device |
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| CN105759108A (en) * | 2016-04-27 | 2016-07-13 | 深圳大学 | Circuit for improving reliability of zero-voltage detection loop of CRM PFC and electronic equipment |
| WO2019021159A1 (en) * | 2017-07-25 | 2019-01-31 | Quepal Limited | Switch control circuit for a gate drive |
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| CN207884527U (en) * | 2018-01-30 | 2018-09-18 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
| CN208507167U (en) * | 2018-08-14 | 2019-02-15 | 广州视源电子科技股份有限公司 | Power factor correction circuit, circuit board and LED display device |
| CN211880299U (en) * | 2020-03-31 | 2020-11-06 | 深圳麦格米特电气股份有限公司 | Power factor correction circuit and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022000596A1 (en) * | 2020-06-29 | 2022-01-06 | 深圳市华思旭科技有限公司 | Switch circuit and electric apparatus |
| CN113938120A (en) * | 2020-06-29 | 2022-01-14 | 深圳市华思旭科技有限公司 | Switch circuit and electric device |
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