CN115021529B - Driving circuit for inhibiting voltage dip of SiC MOSFET Miller platform - Google Patents
Driving circuit for inhibiting voltage dip of SiC MOSFET Miller platform Download PDFInfo
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- CN115021529B CN115021529B CN202210581674.XA CN202210581674A CN115021529B CN 115021529 B CN115021529 B CN 115021529B CN 202210581674 A CN202210581674 A CN 202210581674A CN 115021529 B CN115021529 B CN 115021529B
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- 238000010586 diagram Methods 0.000 description 5
- 230000010355 oscillation Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
Abstract
The invention discloses a driving circuit for inhibiting voltage dip of a SiC MOSFET miller platform, which is respectively arranged on an upper bridge arm and a lower bridge arm; in the driving circuit, one end of a resistor, one end of a second resistor and one end of a third resistor are connected in parallel with the push-pull output interface; the other end of the second resistor is connected with the cathode of the first Schottky diode, and the other end of the third resistor is connected with one end of the capacitor and the drain electrode of the N-channel field effect transistor; the grid electrode of the N-channel field effect transistor is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the positive electrode of the controlled pulse source, and the cathode of the controlled pulse source and the source electrode of the N-channel field effect transistor are both connected with the anode of the second Schottky diode; the anode of the first Schottky diode, the other end of the first resistor, the other end of the capacitor and the cathode of the second Schottky diode are all connected with the grid electrode of the SiC MOSFET. The invention can inhibit the Miller platform voltage of the SiC MOSFET power device from being greatly reduced and gate crosstalk.
Description
Technical Field
The invention belongs to the technical field of power electronic driving, and particularly relates to a driving circuit for inhibiting voltage dip of a SiC MOSFET miller platform, which is mainly used in a bridge driving circuit and is used for reducing switching loss.
Background
Compared with Si MOSFETs and Si IGBTs, the SiC MOSFETs have the advantages of minimum on-state resistance and shortest on/off time, and the input capacitance of the SiC MOSFETs is small, so that the switching frequency is higher. SiC MOSFETs are very widely used in power electronics, and their advent has significant implications for the development of power electronics. SiC MOSFETs have gradually replaced conventional Si MOSFETs in the last decade in high efficiency, high switching frequency and high temperature applications as the most potential transistor in power electronics. Automobiles are a potentially large market for SiC MOSFETs in the next decade, because HEVs/EVs are rapidly growing in popularity in view of concerns about global warming and energy limitations.
Because of parasitic parameters of the MOSFET, as the switching speed increases, the influence of parasitic capacitance and inductance on the driving circuit becomes non-negligible, and even severely affects the normal driving of the MOSFET. The MOSFET gate drive circuit can be equivalently regarded as an RLC series circuit, and changes in either current or voltage cause changes in gate potential, thereby affecting the operating state of the MOSFET. Therefore, there is a higher demand for the design of the reliability of the MOSFET gate driving circuit. Under the condition of large voltage, when the switch tube switches the switch state, the drain end of the complementary switch tube can bear large dv/dt, so that the gate-source capacitance of the MOSFET is charged through the Miller capacitance, when the voltage of the drain electrode of the MOSFET is reduced to be close to the driving voltage, the Miller capacitance is changed from a smaller value to a larger value, and more gate charges are needed to enable the voltage of the gate to rise due to the larger Miller capacitance, so that the Miller capacitance needs to draw charges from the gate-drain capacitance and the power supply, the gate bears large di/dt, and the gate-source capacitance is charged and discharged due to the large di/dt, so that the gate potential is severely oscillated, and voltage shock and voltage dip occur. Because the threshold voltage of the SiC MOSFET is relatively low, crosstalk can be caused by oscillation of the grid voltage of the MOSFET in bridge circuit application, and when a positive voltage peak exceeds the threshold voltage, the device can be even turned on by mistake, so that the normal operation of the power conversion circuit is affected; when the voltage of the grid electrode suddenly drops in the starting process, the MOSFET is insufficiently started, the on-resistance suddenly increases, the switching loss is increased, and the reliability of the MOSFET is affected.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a driving circuit for inhibiting the voltage dip of a miller platform of a SiC MOSFET, which can inhibit the voltage drop of the miller platform of a SiC MOSFET power device and gate crosstalk.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a driving circuit for inhibiting voltage dip of a SiC MOSFET miller platform, wherein the driving circuit is respectively arranged on an upper bridge arm and a lower bridge arm; the driving circuit comprises four resistors, two Schottky diodes, a capacitor, a controlled pulse source and an N-channel field effect transistor;
one end of the first resistor, one end of the second resistor and one end of the third resistor are connected in parallel with the push-pull output interface; the other end of the second resistor is connected with the cathode of the first Schottky diode, and the other end of the third resistor is connected with one end of the capacitor and the drain electrode of the N-channel field effect transistor; the grid electrode of the N-channel field effect transistor is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the positive electrode of the controlled pulse source, and the cathode of the controlled pulse source and the source electrode of the N-channel field effect transistor are both connected with the anode of the second Schottky diode;
the anode of the first Schottky diode, the other end of the first resistor, the other end of the capacitor and the cathode of the second Schottky diode are all connected with the grid electrode of the SiC MOSFET.
The push-pull output interface may also be driven by negative pressure, for example.
And a parallel capacitor is not arranged between the grid electrode and the source electrode of the SiC MOSFET.
Compared with the prior art, the invention has the beneficial effects that:
and an additional parallel capacitor is not needed between the grid sources of the SiC MOSFET, so that the switching speed can be greatly improved.
2. The capacitor is only connected into the circuit during operation, and the switching speed is not affected.
3. No additional negative pressure is needed to turn off the power supply.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
fig. 1 is a diagram of a conventional parallel capacitor driving structure.
Fig. 2 is a conventional drive parallel circuit switching waveform.
Fig. 3 and 4 are vibration-crosstalk amplitude tests.
Fig. 5 is a schematic view of the overall structure of the present invention.
Fig. 6 is a diagram of upper and lower tubes vg-t in the driving circuit of fig. 5.
Fig. 7 is a graph of amplitude versus crosstalk value test for the driving circuit of fig. 5.
Fig. 8 is a circuit diagram of the addition of negative pressure driving.
Fig. 9 is a diagram of upper and lower tubes vg-t in the driving circuit of fig. 8.
Fig. 10 is a graph of vibration-crosstalk amplitude test in the driving circuit of fig. 8.
Fig. 11 is a schematic diagram of threshold voltages of MOSFETs in an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.
In SiC MOSFET bridge gate driving circuits, special attention should be paid to the influence of crosstalk and miller plateau voltage dip phenomena, and it is necessary to analyze the cause of crosstalk generation and miller plateau voltage dip and the influence of various parasitic parameters in the switching loop on the crosstalk and miller plateau voltage dip phenomena. The method has a certain guiding significance for the design optimization of the gate driving circuit.
As shown in fig. 1, in a conventional SiC MOSFET bridge gate driving circuit, in order to overcome the problems of positive voltage spike and voltage dip, a parallel capacitor driving structure is adopted, that is, a capacitor connected in parallel is disposed between the gate and the source of the SiC MOSFET, for example, in fig. 1, an upper bridge arm driving circuit thereof, and a capacitor C1 is disposed between the gate and the source of the SiC MOSFET, that is, the capacitor C1 is connected in parallel with the gate-source capacitor Cgs1 of the SiC MOSFET, so as to alleviate the above problems. But the switching speed is reduced due to the addition of an additional parallel capacitance between the gate sources, as shown in fig. 2. The lower arm drive circuit is similar in structure to the upper arm drive circuit, i.e., a capacitor C2 is provided between the gate and source of the SiC MOSFET.
In addition, as can be seen from fig. 3 and fig. 4, in the driving circuit, the gate driving voltage suddenly drops, which causes insufficient MOSFET turn-on and possibly serious heat, and the negative voltage is about-5V in the acceptable range under the condition of the lower bridge arm turn-off state, but the positive voltage is up to 2V, so that the punch-through problem exists.
In order to avoid the problems, the invention provides a driving circuit for inhibiting the voltage dip of the miller platform of the SiC MOSFET, which eliminates the parallel capacitor C1 or C2 between the grid electrode and the source electrode of the SiC MOSFET. The driving circuit is respectively arranged on the upper bridge arm and the lower bridge arm, namely the driving circuit of the upper bridge arm and the driving circuit of the lower bridge arm with identical circuit structures.
The driving circuit comprises four resistors, two Schottky diodes, a capacitor, a controlled pulse source and an N-channel field effect transistor;
one end of the first resistor, one end of the second resistor and one end of the third resistor are connected in parallel with the push-pull output interface; the other end of the second resistor is connected with the cathode of the first Schottky diode, and the other end of the third resistor is connected with one end of the capacitor and the drain electrode of the N-channel field effect transistor; the grid electrode of the N-channel field effect transistor is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the positive electrode of the controlled pulse source, and the cathode of the controlled pulse source and the source electrode of the N-channel field effect transistor are both connected with the anode of the second Schottky diode; the anode of the first Schottky diode, the other end of the first resistor, the other end of the capacitor and the cathode of the second Schottky diode are all connected with the grid electrode of the SiC MOSFET.
Referring to fig. 5, in the driving circuit of the upper bridge arm of the present invention, the first resistor is R1, the second resistor is R2, the third resistor is R3, the fourth resistor is R4, the first schottky diode is D1, the second schottky diode is D3, the capacitance is C3, the controlled pulse source is VC1, and the N channel fet is N1. In the driving circuit of the lower bridge arm, the first resistor is R5, the second resistor is R6, the third resistor is R7, the fourth resistor is R8, the first Schottky diode is D2, the second Schottky diode is D4, the capacitor is C4, the controlled pulse source is VC2, and the N-channel field effect transistor is N2.
The driving circuit of the upper bridge arm and the driving circuit of the lower bridge arm have the same structure and principle, and the working principle of the driving circuit of the upper bridge arm is described below by taking the driving circuit of the upper bridge arm as an example.
When the push-pull output is turned on in the forward direction, the forward voltage charges the gate-source capacitance Cgs1 of the SiC MOSFET through R1, and simultaneously charges C3 through R3, and C3 stores charges to prepare for the arrival time of the Miller platform; d3 is a fast bleeding charge channel and blocks VC1 access to the drive circuit; by means of VC1 delay control N1 conduction, when severe oscillation occurs on the Miller platform, a capacitor C3 is connected into a driving loop to conduct charge compensation to a gate-drain capacitor Cgd1 of the SiC MOSFET so as not to enable the Miller platform to generate voltage dip, (when VD potential of the SiC MOSFET is close to VG potential, cgd1 becomes large, more charges need to be drawn to enable grid potential to rise, and due to the fact that Ig is constant, charges of an upper polar plate of Cgs1 are drawn to generate voltage dip), positive charges are provided by C3 at the moment, so that Vgs voltage of the SiC MOSFET cannot dip, and VC1 is turned off after the Miller platform passes.
When the power tube is turned off, the paths D1 and R2 are connected into the driving circuit in parallel to enable the resistance R1 to be low, and the power tube is turned off rapidly; when the turned-off miller plateau arrives, C3 is equivalent to providing a low-resistance channel, when the VD potential of the SiC MOSFET is increased, the miller capacitance is charged, and C3 absorbs a part of current, so that the grid source capacitance Cgs1 of the SiC MOSFET is prevented from being charged to increase the voltage.
In the circuit, R4 can prevent VC1 from being directly connected to an N1 grid, so that N1 starting current is overlarge; d3 prevents VC1 from switching into the circuit and can quickly release C3 charge and turn off N1.
In order to reduce switching loss and grid oscillation, the additional on grid resistor R1 is generally selected to be 5-10 ohms, and the off grid resistor R2 is generally selected to be 2-3 ohms; the capacitor C3 is 3-5 nf; the schottky diode employs a fast recovery diode.
In one embodiment of the invention, the DC supply voltage VDC may be as high as 800V, which also has a good rejection for higher dV/dt.
As can be seen from fig. 6, compared with fig. 3, the voltage dip suppression in the scheme of the present invention is greatly improved.
As can be seen from fig. 7, compared with fig. 2, in the scheme of the present invention, the minimum value of the turn-on voltage oscillation is about 13V, the crosstalk voltage of the lower bridge arm is about 1V, the effect of suppressing the voltage dip is obvious, and the present invention has a certain crosstalk suppression function.
Fig. 8 shows a further construction of the invention, in which a negative pressure drive is also connected to the push-pull output interface. Although no negative drive is applied in the circuit shown in fig. 5, the crosstalk voltage is acceptable. The structure of fig. 8 is added with negative pressure driving, and the main function is to inhibit the forward crosstalk voltage, so that no punch-through condition occurs. The principle is as follows: after negative pressure driving is added, when the bridge arm is in an off state, the grid electrode is negative voltage. For example, the maximum positive pressure spike in fig. 7 is about 1V, and when negative pressure driving is added, the peak value can be suppressed to 0V or less.
As can be seen from fig. 9, after the negative pressure driving is added, the waveforms of the gate voltages of the upper bridge arm and the lower bridge arm are not severely distorted, which indicates that the negative pressure driving is introduced and the suppression circuit is still applicable.
As can be seen from fig. 10, compared with fig. 7, the minimum value of the oscillating voltage of the upper bridge arm in the present application is 12V, and the oscillating voltage is reduced by 1V; the crosstalk voltage of the lower bridge arm is-1.9V, and is already below 0V, so that the lower bridge arm cannot have a punch-through phenomenon.
In one embodiment of the present invention, the MOSFET model used is CREE, C2M0040120D, and in conjunction with fig. 11, it can be seen that the threshold voltage is 2.4V at a junction temperature of 25 ℃; the minimum threshold voltage is 1.8V at a junction temperature of 150 ℃. Thus, in theory, it is also possible to not add negative pressure driving.
And through simulation verification of the non-negative pressure drive and the negative pressure drive, the feasibility of the circuit is verified. The negative pressure driving is added to enable the grid crosstalk voltage peak to be below 0V, so that the grid crosstalk voltage peak meets the requirement of a high-reliability driving circuit, but the circuit cost is increased to a certain extent, and therefore, the grid crosstalk voltage peak needs to be taken into consideration when in use.
Claims (3)
1. The driving circuit for inhibiting the voltage dip of the SiC MOSFET Miller platform is characterized by being arranged on an upper bridge arm and a lower bridge arm respectively; the driving circuit comprises four resistors, two Schottky diodes, a capacitor, a controlled pulse source and an N-channel field effect transistor;
one end of the first resistor, one end of the second resistor and one end of the third resistor are connected in parallel with the push-pull output interface; the other end of the second resistor is connected with the cathode of the first Schottky diode, and the other end of the third resistor is connected with one end of the capacitor and the drain electrode of the N-channel field effect transistor; the grid electrode of the N-channel field effect transistor is connected with one end of a fourth resistor, the other end of the fourth resistor is connected with the positive electrode of the controlled pulse source, and the cathode of the controlled pulse source and the source electrode of the N-channel field effect transistor are both connected with the anode of the second Schottky diode;
the anode of the first Schottky diode, the other end of the first resistor, the other end of the capacitor and the cathode of the second Schottky diode are all connected with the grid electrode of the SiC MOSFET.
2. The drive circuit for suppressing a voltage dip of a SiC MOSFET miller platform according to claim 1, wherein the push-pull output interface is connected to a negative voltage drive.
3. The drive circuit for suppressing a miller platform voltage dip of a SiC MOSFET according to claim 1, wherein a parallel capacitance is not provided between the gate and the source of the SiC MOSFET.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210581674.XA CN115021529B (en) | 2022-05-26 | 2022-05-26 | Driving circuit for inhibiting voltage dip of SiC MOSFET Miller platform |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210581674.XA CN115021529B (en) | 2022-05-26 | 2022-05-26 | Driving circuit for inhibiting voltage dip of SiC MOSFET Miller platform |
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| CN115021529A CN115021529A (en) | 2022-09-06 |
| CN115021529B true CN115021529B (en) | 2024-04-16 |
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| CN111464005A (en) * | 2020-04-26 | 2020-07-28 | 湖南大学 | SiC power tube driving circuit with active crosstalk suppression function and control method |
| CN112421940A (en) * | 2020-10-15 | 2021-02-26 | 北京交通大学 | MOSFET grid negative feedback active driving circuit |
| CN112737312A (en) * | 2020-12-28 | 2021-04-30 | 山东大学 | Drive circuit for inhibiting crosstalk of SiC MOSFET bridge circuit |
| CN114024432A (en) * | 2021-11-16 | 2022-02-08 | 西安电子科技大学 | Grid crosstalk suppression circuit of SiC MOSFET power device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108539964B (en) * | 2018-08-08 | 2018-11-20 | 上海颛芯企业管理咨询合伙企业（有限合伙） | The driving circuit and its device of power switch tube |
| JP6726337B1 (en) * | 2019-06-12 | 2020-07-22 | ナブテスコ株式会社 | Switching device, actuator drive circuit device, actuator system |
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2022
- 2022-05-26 CN CN202210581674.XA patent/CN115021529B/en active Active
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| CN102428634A (en) * | 2009-05-19 | 2012-04-25 | 三菱电机株式会社 | Gate driving circuit |
| CN111464005A (en) * | 2020-04-26 | 2020-07-28 | 湖南大学 | SiC power tube driving circuit with active crosstalk suppression function and control method |
| CN112421940A (en) * | 2020-10-15 | 2021-02-26 | 北京交通大学 | MOSFET grid negative feedback active driving circuit |
| CN112737312A (en) * | 2020-12-28 | 2021-04-30 | 山东大学 | Drive circuit for inhibiting crosstalk of SiC MOSFET bridge circuit |
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| Congwen Xu，et al.An improved active gate drive method for SiC MOSFET better switching performance.《2018 IEEE 3rd advanced information technology,electronic and automation control conference》.2018,第1114-1117页. * |
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