CN111341775A - Three-dimensional memory, preparation method thereof and electronic equipment - Google Patents

Three-dimensional memory, preparation method thereof and electronic equipment Download PDF

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Publication number
CN111341775A
CN111341775A CN202010233601.2A CN202010233601A CN111341775A CN 111341775 A CN111341775 A CN 111341775A CN 202010233601 A CN202010233601 A CN 202010233601A CN 111341775 A CN111341775 A CN 111341775A
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channel hole
substrate
nand string
layer
dimensional memory
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CN111341775B (en
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吴林春
张坤
周文犀
夏志良
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The application provides a three-dimensional memory, a preparation method of the three-dimensional memory and electronic equipment. The preparation method comprises the steps of providing a substrate. A first stack structure is formed on one side of a substrate. A plurality of first channel holes are formed through the first stack structure and extending to the substrate. And forming an etching barrier layer for filling the first channel hole. And forming a second laminated structure on the first laminated structure and the etching barrier layer. A plurality of second channel holes are formed through the second stacked structure. And removing the etching barrier layer to enable the first channel hole to be communicated with the second channel hole to form a channel hole. The preparation method is characterized in that the channel hole formed in one step in the related technology is changed into a two-step method. First channel holes are formed near the bottom, and then the remaining second channel holes communicating with the first channel holes are formed. The forming method provided by the application can reduce the forming difficulty of the channel hole, form the channel hole with an excellent structure and improve the uniformity of the depth of the channel hole.

Description

Three-dimensional memory, preparation method thereof and electronic equipment
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a three-dimensional memory, a preparation method of the three-dimensional memory and electronic equipment.
Background
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, and the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. For example, it is often desirable to form a channel hole in the stack structure to facilitate the formation of a NAND string in the channel hole to electrically extract certain components in the stack structure. However, as the number of layers of the three-dimensional memory increases, that is, the depth of the stacked structure increases, the bottom of the trench hole cannot be formed or the quality of the trench hole is poor, and the difficulty in forming the trench hole is greatly increased.
Disclosure of Invention
In view of this, the first aspect of the present application provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a substrate;
forming a first stacked structure on one side of the substrate;
forming a plurality of first channel holes penetrating the first stacked structure and extending to the substrate;
forming an etching barrier layer for filling the first channel hole;
forming a second laminated structure on the first laminated structure and the etching barrier layer;
forming a plurality of second channel holes penetrating through the second laminated structure, and enabling each second channel hole to correspondingly expose the etching barrier layer in each first channel hole; and
and removing the etching barrier layer to enable the first channel hole to be communicated with the second channel hole to form a channel hole.
The forming method provided by the application is prepared by changing the channel hole formed in one step in the related technology into a two-step method. First channel holes are formed near the bottom, and then the remaining second channel holes communicating with the first channel holes are formed. Since the first channel hole near the bottom is separately prepared, the structure of the first channel hole at the bottom is not affected no matter how thick the second stacked structure is, that is, no matter how deep the second channel hole is. Therefore, the forming method provided by the application can reduce the forming difficulty of the channel hole, form the channel hole with an excellent structure and improve the depth uniformity of the channel hole.
Wherein a surface of the first stacked structure where the first channel hole is opened is defined as a first surface, and a ratio of a depth of the channel hole in a direction perpendicular to the first surface to a width of the channel hole in a direction parallel to the first surface is (50-1000): 1.
wherein a surface of the first laminated structure where the first channel hole is opened is defined as a first surface, and a ratio of a depth of the first channel hole in a direction perpendicular to the first surface to a width of the first channel hole in a direction parallel to the first surface is (0.1 to 10): 1.
wherein a surface of the first stacked structure on which the first channel hole is formed is defined as a first surface, and a ratio of a depth of the first channel hole to a depth of the second channel hole in a direction perpendicular to the first surface is 1: (10-100).
The surface of the first laminated structure provided with the first channel hole is defined as a first surface, and in a direction parallel to the first surface, the aperture of the first channel hole close to the second channel hole is larger than the aperture of the second channel hole close to the first channel hole.
Wherein "forming a first stacked structure on one side of the substrate" includes:
forming a sacrificial layer on the substrate;
and forming a first laminated structure on the sacrificial layer, wherein the first laminated structure covers the sacrificial layer.
Wherein, after removing the etching barrier layer, the method further comprises the following steps:
removing the sacrificial layer to form an empty groove;
and forming a semiconductor material layer in the empty groove.
Wherein, after forming a plurality of first channel holes penetrating the first stacked structure and extending to the substrate, further comprising:
forming a plurality of first gate slits through the first stack structure;
and forming the etching barrier layer for filling the first gate gap.
Wherein "forming a plurality of first gate slits through the first stacked structure" includes:
and etching the first laminated structure to form a plurality of first gate gaps, and enabling the openings of the first gate gaps, which are close to the substrate, to be flush with the surface of the first laminated structure, which is close to the substrate.
Wherein, after the step of forming the second stacked structure on the first stacked structure and the etching barrier layer, the method further comprises the steps of:
and forming a plurality of second gate gaps penetrating through the second laminated structure, and enabling each second gate gap to correspondingly expose the etching barrier layer in each first gate gap.
Wherein, after removing the etching barrier layer to communicate the first channel hole with the second channel hole to form a channel hole, the method further comprises:
forming a NAND string within the channel hole, the NAND string including a channel layer and a memory layer surrounding the channel layer;
removing the etching barrier layer in the first gate gap so that the first gate gap is communicated with the second gate gap to form a gate gap;
forming a protective layer covering the side wall of the gate gap;
removing the sacrificial layer to form an empty groove;
removing the part of the memory layer exposed in the empty groove to expose part of the channel layer; and
and forming a semiconductor material layer in the empty groove, and enabling the semiconductor material layer to be in contact with part of the channel layer.
Wherein the material of the etching barrier layer comprises metal.
Wherein the metal comprises tungsten.
The surface of the first laminated structure provided with the first channel hole is defined as a first surface, and the longitudinal section of the first channel hole and/or the second channel hole is tapered in a direction perpendicular to the first surface.
A second aspect of the present application provides a three-dimensional memory, comprising:
a substrate;
the first stack structure is arranged on one side of the substrate, and the second stack structure is arranged on one side, far away from the substrate, of the first stack structure;
a NAND string comprising a first NAND string passing through the first stack structure and extending to the substrate, and a second NAND string passing through the second stack structure;
defining a surface of the first stack structure proximate to the second stack structure as a first surface, a width of a surface of the first NAND string distal to the substrate in a direction parallel to the first surface being greater than or less than a width of a surface of the second NAND string proximate to the substrate.
In the three-dimensional memory provided by the second aspect of the present application, the width of the surface of the first NAND string far away from the substrate is larger or smaller than the width of the surface of the second NAND string near the substrate, so that the first NAND string and the second NAND string are better connected, a NAND string with an excellent structure is formed, and the quality of the three-dimensional memory is improved.
Wherein a width of the first NAND string in a direction parallel to the first surface away from a surface of the substrate is greater than a width of the second NAND string in a direction parallel to the first surface.
Wherein a ratio of a height of the NAND string in a direction perpendicular to the first surface to a width of the NAND string in a direction parallel to the first surface is (50-1000): 1.
wherein a ratio of a height of the first NAND string in a direction perpendicular to the first surface to a width of the first NAND string in a direction parallel to the first surface is (0.1-10): 1.
wherein a ratio of heights of the first NAND string to the second NAND string in a direction perpendicular to the first surface is 1: (10-100).
Wherein the first NAND string and/or the second NAND string are frustoconical.
Wherein the three-dimensional memory further comprises an array common source comprising a first array common source through the first stack structure and a second array common source through the second stack structure;
in a direction parallel to the first surface, the width of the surface of the first array of common sources away from the substrate is greater than or less than the width of the surface of the second array of common sources close to the substrate.
Wherein a surface of the first NAND string remote from the substrate is flush with a surface of the first array of common sources remote from the substrate.
Wherein the three-dimensional memory further comprises a layer of semiconductor material between the first stack structure and the substrate, the layer of semiconductor material is between the array common source and the substrate, and the first NAND string extends through the first stack structure and the layer of semiconductor material and to the substrate.
Wherein the surface of the array common source electrode close to the substrate is flush with the surface of the first stack structure close to the substrate.
A third aspect of the present application provides an electronic device comprising a processor and the three-dimensional memory provided in the second aspect of the present application, wherein the processor is configured to write data into and read data from the three-dimensional memory.
In the electronic device provided by the third aspect of the present application, by using the three-dimensional memory provided by the second aspect of the present application, the structural stability of the NAND string can be improved, and the performance of the three-dimensional memory and the electronic device can be improved.
Drawings
In order to more clearly explain the technical solution in the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be described below.
Fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2 to 8 are schematic structural diagrams corresponding to S100, S200, S300, S400, S500, S600 and S700 in fig. 1, respectively.
Fig. 9 is a schematic structural diagram of a three-dimensional memory corresponding to fig. 8 in an embodiment of the present application.
Fig. 10 is a schematic structural diagram of a three-dimensional memory corresponding to fig. 8 in another embodiment of the present application.
Fig. 11 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure.
Fig. 12 and fig. 13 are schematic structural diagrams corresponding to S210 and S220 in fig. 11, respectively.
Fig. 14 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 15 and fig. 16 are schematic structural diagrams corresponding to S710 and S720 in fig. 14, respectively.
Fig. 17 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 18 and fig. 19 are corresponding schematic structural diagrams of S310 and S320 in fig. 17, respectively.
Fig. 20 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 21 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 22 is a schematic structural diagram corresponding to S510 in fig. 21.
Fig. 23 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application.
Fig. 24-fig. 29 are schematic structural diagrams corresponding to S730, S740, S750, S760, S770, and S780 in fig. 23, respectively.
Fig. 30 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application.
Fig. 31 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application.
Fig. 32 is a schematic structural diagram of a three-dimensional memory according to yet another embodiment of the present application.
Description of reference numerals:
three-dimensional memory-1, substrate-10, sacrificial layer-20, first stacked structure-30, first stacked structure-300, stacked pair-31, insulating layer-32, replacement layer-33, gate layer-330, first gate gap-34, etch stop-35, first channel hole-36, first surface-37, second stacked structure-40, second stacked structure-400, NAND string-41, first NAND string-411, second NAND string-412, channel layer-42, memory layer-43, second gate gap-44, second channel hole-45, semiconductor material layer-50, array common source-60, first array common source-601, second array common source-602, protective layer-70, empty slot-80.
Detailed Description
The following is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications are also considered as the protection scope of the present application.
Before the technical solutions of the present application are introduced, the technical problems in the related art will be described in detail.
In the related art, a plurality of channel holes are present in the three-dimensional memory, and for example, the channel holes are formed in order to form NAND strings in the channel holes to electrically extract some components in the stacked structure, so that the components can be electrically connected to other structural members of the three-dimensional memory. However, the current trend is that the number of layers of the three-dimensional memory is more and more, and as the number of layers of the three-dimensional memory, namely the depth of the laminated structure, is increased, the depth of the channel hole is further increased. The channel hole is usually formed in one step by etching. However, as the depth of the trench hole increases, the etching method or other forming methods cannot ensure the etching directionality and accuracy, which may cause the etching direction to deviate, and further the bottom trench hole cannot be formed, or even if the bottom trench hole is formed, the structural accuracy of the bottom trench hole cannot be ensured, so that the quality of the trench hole is poor, and the difficulty in forming the trench hole is greatly increased.
In view of the above, the present application provides a method for manufacturing a three-dimensional memory, which changes a trench hole formed in one step in the related art into a two-step method, thereby ensuring a structure of a bottom of the trench hole.
Referring to fig. 1 to 8 together, fig. 1 is a process flow diagram of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Fig. 2 to 8 are schematic structural diagrams corresponding to S100, S200, S300, S400, S500, S600 and S700 in fig. 1, respectively. The present embodiment provides a method for manufacturing a three-dimensional memory 1, including S100, S200, S300, S400, S500, S600, and S700. The details of S100, S200, S300, S400, S500, S600, and S700 are as follows.
Referring to fig. 2, S100, a substrate 10 is provided.
The substrate 10 of the present application may include a silicon substrate 10, a Germanium substrate 10, a Silicon On Insulator (SOI) substrate 10 or a Germanium On Insulator (GOI) substrate 10, etc.
Referring to fig. 3, S200, a first stacked structure 30 is formed on one side of the substrate 10.
The present application may first form a first stack 30 on one side of a substrate 10. The present application also divides the stack structure into two steps for preparation, wherein the first stack structure 30 is used for the subsequent formation of the first channel hole 36. Optionally, the first stacked structure 30 includes one or more stacked pairs 31, wherein each stacked pair 31 includes an insulating layer 32 and a replacement layer 33, and the insulating layer 32 may be made of an oxide, such as silicon oxide. The material of the replacement layer 33 may be a nitride, such as silicon nitride. And the replacement layer 33 is subsequently made of a metal (e.g., tungsten) to form the gate layer 330. Further optionally, the first array storage layer comprises 1-5 stacked pairs 31. Since the first stack structure 30 is used only to form the first channel holes 36, the number is not required to be too large, and a specific number may be negotiated according to the structure of the three-dimensional memory 1. The present application illustrates 2 stacked pairs 31.
Referring to fig. 4, S300, a plurality of first channel holes 36 extending through the first stacked structure 30 and to the substrate 10 are formed.
The first channel hole 36 can be formed on the first stacked structure 30, and since the thickness of the first stacked structure 30 is relatively low and there are only several stacked pairs 31, the depth of the first channel hole 36 is relatively low, so that the structure and position of the first channel hole 36 can be precisely controlled when the first stacked structure 30 is etched. This avoids the influence of the thickness of the subsequent second stacked structure 40 on the structural accuracy of the first channel hole 36 near the bottom.
Referring to fig. 5, S400, an etch stop layer 35 is formed to fill the first channel hole 36.
Since it is necessary to form the second stacked structure 40 on the first stacked structure 30, the etch stop layer 35 may be formed in the first channel hole 36 to prevent the material of the second stacked structure 40 from filling the first channel hole 36. The second etch stop layer 35 may also serve as an etch stop surface at a subsequent time when the second channel hole 45 is formed. Optionally, the material of the etch stop layer 35 includes a metal. Further optionally, the metal comprises tungsten.
Referring to fig. 6, S500, a second stacked structure 40 is formed on the first stacked structure 30 and the etch stop layer 35.
A second stacked structure 40 may be formed on the first stacked structure 30 and the etch stop layer 35, where the number of the second stacked structure 40 is only different from that of the first stacked structure 30, and the number of the second stacked structure 40 is much greater than that of the first stacked structure 30, for example, the number of the stacked pairs 31 in the second stacked structure 40 may be 10 to 1000, which is not described herein again.
Referring to fig. 7, S600, a plurality of second trench holes 45 penetrating through the second stacked structure 40 are formed, and each of the second trench holes 45 correspondingly exposes the etching stop layer 35 in each of the first trench holes 36.
According to the method, the second channel holes 45 are formed in the second laminated structure 40 with the higher thickness, and each second channel hole 45 is correspondingly exposed out of the etching barrier layer 35 in each first channel hole 36. First, when the etching stop layer 35 is exposed, the etching process is stopped by the etching stop layer 35 and cannot be continued. Next, in order to form the entire channel hole, the second channel hole 45 needs to be communicated with the first channel hole 36. Since the etch stopper 35 fills the first channel hole 36, when the etch stopper 35 is exposed, it means that the first channel hole 36 is exposed, and further means that the second channel hole 45 communicates with the first channel hole 36.
Optionally, a second channel hole 45 is formed through the second stacked structure 40 and exposes a portion of the etch stop layer 35. Optionally, a second trench hole 45 is formed through the second stack 40 and completely exposes the etch stop layer 35. Further alternatively, a second trench hole 45 penetrating through the second stacked structure 40 is formed, and the etch stop layer 35 is completely exposed, and the first stacked structure 30 is not exposed, which may also be understood as that the first trench hole 36 and the second trench hole 45 are completely disposed correspondingly (as shown in fig. 7).
Referring to fig. 8, S700, the etching stopper layer 35 is removed to make the first channel hole 36 and the second channel hole 45 communicate with each other to form a channel hole.
Finally, the etching barrier layer 35 is removed to expose the first channel hole 36, so that the first channel hole 36 and the second channel hole 45 are communicated to form a channel hole.
In summary, it can be seen from the above that the present application is prepared by changing the trench hole formed in one step in the related art into a two-step process. The first channel hole 36 is formed near the bottom, and then the remaining second channel holes 45 communicating with the first channel hole 36 are formed. Since the first channel hole 36 near the bottom is separately prepared, the structure of the first channel hole 36 at the bottom is not affected regardless of the thickness of the second laminate structure 40, i.e., regardless of the depth of the second channel hole 45. Therefore, the forming method provided by the application can reduce the forming difficulty of the channel hole, form the channel hole with an excellent structure and improve the depth uniformity of the channel hole.
Optionally, the number of trench holes is not limited herein. The number of channel holes is five for this application.
Referring to fig. 8 again, in the present embodiment, a surface of the first stacked structure 30 on which the first channel hole 36 is opened is defined as a first surface 37, and a ratio of a depth of the channel hole in a direction perpendicular to the first surface 37 (in a direction of D1 in the figure) to a width of the channel hole in a direction parallel to the first surface 37 (in a direction of D2 in the figure) is (50-1000): 1.
the ratio of the depth of the channel hole to the width of the channel hole of the present application may satisfy (50-1000): 1. if the depth of the channel hole is too large or the width of the channel hole is too small, the performance of the channel hole is affected. For example, if the ratio of the depth of the channel hole to the width of the channel hole is too large, it is larger than (50-1000): 1, this may result in that the portion of the second channel hole 45 adjacent to the first channel hole 36 may not be formed, or the quality of the structure formed thereby may be poor. If the ratio of the depth of the channel hole to the width of the channel hole is too small, it is less than (50-1000): 1, the width of the channel hole is too small, which affects the structure of other parts prepared in the channel hole and the transmission of electric signals.
Optionally, a ratio of a depth of the channel hole in a direction perpendicular to the first surface 37 to a width of the channel hole in a direction parallel to the first surface 37 is (80-800): 1. further optionally, a ratio of a depth of the channel hole in a direction perpendicular to the first surface 37 to a width of the channel hole in a direction parallel to the first surface 37 is (150-: 1.
referring to fig. 8 again, in the present embodiment, a surface of the first stacked structure 30 on which the first channel hole 36 is opened is defined as a first surface 37, and a ratio of a depth of the first channel hole 36 in a direction perpendicular to the first surface 37 to a width of the first channel hole 36 in a direction parallel to the first surface 37 is (0.1-10): 1.
the present application also makes it possible for the ratio of the depth to the width of the first channel hole 36 to satisfy (0.1 to 10): 1, preparing a channel hole structure close to the bottom with excellent structure. The formation of the channel hole may be affected if the depth of the first channel hole 36 is too large or the width of the first channel hole 36 is too small. For example, if the ratio of the depth of the first channel hole 36 to the width of the first channel hole 36 is too large, greater than (0.1-10): 1, the first channel hole 36 is too deep, so that the amount of the etching stop layer 35 and the time for removing the etching stop layer 35 are increased, the process cost is increased, and the process efficiency is reduced. If the ratio of the depth of the first channel hole 36 to the width of the first channel hole 36 is too small, it is smaller than (0.1 to 10): 1, which may result in the first channel hole 36 being too narrow, may affect the structure of other components subsequently fabricated within the channel hole and affect the transmission of electrical signals thereof.
Optionally, a ratio of a depth of the first channel hole 36 in a direction perpendicular to the first surface 37 to a width of the first channel hole 36 in a direction parallel to the first surface 37 is (0.5-8): 1. further optionally, a ratio of a depth of the first channel hole 36 in a direction perpendicular to the first surface 37 to a width of the first channel hole 36 in a direction parallel to the first surface 37 is (1-5): 1.
referring to fig. 8 again, in the present embodiment, a surface of the first stacked structure 30, on which the first channel hole 36 is opened, is defined as a first surface 37, and a ratio of a depth of the first channel hole 36 to a depth of the second channel hole 45 in a direction perpendicular to the first surface 37 is 1: (10-100).
The present application can also make the ratio of the depth of the first channel hole 36 to the depth of the second channel hole 45 satisfy 1: (10-100) to prepare a channel hole structure with an excellent structure. The formation of the channel hole may be affected if the depth of the first channel hole 36 is too large or if the depth of the first channel hole 36 is too small. For example, if the ratio of the depth of the first channel hole 36 to the depth of the second channel hole 45 is too large, greater than 1: (10-100), the depth of the first channel hole 36 is too large, so that the amount of the etching stop layer 35 and the time for removing the etching stop layer 35 are increased, the process cost is increased, and the process efficiency is reduced. For example, if the ratio of the depth of the first channel hole 36 to the depth of the second channel hole 45 is too small, less than 1: (10-100), the depth of the first channel hole 36 is too small, and the structure of the bottom first channel hole 36 is too small to meet the user's requirement. It can also be understood that if the depth of the first channel hole 36 is too small, the depth of the second channel hole 45 is too large, and thus the portion of the second channel hole 45 close to the first channel hole 36 cannot be formed, or the formed structure has poor quality.
Optionally, in a direction perpendicular to the first surface 37, a ratio of a depth of the first channel hole 36 to a depth of the second channel hole 45 is 1: (20-80). Further optionally, in a direction perpendicular to the first surface 37, a ratio of a depth of the first channel hole 36 to a depth of the second channel hole 45 is 1: (40-60).
Referring to fig. 9, fig. 9 is a schematic structural diagram of a three-dimensional memory corresponding to fig. 8 in an embodiment of the present application. In the present embodiment, the surface of the first stacked structure 30 on which the first channel hole 36 is opened is defined as a first surface 37, and an opening diameter of the first channel hole 36 near the second channel hole 45 is larger than an opening diameter of the second channel hole 45 near the first channel hole 36 in a direction parallel to the first surface 37 (direction D2 in the drawing).
The present application may also make the aperture of the first channel hole 36 close to the second channel hole 45 larger than the aperture of the second channel hole 45 close to the first channel hole 36 in the direction parallel to the first surface 37, and may also understand that the width of the first channel hole 36 is larger than the width of the second channel hole 45, so as to make the first channel hole 36 at the bottom wider, thereby reducing the difficulty of connecting the first channel hole 36 and the second channel hole 45. And may also make NAND strings 41 subsequently formed within first channel hole 36 wider so that NAND strings 41 thereof may better support the upper portion of second stack 40.
Please refer to fig. 10, fig. 10 is a schematic structural diagram of a three-dimensional memory corresponding to fig. 8 in another embodiment of the present application. In the present embodiment, the surface of the first stacked structure 30 in which the first channel hole 36 is opened is defined as a first surface 37, and the longitudinal section of the first channel hole 36 and/or the second channel hole 45 is tapered in a direction perpendicular to the first surface 37 (direction D1 in the drawing).
In order to make the first channel hole 36 and the second channel hole 45 more easily communicate with each other, the width of the first channel hole 36 and/or the second channel hole 45 may be increased, and alternatively, only the width of the connection portion of the first channel hole 36 and/or the second channel hole 45 may be increased, even if the longitudinal section of the first channel hole 36 and/or the second channel hole 45 is tapered, so as to ensure the connection of the first channel hole 36 and the second channel hole 45, the present embodiment is illustrated only with the longitudinal section of the first channel hole 36 being tapered.
Alternatively, the cross-section of the first channel hole 36 and/or the second channel hole 45 in a direction parallel to the first surface 37 may be circular, oval, rectangular, or other polygonal shapes, which are not limited herein.
Referring to fig. 11 to 13 together, fig. 11 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure. Fig. 12 and fig. 13 are schematic structural diagrams corresponding to S210 and S220 in fig. 11, respectively. In this embodiment, S200 "forming the first stacked structure 30" on one side of the substrate 10 "includes S210 and S220. The details of S210 and S220 are as follows.
Referring to fig. 12, S210, a sacrificial layer 20 is formed on the substrate 10.
Referring to fig. 13, S220, a first stacked structure 30 is formed on the sacrificial layer 20, and the first stacked structure 30 covers the sacrificial layer 20.
The present application may also form the semiconductor material layer 50 between the substrate 10 and the stacked structure, first, the sacrificial layer 20 may be formed on the substrate 10, the sacrificial layer 20 may serve to support other structures to be prepared later, and the sacrificial layer 20 may be replaced with the semiconductor material layer 50 later. Optionally, the material of the sacrificial layer 20 includes polysilicon. Then, the first stacked structure 30 is formed on the sacrificial layer 20. Optionally, when the substrate 10 is further provided with the sacrificial layer 20, the first channel hole 36 also penetrates through the sacrificial layer 20.
Referring to fig. 14 to 16, fig. 14 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure. Fig. 15 and fig. 16 are schematic structural diagrams corresponding to S710 and S720 in fig. 14, respectively. In this embodiment, after removing the etching stopper layer 35 "in S700", S710 and S720 are further included. The details of S710 and S720 are as follows.
Referring to fig. 15, S710, the sacrificial layer 20 is removed to form a hollow groove 80.
Referring to fig. 16, S720, a semiconductor material layer 50 is formed in the empty trench 80.
As mentioned above, the present application may first form the sacrificial layer 20 on the substrate 10, and then prepare the first stacked structure 30, the first channel hole 36, the second stacked structure 40, and the second channel hole 45 on the sacrificial layer 20, and in an embodiment of the present application, the semiconductor material layer 50 may be formed through the first channel hole 36 and the second channel hole 45. First, after the etch stop layer 35 in the first channel hole 36 is removed, the sacrificial layer 20 is removed to form the empty trench 80. Then, the semiconductor material layer 50 is formed in the empty trench 80. Optionally, the material of the semiconductor material layer 50 of the present application includes monocrystalline silicon.
Referring to fig. 17 to 19 together, fig. 17 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present application. Fig. 18 and fig. 19 are corresponding schematic structural diagrams of S310 and S320 in fig. 17, respectively. In this embodiment, after forming the plurality of first channel holes 36 "penetrating through the first stacked structure 30 and extending to the substrate 10 in S300 ″, S310 and S320 are also included. The details of S310 and S320 are as follows.
Referring to fig. 18, S310, a plurality of first gate slits 34 penetrating the first stacked structure 30 are formed.
Referring to fig. 19, S320, the etch stop layer 35 filling the first gate gap 34 is formed.
In another embodiment of the present application, the semiconductor material layer 50 may also be formed by a gate slit, and then the formation of the gate slit is first described.
The gate gap can also be formed after the channel hole is formed. Alternatively, the NAND string 41 may be formed in the first channel hole 36 and the second channel hole 45, and then the second gate slit 44 is formed, so that when the sacrificial layer 20 is removed, the NAND string 41 may be used to support the upper second stacked structure 40, thereby preventing the three-dimensional memory 1 from being structurally unstable. And when the gate gap is formed, the gate gap can be prepared by a two-step method like a trench hole, so that the uniformity of the depth of the gate gap is improved, and the gate gap with an excellent structure is prepared. First, a plurality of first gate slits 34 may be formed through the first stack structure 30. Since the thickness of the first stacked structure 30 is relatively low, there are only a few stacked pairs 31, and therefore the depth of the first gate slit 34 is relatively low, the structure and position of the first gate slit 34 can be precisely controlled when etching the first stacked structure 30. This avoids the influence of the thickness of the subsequent second stack structure 40 on the structural accuracy of the first gate slit 34 near the bottom. The etch stop layer 35 filling the first gate slit 34 may also be subsequently formed for subsequent layer structure preparation.
Referring to fig. 20 and 18 together, fig. 20 is a process flow diagram of a method for fabricating a three-dimensional memory according to yet another embodiment of the present application. In this embodiment, the step S310 "of forming the plurality of first gate slits 34" penetrating the first stacked structure 30 includes a step S311. The details of S311 are as follows.
Referring to fig. 18, S311, the first stacked structure 30 is etched to form a plurality of first gate slits 34, and an opening of the first gate slit 34 close to the substrate 10 is flush with a surface of the first stacked structure 30 close to the substrate 10.
Due to the small thickness of the first stacked structure 30, the present application can also make the opening of the first gate slit 34 close to the substrate 10 flush with the surface of the first stacked structure 30 close to the substrate 10. Therefore, the first gate gap 34 only penetrates through the first stacked structure 30 without damaging the structures of other layers, so that the structural accuracy of the gate gap is further improved, and the structural stability of the subsequent semiconductor material layer 50 can be further improved.
Referring to fig. 21 to 22 together, fig. 21 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure. Fig. 22 is a schematic structural diagram corresponding to S510 in fig. 21. In this embodiment, after S500 "forming the second stacked structure 40 on the first stacked structure 30 and the etch stop layer 35", S510 is further included. The details of S510 are as follows.
Referring to fig. 22, S510, a plurality of second gate gaps 44 penetrating through the second stacked structure 40 are formed, and each second gate gap 44 correspondingly exposes the etch stop layer 35 in each first gate gap 34.
According to the method, the second gate gaps 44 are formed in the second laminated structure 40 with the larger thickness, and each second gate gap 44 correspondingly exposes the etching barrier layer 35 in each first gate gap 34. First, when the etching stop layer 35 is exposed, the etching process is stopped by the etching stop layer 35 and cannot be continued. Next, in order to form the integrated gate slit, the second gate slit 44 needs to be communicated with the first gate slit 34. Since the etch stop layer 35 fills the first gate gap 34, when the etch stop layer 35 is exposed, it means that the first gate gap 34 is exposed, and further means that the second gate gap 44 is connected to the first gate gap 34.
Optionally, a second gate gap 44 is formed through the second stacked structure 40, and a portion of the etch stop layer 35 is exposed. Optionally, a second gate gap 44 is formed through the second stack structure 40 and completely exposes the etch stop layer 35. Further alternatively, the second gate gap 44 penetrating the second stacked structure 40 is formed, and the etch stop layer 35 is completely exposed, and the first stacked structure 30 is not exposed, which may also be understood as that the first gate gap 34 and the second gate gap 44 are completely disposed correspondingly (as shown in fig. 22).
Alternatively, after NAND string 41 is formed in the trench hole, a plurality of second gate gaps 44 penetrating through the second stacked structure 40 are formed on the second stacked structure 40, and each second gate gap 44 is exposed out of the etch stop layer 35 in each first gate gap 34, so that the material of NAND string 41 can be prevented from entering the second gate gaps 44 when NAND string 41 is formed.
Referring to fig. 23 to 29, fig. 23 is a process flow diagram of a method for fabricating a three-dimensional memory according to another embodiment of the present disclosure. Fig. 24-fig. 29 are schematic structural diagrams corresponding to S730, S740, S750, S760, S770, and S780 in fig. 23, respectively. In this embodiment, after removing the etch stop layer 35 in S700 "to make the first channel hole 36 communicate with the second channel hole 45 to form a channel hole", S730, S740, S750, S760, S770, and S780 are further included. The details of S730, S740, S750, S760, S770, and S780 are as follows.
Referring to fig. 24, S730, a NAND string 41 is formed in the channel hole, the NAND string 41 including a channel layer 42 and a memory layer 43 surrounding the channel layer 42.
Referring to fig. 25, S740 is performed to remove the etch stop layer 35 in the first gate gap 34, so that the first gate gap 34 is communicated with the second gate gap 44 to form a gate gap.
Referring to fig. 26, S750, a protection layer 70 is formed to cover the sidewalls of the gate gap.
Referring to fig. 27, S760, the sacrificial layer 20 is removed to form the empty trench 80.
Referring to fig. 28, S770, the exposed portion of the memory layer 43 in the empty trench 80 is removed to expose a portion of the channel layer 42.
Referring to fig. 29, S780, a semiconductor material layer 50 is formed in the empty trench 80, and the semiconductor material layer 50 is in contact with a portion of the channel layer 42.
The application may also form NAND string 41 in the trench hole after the second gap is formed. The protective layer 70 covering the gate gap sidewall can be formed, and the protective layer 70 is used for protecting the gate gap sidewall to prevent the sidewall from being damaged in the subsequent process. Then, the sacrificial layer 20 is removed to form the empty trench 80, and since the sacrificial layer 20 is removed through the gate gap in the present embodiment and the NAND string 41 exists at this time, after the sacrificial layer 20 is removed, the NAND string 41 can better support the second stacked structure 40 at the upper portion, and the structural stability of the three-dimensional memory 1 is ensured. The portion of memory layer 43 exposed within recess 80 may then be removed to expose a portion of channel layer 42, such that when semiconductor material layer 50 is formed within recess 80, semiconductor material layer 50 may be brought into contact with a portion of channel layer 42, thereby improving the electrical connection of semiconductor material layer 50 to NAND string 41.
In addition to the above method for manufacturing the three-dimensional memory 1, the present embodiment also provides a three-dimensional memory 1. The three-dimensional memory 1 and the method for manufacturing the three-dimensional memory 1 of the present application can achieve the advantages of the present application, and the two can be used together or independently, and the present application is not particularly limited thereto. For example, as an alternative, the three-dimensional memory 1 below may be prepared using the preparation method of the three-dimensional memory 1 provided above.
Referring to fig. 30, fig. 30 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present disclosure. The embodiment provides a three-dimensional memory 1, where the three-dimensional memory 1 includes a substrate 10, a first stack structure 300 and a second stack structure 400, the first stack structure 300 is disposed on one side of the substrate 10, and the second stack structure 400 is disposed on one side of the first stack structure 300 away from the substrate 10. NAND string 41, said NAND string 41 comprising a first NAND string 411 passing through said first stack structure 300 and extending to said substrate 10, and a second NAND string 412 passing through said second stack structure 400.
The surface of the first stack structure 300 near the second stack structure 400 is defined as a first surface 37, and the width of the surface of the first NAND string 411 away from the substrate 10 in a direction parallel to the first surface 37 is greater than or less than the width of the surface of the second NAND string 412 near the substrate 10.
In the three-dimensional memory 1 provided by the application, the width of the surface, away from the substrate 10, of the first NAND string 411 is larger or smaller than the width of the surface, close to the substrate 10, of the second NAND string 412, so that the first NAND string 411 and the second NAND string 412 are better connected, a NAND string 41 with an excellent structure is formed, and the quality of the three-dimensional memory 1 is improved. Alternatively, the present application is only illustrative of the width of the surface of the first NAND string 411 remote from the substrate 10 being greater than the width of the surface of the second NAND string 412 near the substrate 10.
Referring again to fig. 30, in this embodiment, the ratio of the height of NAND string 41 in the direction perpendicular to the first surface 37 (the D1 direction in the figure) to the width of NAND string 41 in the direction parallel to the first surface 37 (the D2 direction in the figure) is (50-1000): 1.
the ratio of the height of NAND string 41 to the width of NAND string 41 of the present application can satisfy (50-1000): 1. if the height of NAND string 41 is too large or the width of NAND string 41 is too small, the performance of NAND string 41 will be affected. For example, if the ratio of the height of NAND string 41 to the width of NAND string 41 is too large, greater than (50-1000): 1, this may result in the portion of the second NAND string 412 adjacent to the first NAND string 411 not being formed, or in a structure formed with poor quality. If the ratio of the height of NAND string 41 to the width of NAND string 41 is too small, less than (50-1000): 1, the width of NAND string 41 is too small, which affects the transmission of its electrical signal.
Optionally, the ratio of the height of the NAND string 41 in a direction perpendicular to the first surface 37 to the width of the NAND string 41 in a direction parallel to the first surface 37 is (80-800): 1. further optionally, the ratio of the height of NAND string 41 in the direction perpendicular to the first surface 37 to the width of NAND string 41 in the direction parallel to the first surface 37 is (150- & 600): 1.
referring again to fig. 30, in this embodiment, the ratio of the height of the first NAND string 411 in the direction perpendicular to the first surface 37 (the D1 direction in the figure) to the width of the first NAND string 411 in the direction parallel to the first surface 37 (the D2 direction in the figure) is (0.1-10): 1.
the present application may also have the height to width ratio of the first NAND string 411 satisfy (0.1-10): 1 to produce a well-formed near-bottom NAND string 41 structure. The formation of its NAND string 41 can be affected if the height of first NAND string 411 is too large or if the width of first NAND string 411 is too small. For example, if the ratio of the height of the first NAND string 411 to the width of the first NAND string 411 is too large, greater than (0.1-10): 1, this may result in the first NAND string 411 being too deep, thereby increasing the amount of the etch stop layer 35 and the time to remove the etch stop layer 35, increasing the process cost, and reducing the process efficiency. If the ratio of the height of the first NAND string 411 to the width of the first NAND string 411 is too small, less than (0.1-10): 1, this would result in the first NAND string 411 being too narrow, affecting the transmission of its electrical signal.
Optionally, a ratio of a height of the first NAND string 411 in a direction perpendicular to the first surface 37 to a width of the first NAND string 411 in a direction parallel to the first surface 37 is (0.5-8): 1. further optionally, a ratio of a height of the first NAND string 411 in a direction perpendicular to the first surface 37 to a width of the first NAND string 411 in a direction parallel to the first surface 37 is (1-5): 1.
referring again to fig. 30, in this embodiment, in the direction perpendicular to the first surface 37 (direction D1 in the figure), the ratio of the heights of the first NAND string 411 and the second NAND string 412 is 1: (10-100).
The present application may also have the ratio of the height of the first NAND string 411 to the height of the second NAND string 412 satisfy 1: (10-100) to prepare a NAND string 41 structure excellent in structure. The formation of its NAND string 41 is affected if the height of first NAND string 411 is too large or if the height of first NAND string 411 is too small. For example, if the ratio of the height of the first NAND string 411 to the height of the second NAND string 412 is too large, greater than 1: (10-100), this may result in an excessive height of the first NAND string 411, thereby increasing the amount of the etch stop layer 35 and the time to remove the etch stop layer 35, increasing the process cost, and reducing the process efficiency. For example, if the ratio of the height of the first NAND string 411 to the height of the second NAND string 412 is too small, less than 1: (10-100), this results in the height of the first NAND string 411 being too small, and the bottom first NAND string 411 being formed with too small a structure to meet the user's needs. It can also be appreciated that if the height of the first NAND string 411 is too small, it will result in the height of the second NAND string 412 being too large, thereby rendering the portion of the second NAND string 412 near the first NAND string 411 impossible to form, or of a poor quality structure.
Optionally, the ratio of the height of the first NAND string 411 to the height of the second NAND string 412 in a direction perpendicular to the first surface 37 is 1: (20-80). Further optionally, a ratio of a height of the first NAND string 411 to a height of the second NAND string 412 in a direction perpendicular to the first surface 37 is 1: (40-60).
Referring again to fig. 30, in this embodiment, the first NAND string 411 and/or the second NAND string 412 are truncated cone-shaped.
The present application may design the first NAND string 411 and/or the second NAND string 412 as circular truncated cones, it being understood that the first NAND string 411 and/or the second NAND string 412 are circular in a direction parallel to the first surface 37. Optionally, the first NAND string 411 and/or the second NAND string 412 can also be oval, rectangular, or other polygonal shape in a direction parallel to the first surface 37.
Please refer to fig. 31, fig. 31 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application. In this embodiment, the three-dimensional memory 1 further comprises an array common source 60, and the array common source 60 comprises a first array common source 601 passing through the first stack structure 300 and a second array common source 602 passing through the second stack structure 400. In a direction parallel to the first surface 37 (direction D2 in the figure), the width of the surface of the first array of common sources 601 far away from the substrate 10 is larger or smaller than the width of the surface of the second array of common sources 602 near the substrate 10.
The width of the surface of the first array common source 601 far away from the substrate 10 is larger or smaller than the width of the surface of the second array common source 602 near the substrate 10, so that the first array common source 601 and the second array common source 602 are better connected, the array common source 60 with an excellent structure is formed, and the quality of the three-dimensional memory 1 is improved. Alternatively, the present application is only illustrated with the width of the surface of the first array of common sources 601 away from the substrate 10 being greater than the width of the surface of the second array of common sources 602 close to the substrate 10.
Referring again to fig. 31, in this embodiment, the surface of the first NAND string 411 away from the substrate 10 is flush with the surface of the first array of common sources 601 away from the substrate 10.
The present application may also make the surface of the first NAND string 411 remote from the substrate 10 flush with the surface of the first array common source 601 remote from the substrate 10, thereby reducing the difficulty of fabricating the first NAND string 411 and the first array common source 601.
Please refer to fig. 32, fig. 32 is a schematic structural diagram of a three-dimensional memory according to another embodiment of the present application. In this embodiment, the three-dimensional memory 1 further includes a semiconductor material layer 50 located between the first stack structure 300 and the substrate 10, the semiconductor material layer 50 is located between the array common source 60 and the substrate 10, and the first NAND string 411 penetrates through the first stack structure 300 and the semiconductor material layer 50 and extends to the substrate 10.
The present application provides a semiconductor material layer 50 between the first stack structure 300 and the substrate 10, thereby increasing the area of the semiconductor material layer 50. And when the semiconductor material layer 50 is present, the first NAND string 411 may also extend through the semiconductor material layer 50.
Referring again to fig. 32, in the present embodiment, the surface of the array common source 60 close to the substrate 10 is flush with the surface of the first stack structure 300 close to the substrate 10.
The present application can also make the surface of the array common source 60 close to the substrate 10 flush with the surface of the first stack structure 300 close to the substrate 10, so as to form a structurally complete and excellent semiconductor material layer 50.
The application further provides an electronic device, which comprises a processor and the three-dimensional memory provided by the above embodiment of the application, wherein the processor is used for writing data into the three-dimensional memory and reading data from the three-dimensional memory.
The application also provides an electronic device comprising the three-dimensional memory provided by the application. Specifically, the electronic device may be an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, an electronic digital camera, or the like having a storage device. The electronic device of the present application typically further includes a processor, an input-output device, a display device, and the like. The three-dimensional memory is manufactured into storage devices such as a flash memory through processes such as packaging and the like, and the storage devices are used for storing files or data and are called by a processor. Specifically, the processor may write data to or read data from the storage device, i.e., the three-dimensional memory provided in the present application. The input and output device is used for inputting instructions or outputting signals, and the display device visualizes the signals to realize various functions of the electronic equipment. According to the electronic device provided by the application, the three-dimensional memory provided by the embodiment of the application is utilized, so that the structural stability of the NAND string can be improved, and the performances of the three-dimensional memory and the electronic device can be improved.
The foregoing detailed description has provided for the embodiments of the present application, and the principles and embodiments of the present application have been presented herein for purposes of illustration and description only and to facilitate understanding of the methods and their core concepts; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (25)

1. A method for preparing a three-dimensional memory, the method comprising:
providing a substrate;
forming a first stacked structure on one side of the substrate;
forming a plurality of first channel holes penetrating the first stacked structure and extending to the substrate;
forming an etching barrier layer for filling the first channel hole;
forming a second laminated structure on the first laminated structure and the etching barrier layer;
forming a plurality of second channel holes penetrating through the second laminated structure, and enabling each second channel hole to correspondingly expose the etching barrier layer in each first channel hole; and
and removing the etching barrier layer to enable the first channel hole to be communicated with the second channel hole to form a channel hole.
2. The production method according to claim 1, wherein a surface of the first laminated structure in which the first channel hole is opened is defined as a first surface, and a ratio of a depth of the channel hole in a direction perpendicular to the first surface to a width of the channel hole in a direction parallel to the first surface is (50-1000): 1.
3. the production method according to claim 1, wherein a surface of the first stacked structure in which the first channel hole is opened is defined as a first surface, and a ratio of a depth of the first channel hole in a direction perpendicular to the first surface to a width of the first channel hole in a direction parallel to the first surface is (0.1 to 10): 1.
4. the method according to claim 1, wherein a surface of the first stacked structure in which the first channel hole is opened is defined as a first surface, and a ratio of a depth of the first channel hole to a depth of the second channel hole in a direction perpendicular to the first surface is 1: (10-100).
5. The method according to claim 1, wherein a surface of the first stacked structure on which the first channel hole is formed is defined as a first surface, and an aperture of the first channel hole near the second channel hole is larger than an aperture of the second channel hole near the first channel hole in a direction parallel to the first surface.
6. The method of claim 1, wherein forming a first stacked structure on one side of the substrate comprises:
forming a sacrificial layer on the substrate;
and forming a first laminated structure on the sacrificial layer, wherein the first laminated structure covers the sacrificial layer.
7. The method of claim 6, further comprising, after removing the etch stop layer:
removing the sacrificial layer to form an empty groove;
and forming a semiconductor material layer in the empty groove.
8. The method of manufacturing according to claim 6, further comprising, after forming a plurality of first channel holes that extend through the first stacked structure and to the substrate:
forming a plurality of first gate slits through the first stack structure;
and forming the etching barrier layer for filling the first gate gap.
9. The method of claim 8, wherein forming a plurality of first gate apertures through the first stack structure comprises:
and etching the first laminated structure to form a plurality of first gate gaps, and enabling the openings of the first gate gaps, which are close to the substrate, to be flush with the surface of the first laminated structure, which is close to the substrate.
10. The method of manufacturing according to claim 8, further comprising, after forming the second stacked structure on the first stacked structure and the etch stopper layer:
and forming a plurality of second gate gaps penetrating through the second laminated structure, and enabling each second gate gap to correspondingly expose the etching barrier layer in each first gate gap.
11. The method of manufacturing according to claim 10, further comprising, after "removing the etching stopper layer so that the first channel hole communicates with the second channel hole to form a channel hole":
forming a NAND string within the channel hole, the NAND string including a channel layer and a memory layer surrounding the channel layer;
removing the etching barrier layer in the first gate gap so that the first gate gap is communicated with the second gate gap to form a gate gap;
forming a protective layer covering the side wall of the gate gap;
removing the sacrificial layer to form an empty groove;
removing the part of the memory layer exposed in the empty groove to expose part of the channel layer; and
and forming a semiconductor material layer in the empty groove, and enabling the semiconductor material layer to be in contact with part of the channel layer.
12. The method of claim 1, wherein the material of the etch stop layer comprises a metal.
13. The method of claim 12, wherein the metal comprises tungsten.
14. The method according to claim 1, wherein a surface of the first stacked structure in which the first channel hole is opened is defined as a first surface, and a longitudinal section of the first channel hole and/or the second channel hole is tapered in a direction perpendicular to the first surface.
15. A three-dimensional memory, the three-dimensional memory comprising:
a substrate;
the first stack structure is arranged on one side of the substrate, and the second stack structure is arranged on one side, far away from the substrate, of the first stack structure;
a NAND string comprising a first NAND string passing through the first stack structure and extending to the substrate, and a second NAND string passing through the second stack structure;
defining a surface of the first stack structure proximate to the second stack structure as a first surface, a width of a surface of the first NAND string distal to the substrate in a direction parallel to the first surface being greater than or less than a width of a surface of the second NAND string proximate to the substrate.
16. The three-dimensional memory of claim 15, wherein a width of the first NAND string in a direction parallel to the first surface away from the surface of the substrate is greater than a width of the second NAND string in a direction parallel to the surface of the substrate.
17. The three-dimensional memory of claim 15, wherein a ratio of a height of the NAND string in a direction perpendicular to the first surface to a width of the NAND string in a direction parallel to the first surface is (50-1000): 1.
18. the three-dimensional memory of claim 15, wherein a ratio of a height of the first NAND string in a direction perpendicular to the first surface to a width of the first NAND string in a direction parallel to the first surface is (0.1-10): 1.
19. the three-dimensional memory of claim 15, wherein a ratio of a height of the first NAND string to the second NAND string in a direction perpendicular to the first surface is 1: (10-100).
20. The three-dimensional memory of claim 15, wherein the first NAND string and/or the second NAND string is frustoconical.
21. The three-dimensional memory of claim 15, further comprising an array common source comprising a first array common source through the first stack structure and a second array common source through the second stack structure;
in a direction parallel to the first surface, the width of the surface of the first array of common sources away from the substrate is greater than or less than the width of the surface of the second array of common sources close to the substrate.
22. The three-dimensional memory of claim 21, wherein a surface of the first NAND string distal from the substrate is flush with a surface of the first array common source distal from the substrate.
23. The three-dimensional memory of claim 21, further comprising a layer of semiconductor material between the first stack structure and the substrate, the layer of semiconductor material between the array common source and the substrate, and the first NAND string extending through the first stack structure and the layer of semiconductor material and to the substrate.
24. The three-dimensional memory of claim 23, wherein a surface of the array common source proximate the substrate is flush with a surface of the first stack structure proximate the substrate.
25. An electronic device comprising a three-dimensional memory according to any of claims 15-24 and a processor for writing data to and reading data from the three-dimensional memory.
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