CN111338426A - DDR (double data Rate) read data-based fractional clock cycle synchronization system and method - Google Patents
DDR (double data Rate) read data-based fractional clock cycle synchronization system and method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
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Abstract
The invention discloses a DDR (double data Rate) read data-based fractional clock cycle synchronization system and a DDR read data-based fractional clock cycle synchronization method, wherein the system comprises the following steps: the digital phase-locked loop comprises a sampling register, a digital phase-locked loop and a digital delay stage control circuit; the digital phase-locked loop is used for delaying the sampling signal according to the delay level of the digital phase-locked loop to obtain a delay signal; the sampling register is used for sampling a data strobe signal through a delay signal and sending a sampling result to the digital delay stage control circuit; the digital delay stage control circuit is used for controlling the delay stage of the digital phase-locked loop according to the received sampling result. The invention realizes the synchronization of the sampling signal DQS _ gate and the data strobe signal DQS, generates the burr-free DQS signal and improves the timing sequence problem in design.
Description
Technical Field
The invention relates to the field of DDR (double data rate), in particular to a system and a method for synchronizing a fractional clock period based on DDR read data.
Background
According to the DDR protocol, after a DDR controller issues a read command, after several DDR clock cycles, the DDR granule returns DQS (data strobe), and all that the physical layer of the controller needs to process is to send a received data strobe signal (DQS) to the inside of the controller. Due to uncertainty of connection delay between an input/output (IO) port and a board level, a data strobe signal received by a DDR physical layer may generate glitches to affect normal functions, and the timing sequence requirement of a DDR controller cannot be met.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a DDR (double data rate) read data-based fractional clock cycle synchronization system and method, which are used for realizing the synchronization of a sampling signal DQS _ gate and a data strobe signal DQS, generating a glitch-free DQS signal and improving the timing sequence problem in design.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a fractional clock cycle synchronization system based on DDR read data, the system comprising: the digital phase-locked loop comprises a sampling register, a digital phase-locked loop and a digital delay stage control circuit;
the digital phase-locked loop is connected with a sampling signal generated by a data reading command of the DDR controller, the CK end of the sampling register is connected with the digital phase-locked loop, the D end of the sampling register is connected with a data strobe signal of the DDR controller, the Q end of the sampling register is connected with the input end of the digital delay stage control circuit, and the output end of the digital delay stage control circuit is connected with the digital phase-locked loop;
the digital phase-locked loop is used for delaying the sampling signal according to the delay level of the digital phase-locked loop to obtain a delay signal;
the sampling register is used for sampling the data strobe signal through the delay signal and sending a sampling result to the digital delay stage control circuit;
the digital delay stage control circuit is used for controlling the delay stage of the digital phase-locked loop according to the received sampling result, so that the sampling signal is synchronous with the data strobe signal.
Further, as mentioned above, the digital phase-locked loop is composed of digital gate units with fixed delay, and the delay of the maximum stage number of the digital phase-locked loop satisfies an operation clock cycle of the DDR controller.
Further, as to the above-mentioned system for synchronizing fractional clock cycles based on DDR read data, the digital gate unit is a nand gate, and the delay of one stage of the digital phase-locked loop is the delay of two nand gates.
Further, as described above, in the system for synchronizing fractional clock cycles based on DDR read data, the maximum delay stage number of the digital phase-locked loop is modified according to the actual operating frequency of the DDR controller.
Further, in the DDR-read-data-based fractional clock cycle synchronization system, the maximum delay stage number of the digital phase-locked loop is 256.
Further, as for the DDR-read-data-based fractional clock cycle synchronization system, when the number of delay stages of the digital phase-locked loop is 0, the sampling result of the sampling register is 0.
Further, as to the above-mentioned fractional clock cycle synchronization system based on DDR read data, when the digital phase-locked loop increases the number of delay stages until the CK end of the sampling register reaches the rising edge of the D end, the current delay of the digital phase-locked loop is the phase difference between the sampling signal and the data strobe signal, and the digital delay stage control circuit records that the current number of delay stages of the digital phase-locked loop is N, where N is a positive integer.
Further, as described above, in the system for synchronizing fractional clock cycles based on DDR read data, the digital delay stage control circuit is specifically configured to:
and when the delay stage number of the current fractional clock period of the DDR controller is T, setting the delay stage number of the digital phase-locked loop to be (N-T/4), wherein the (N-T/4) is the fractional clock period stage number of the sampling signal, and the T is a positive integer.
A method of fractional clock cycle synchronization based on DDR read data, the method comprising:
(1) the digital phase-locked loop delays a sampling signal generated by a data reading command of the DDR controller according to the delay stage number of the digital phase-locked loop to obtain a delay signal;
(2) the sampling register samples the data strobe signal of the DDR controller through the delay signal and sends a sampling result to the digital delay stage control circuit;
(3) the digital delay stage control circuit controls the delay stage of the digital phase-locked loop according to the received sampling result, so that the sampling signal is synchronous with the data strobe signal.
Further, as described above, in the method for synchronizing fractional clock cycles based on DDR read data, the digital phase-locked loop is formed by a digital gate unit with fixed delay, and the delay of the maximum stage number of the digital phase-locked loop satisfies an operation clock cycle of the DDR controller.
The invention has the beneficial effects that: the invention adopts a mode of adding a sampling register to a digital phase-locked loop to realize the synchronization of a sampling signal DQS _ gate and a data strobe signal DQS, and generates a glitch-free DQS signal through a gate control logic, thereby solving the problem of design transplantation among different processes, improving the time sequence problem in design, reducing the difficulty in design and reducing the design time.
Drawings
Fig. 1 is a schematic structural diagram of a DDR read data based fractional clock cycle synchronization system according to an embodiment of the present invention;
FIG. 2 is a timing diagram of DQS and DQS _ gate provided in an embodiment of the invention;
fig. 3 is a schematic flowchart of a method for synchronizing fractional clock cycles based on DDR read data according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
In the prior art, due to uncertainty of connection delay between an IO (input/output port) and a board level, a data strobe signal received by a DDR physical layer may generate glitches to influence normal functions. Integer clock cycle calibration the present invention is not discussed, and the present invention is primarily directed to fractional clock cycle calibration.
As shown in fig. 1, a system for fractional clock cycle synchronization based on DDR read data, the system comprising: the digital phase-locked loop comprises a sampling register, a digital phase-locked loop and a digital delay stage control circuit;
the digital phase-locked loop is connected with a sampling signal generated by a data reading command of the DDR controller, the CK end of the sampling register is connected with the digital phase-locked loop, the D end of the sampling register is connected with a data strobe signal of the DDR controller, the Q end of the sampling register is connected with the input end of the digital delay stage control circuit, and the output end of the digital delay stage control circuit is connected with the digital phase-locked loop;
the digital phase-locked loop is used for delaying the sampling signal according to the delay level of the digital phase-locked loop to obtain a delay signal;
the sampling register is used for sampling a data strobe signal through a delay signal and sending a sampling result to the digital delay stage control circuit;
the digital delay stage control circuit is used for controlling the delay stage of the digital phase-locked loop according to the received sampling result so that the sampling signal is synchronous with the data strobe signal.
In the above embodiment, the digital phase-locked loop may be formed by a digital gate unit with a fixed delay, and the delay of the maximum number of stages of the digital phase-locked loop satisfies one operation clock cycle of the DDR controller. The digital gate unit may be configured as a nand gate, and the delay of one stage of the digital phase locked loop is the delay of two nand gates. The maximum delay stage number of the digital phase-locked loop is modified according to the actual operation frequency of the DDR controller. The maximum number of delay stages of the digital phase locked loop may be set to 256 stages.
When the delay stage number of the digital phase-locked loop is 0, the sampling result of the sampling register is 0.
When the digital phase-locked loop increases the delay stages until the CK end of the sampling register adopts the rising edge of the D end, the current delay of the digital phase-locked loop is the phase difference between the sampling signal and the data strobe signal, and the digital delay stage control circuit records that the current delay stages of the digital phase-locked loop are N, wherein N is a positive integer.
The digital delay stage control circuit is specifically configured to:
when the delay stage number of the current fractional clock period of the DDR controller is T, the delay stage number of the digital phase-locked loop is set to be (N-T/4), wherein the (N-T/4) is the fractional clock period stage number of the sampling signal, and T is a positive integer.
In fig. 1, DQS is the data strobe signal, i.e., the sampled signal, of the DDR controller. DQS _ gate is generated by the DDR controller read enable signal delayed by an integer number of clock cycles, i.e., the sample signal, which is used to gate the DQS signal. The D end of the sampling register is connected with a data strobe signal DQS of the DDR controller, the Q end of the sampling register is a sampling data output result, and the adjustment of the digital phase-locked loop stage is controlled by a digital delay stage control circuit. The digital phase-locked loop DLL is composed of digital gate units NAND (NAND gate logic) with fixed delay, the delay of one stage is the delay of two NAND, the stage number is set to be 256, the modification can be carried out according to the actual DDR controller running frequency, and no problem exists as long as the largest DLL stage number can realize one DDR running clock cycle.
The working principle is as follows:
the DDR controller reads a data command to generate a sampling signal DQS _ gate, the sampling signal DQS _ gate is delayed by the digital phase-locked loop to obtain a delay signal, a sampling register samples a data strobe signal DQS (DDR protocol signal) of the DDR controller by the delay signal and sends a sampling result to a digital delay progression control circuit, and the digital delay progression control circuit continuously increases the delay progression of the digital phase-locked loop DLL by the sampling result of the sampling register and is used for delaying the DQS _ gate signal. As shown in fig. 2, since the DQS _ gate signal is generated by a DDR controller read data command, that is, it is ensured that DQS _ gate is ahead of DQS, the sampled data of the sampling register is also 0 when the DLL delay stage number is 0, and then the DLL delay stage number is increased until the CK end of the sampling register reaches the rising edge of the D end, at which time the delay of the DLL is regarded as a phase difference between the DQS _ gate signal and the DQS signal, and the digital delay stage number control circuit records that the delay stage number is N at this time. If the fractional clock cycle DLL stage of the current DDR controller is T, the delay stage of the final DQS _ gate is set to (N- (T/4)), i.e., the fractional clock cycle stage of DQS _ gate. T is an intermediate value or a temporary value generated by the training process, and the training result is (N- (T/4)). The training process is the synchronization process.
And finally, the DQS signal is gated by the DQS _ gate delay signal, and the DQS signal received by the DDR controller is an ideal signal without burrs, so that the good timing sequence requirement of the DDR controller is met.
The invention adopts a mode of digital phase-locked loop plus sampling register to realize the synchronization of DQS _ gate and DQS, and generates a glitch-free DQS signal through gate control logic, thereby solving the problem of design transplantation among different processes, improving the time sequence problem in design, reducing the difficulty in design and reducing the design time.
As shown in fig. 2, a method for fractional clock cycle synchronization based on DDR read data includes:
s100, delaying a sampling signal generated by a data reading command of the DDR controller by the digital phase-locked loop according to the delay stage number of the digital phase-locked loop to obtain a delay signal;
s200, sampling a data strobe signal of the DDR controller by a sampling register through a delay signal, and sending a sampling result to a digital delay stage control circuit;
s300, the digital delay stage control circuit controls the delay stage of the digital phase-locked loop according to the received sampling result, so that the sampling signal is synchronous with the data strobe signal.
The digital phase-locked loop is composed of digital gate units with fixed delay, and the delay of the maximum stage number of the digital phase-locked loop meets one operation clock period of the DDR controller.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. A fractional clock cycle synchronization system based on DDR read data, the system comprising: the digital phase-locked loop comprises a sampling register, a digital phase-locked loop and a digital delay stage control circuit;
the digital phase-locked loop is connected with a sampling signal generated by a data reading command of the DDR controller, the CK end of the sampling register is connected with the digital phase-locked loop, the D end of the sampling register is connected with a data strobe signal of the DDR controller, the Q end of the sampling register is connected with the input end of the digital delay stage control circuit, and the output end of the digital delay stage control circuit is connected with the digital phase-locked loop;
the digital phase-locked loop is used for delaying the sampling signal according to the delay level of the digital phase-locked loop to obtain a delay signal;
the sampling register is used for sampling the data strobe signal through the delay signal and sending a sampling result to the digital delay stage control circuit;
the digital delay stage control circuit is used for controlling the delay stage of the digital phase-locked loop according to the received sampling result, so that the sampling signal is synchronous with the data strobe signal.
2. The DDR read data based fractional clock cycle synchronization system of claim 1, wherein said digital phase locked loop is formed by fixed delay digital gate units, and a maximum number of stages of delay of said digital phase locked loop satisfies an operational clock cycle of said DDR controller.
3. The DDR read data based fractional clock cycle synchronization system of claim 2, wherein the digital gate units are NAND gates, and the delay of one stage of the digital phase locked loop is the delay of two NAND gates.
4. The DDR read data based fractional clock cycle synchronization system of claim 3, wherein a maximum delay stage number of the digital phase locked loop is modified based on an actual operating frequency of the DDR controller.
5. The DDR read data based fractional clock cycle synchronization system of claim 4, wherein the maximum delay stage number of the digital phase locked loop is 256.
6. The DDR read data based fractional clock cycle synchronization system of claim 1, wherein when the number of delay stages of the digital phase locked loop is 0, the sampling result of the sampling register is 0.
7. The DDR read data based fractional clock cycle synchronization system of claim 6, wherein when the digital phase locked loop increases the number of delay stages until the CK terminal of the sampling register takes the rising edge of the D terminal, the current delay of the digital phase locked loop is the phase difference between the sampling signal and the data strobe signal, the digital delay stage number control circuit records the current number of delay stages of the digital phase locked loop as N, N being a positive integer.
8. The DDR read data based fractional clock cycle synchronization system of claim 7, wherein the digital delay stage number control circuit is specifically configured to:
and when the delay stage number of the current fractional clock period of the DDR controller is T, setting the delay stage number of the digital phase-locked loop to be (N-T/4), wherein the (N-T/4) is the fractional clock period stage number of the sampling signal, and the T is a positive integer.
9. A method for fractional clock cycle synchronization based on DDR read data, the method comprising:
(1) the digital phase-locked loop delays a sampling signal generated by a data reading command of the DDR controller according to the delay stage number of the digital phase-locked loop to obtain a delay signal;
(2) the sampling register samples the data strobe signal of the DDR controller through the delay signal and sends a sampling result to the digital delay stage control circuit;
(3) the digital delay stage control circuit controls the delay stage of the digital phase-locked loop according to the received sampling result, so that the sampling signal is synchronous with the data strobe signal.
10. The method as claimed in claim 9, wherein the digital phase locked loop is composed of a digital gate unit with fixed delay, and the delay of the maximum stage number of the digital phase locked loop satisfies an operation clock cycle of the DDR controller.
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| CN115547381A (en) * | 2022-11-30 | 2022-12-30 | 合肥奎芯集成电路设计有限公司 | Gate signal generating circuit of data gate signal and signal generating method thereof |
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