CN111327861B

CN111327861B - Image transmission method based on FPGA single differential pair

Info

Publication number: CN111327861B
Application number: CN201811544752.9A
Authority: CN
Inventors: 白志强; 李战行; 于云翔; 张艳辉; 张建平
Original assignee: Beijing Huahang Radio Measurement Research Institute
Current assignee: Beijing Huahang Radio Measurement Research Institute
Priority date: 2018-12-17
Filing date: 2018-12-17
Publication date: 2021-02-19
Anticipated expiration: 2038-12-17
Also published as: CN111327861A

Abstract

An image transmission system and method based on single differential pair of FPGA, including sending end and receiving end; the sending end and the receiving end both comprise an FPGA with a GTX interface and a clock module, and the FPGA comprises a 7series transfer Wizard IP core and an image data synchronization module; a 120M differential clock output by the clock module is connected to a differential clock input end of the GTX; the transmitting end and the receiving end of the GTX are connected by a coaxial cable or a twisted pair. The invention provides an image transmission system method based on a single differential pair of an FPGA (field programmable gate array). A pair of CML (China Mobile language) differential cables is used for realizing the transmission of 0.6-1.5 Gbps serial image signals, a low-power-consumption gigabit transceiver GTX owned by a xilinx 7series chip is used for realizing the serial-parallel conversion of high-speed serial signals, 8B/10B coding and decoding are carried out, and then FPGA logic is used for realizing the synchronization of image data and the extraction of effective data signals.

Description

Image transmission method based on FPGA single differential pair

Technical Field

The invention relates to the field of image data transmission interfaces, in particular to a method for realizing high-speed serial image data transmission by using a single differential pair based on an FPGA (field programmable gate array).

Background

At present, in the field of image transmission, interfaces are various, and the application is wider in LVDS transmission technology. LVDS is a low-cost, low-power consumption signal transmission technique that is widely used in parallel and lower-rate serial image data transmission systems. LVDS applications are limited where a single pair of data exceeds 1 Gbps. CML is the simplest of high speed data transfer interfaces, with matched input and output circuitry, and supports higher data transfer rates. Meanwhile, in engineering application, a data cable can generate various adverse effects such as nonlinear disturbance on a system platform, and how to reduce the number of transmission cables is particularly important for the whole system. Therefore, it is a good solution to select a single differential pair of CML levels for image transmission. In addition, for CML single differential pair image transmission, a more implementation scheme is to select a TI integrated chip TLK1501 which integrates a serial-parallel conversion module, a clock module and an 8B/10B coding and decoding module. However, the chip size is large and the peripheral circuit is complicated.

Disclosure of Invention

In order to solve the problems, the invention provides an image transmission system and method based on a single differential pair of an FPGA.

An image transmission system based on a single differential pair of an FPGA comprises a sending end and a receiving end; the sending end and the receiving end both comprise an FPGA with a GTX interface and a clock module, and the FPGA comprises a 7series transfer Wizard IP core and an image data synchronization module; a 120M differential clock output by the clock module is connected to a differential clock input end of the GTX; the transmitting end and the receiving end of the GTX are connected by a coaxial cable or a twisted pair.

An image transmission method based on FPGA single differential pair, which utilizes the system of claim 1, and comprises the following steps:

s1, configuring a GTX gigabit serial transceiver by utilizing a 7series transfer Wizard IP core in the FPGA, setting an MGT reference clock to be 120MHz, setting the transmission rate to be 0.6Gbps, and selecting an MGT reference clock pin according to a circuit interface pin;

s2, configuring a GTX gigabit serial transceiver by using a 7series Transfer Wizard IP core in the FPGA, setting the bit width of input and output data to be 16/20, selecting an 8B/10B coding and decoding mode, and setting an RP clock to be 60 MHz; setting the 8B/10B control code as a K28.5 code, setting the mask code as 0B0001111111, and setting the alignment mode as 2-byte alignment;

s3, generating a 7series Transfer Wizard IP core inside the FPGA, and instantiating and connecting an external GTX clock and a data interface to complete pin distribution;

s4, the image data synchronization module detects an IDLE code to carry out synchronization operation, and the IDLE code consists of K28.5+ D5.6 or K28.5+ D16.2 codes according to an 8B/10B coding rule; a state machine is realized in the FPGA for monitoring different states, including a synchronous capture state, a synchronous state and an error code monitoring state; before effective data transmission, the state machine needs to enter a synchronous capture state; in the state, if the state machine monitors 5 continuous IDLE codes, the state machine enters a synchronous state, and starts to receive effective data after entering the synchronous state to obtain a data effective state indicating signal and effective data; otherwise, continuing monitoring until entering a synchronous state; after entering the synchronous state, when monitoring the data error code, the state machine enters the error code monitoring state, and after entering the error code monitoring state, if monitoring 3 continuous error codes, the state machine returns to the synchronous capturing state again; and if 5 IDLE codes are monitored continuously, entering a synchronous state, otherwise, continuing monitoring until the synchronous state is entered.

The invention provides an image transmission system method based on a single differential pair of an FPGA (field programmable gate array). A pair of CML (China Mobile language) differential cables is used for realizing the transmission of 0.6-1.5 Gbps serial image signals, a low-power-consumption gigabit transceiver GTX owned by a xilinx 7series chip is used for realizing the serial-parallel conversion of high-speed serial signals, 8B/10B coding and decoding are carried out, and then FPGA logic is used for realizing the synchronization of image data and the extraction of effective data signals.

Drawings

FIG. 1 is a schematic diagram of the system of the present invention,

FIG. 2 is a schematic view of the method of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

An image transmission system based on a single differential pair of an FPGA (field programmable gate array) as shown in FIG. 1 comprises a sending end and a receiving end; the sending end and the receiving end both comprise an FPGA with a GTX interface and a clock module, and the FPGA comprises a 7series transfer Wizard IP core and an image data synchronization module; a 120M differential clock output by the clock module is connected to a differential clock input end of the GTX; the transmitting end and the receiving end of the GTX are connected by a coaxial cable or a twisted pair.

An image transmission method based on a single differential pair of an FPGA adopts the system equipment, and comprises the following steps:

s4, the image data synchronization module detects an IDLE code to carry out synchronization operation, and the IDLE code consists of K28.5+ D5.6 or K28.5+ D16.2 codes according to an 8B/10B coding rule; a state machine is realized in the FPGA for monitoring different states, including a synchronous capture state, a synchronous state and an error code monitoring state; before effective data transmission, the state machine needs to enter a synchronous capture state; in the state, if the state machine monitors 5 continuous IDLE codes, the state machine enters a synchronous state, and starts to receive effective data after entering the synchronous state to obtain a data effective state indicating signal and effective data; otherwise, continuing monitoring until entering a synchronous state; after entering the synchronous state, when monitoring the data error code, the state machine enters the error code monitoring state, and after entering the error code monitoring state, if monitoring 3 continuous error codes, the state machine returns to the synchronous capturing state again; if 5 IDLE codes are monitored continuously, the synchronous state is entered, otherwise, the monitoring is continued until the synchronous state is entered, as shown in fig. 2.

The invention provides an image transmission method based on a single differential pair of an FPGA (field programmable gate array). the image transmission method is based on a xilinx ZYNQ hardware platform, and selects a zc7030 chip with a GTX transceiver. The image transmission method utilizes a pair of CML level differential cables to realize the transmission of 0.6-1.5 Gbps serial image signals, utilizes a low-power-consumption gigabit transceiver GTX possessed by a xilinx 7series chip to realize the serial-parallel conversion of high-speed serial signals, 8B/10B coding and decoding, and then utilizes FPGA logic to realize the synchronization of image data and the extraction of effective data signals. The invention has the obvious characteristic of simple external transmission interface, only uses a pair of differential cables to complete image transmission, and utilizes a GTX interface and a corresponding IP core provided by xilinx ZYNQ to be matched with a small amount of FPGA logic to realize the transceiving of high-speed serial image data, thereby greatly improving the design efficiency, simplifying the transmission interface circuit and reducing the influence of interface wiring on the system.

Claims

1. An image transmission method based on a single differential pair of an FPGA is realized by the following devices, wherein each device comprises a sending end and a receiving end; the transmitting end comprises a first FPGA with a first GTX interface and a first clock module, the receiving end comprises a second FPGA with a second GTX interface and a second clock module, and the first FPGA and the second FPGA both comprise a 7series Transfer Wizard IP core and an image data synchronization module; a 120M differential clock output by the first clock module is connected to a differential clock input end of the first GTX; the transmitting end of the first GTX is connected with the receiving end of the second GTX through a coaxial cable or a twisted pair; a first clock at a transmitting end generates a differential clock pair of 120MHz, MGT _ CLK _ P represents a positive end of the differential pair, MGT _ CLK _ N represents a negative end of the differential pair, and the output of the MGT _ CLK _ N is connected to a first GTX clock input end of the first FPGA to be used as a clock of a first GTX; a 120MHz differential clock generated by a second clock at the receiving end is output and connected to a second GTX clock input end of a second FPGA to be used as a clock of a second GTX; a first GTX data transmitting terminal differential pair GTX _ TX _ P/N is connected to a data receiving terminal differential pair GTX _ RX _ P/N of a second GTX; the method comprises the following steps:

s1, configuring a first GTX and a second GTX gigabit serial transceiver by utilizing a 7series Transfer Wizard IP core in a first FPGA and a second FPGA, setting a first GTX reference clock and a second GTX reference clock to be 120MHz, setting a transmission rate to be 0.6Gbps, and selecting a first GTX reference clock pin and a second GTX reference clock pin according to a circuit interface pin;

s2, configuring a first GTX and a second GTX gigabit serial transceiver by utilizing a 7series Transfer Wizard IP core in the first FPGA and the second FPGA, setting the bit width of input and output data to be 16/20, selecting 8B/10B in a coding and decoding mode, and setting an RP clock to be 60 MHz; setting the 8B/10B control code as a K28.5 code, setting the mask code as 0B0001111111, and setting the alignment mode as 2-byte alignment;

s3, generating 7series Transfer Wizard IP cores inside the first FPGA and the second FPGA, and instantiating and connecting external first GTX, second GTX clocks and data interfaces to complete pin distribution;

s4, the image data synchronization module detects an IDLE code to carry out synchronization operation, and the IDLE code consists of K28.5+ D5.6 or K28.5+ D16.2 codes according to an 8B/10B coding rule; a state machine is realized in the first FPGA and the second FPGA and is used for monitoring different states, including a synchronous capture state, a synchronous state and an error code monitoring state; before effective data transmission, the state machine needs to enter a synchronous capture state; in the state, if the state machine monitors 5 continuous IDLE codes, the state machine enters a synchronous state, and starts to receive effective data after entering the synchronous state to obtain a data effective state indicating signal and effective data; otherwise, continuing monitoring until entering a synchronous state; after entering the synchronous state, when monitoring the data error code, the state machine enters the error code monitoring state, and after entering the error code monitoring state, if monitoring 3 continuous error codes, the state machine returns to the synchronous capturing state again; and if 5 IDLE codes are monitored continuously, entering a synchronous state, otherwise, continuing monitoring until the synchronous state is entered.