CN111327318B - Interface circuit and communication device - Google Patents
Interface circuit and communication device Download PDFInfo
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- CN111327318B CN111327318B CN201911272177.6A CN201911272177A CN111327318B CN 111327318 B CN111327318 B CN 111327318B CN 201911272177 A CN201911272177 A CN 201911272177A CN 111327318 B CN111327318 B CN 111327318B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an interface circuit and a communication device capable of reducing circuit scale and power consumption. The interface circuit (1) is provided with: a plurality of communication devices (10-1, 10-2); an AD conversion circuit (20) for converting the analog signal AD into digital data; and a control circuit (30) for reading out the digital data in response to the read-out request signals from the plurality of communication devices (10-1, 10-2).
Description
Technical Field
The present application relates to an interface circuit and a communication device.
Background
In recent years, mobile communication terminals such as mobile phones and smart phones are required to cope with multiple frequencies and multiple frequency bands and multiple modes of wireless systems by one terminal. Such a communication device that deals with multi-band and multi-mode is required to process a plurality of transmission/reception signals at high speed without deteriorating quality. For example, LAA (Licensed-Assisted Access) is standardized, and an unlicensed band of a 5GHz band used in a wireless LAN is used as a secondary cell for Carrier Aggregation (CA) in LTE-Advanced, thereby improving throughput.
The communication device is generally configured to monitor a temperature and compensate for a gain caused by a temperature change. For example, a structure is disclosed in which an analog signal from one temperature sensor is AD-converted and introduced (for example, patent document 1).
Prior art literature
Patent literature
Patent document 1: U.S. Pat. No. 8526995 Specification
For example, in a configuration in which a communication device for wireless LAN and a communication device for LTE are mixed, if a temperature sensor and an AD conversion circuit are provided for each communication device, there is a problem that the circuit scale and the power consumption increase.
Disclosure of Invention
Problems to be solved by the application
The present application has been made in view of the above circumstances, and an object thereof is to realize an interface circuit and a communication device that can reduce the circuit scale and power consumption.
Means for solving the problems
An interface circuit according to an aspect of the present application includes: a plurality of communication devices; an AD conversion circuit for converting the analog signal AD into digital data; and a control circuit that reads out the digital data in accordance with read-out request signals from the plurality of communication devices.
In this configuration, the AD conversion circuit is shared by a plurality of communication devices. This can reduce the circuit scale and power consumption of the interface circuit.
The communication device according to one aspect of the present application includes: the interface circuit; a power amplifier circuit that amplifies the high frequency signal; and a sensor that detects a temperature of the power amplifier circuit and outputs the detected value as the analog signal.
In this configuration, the AD conversion circuit is shared by a plurality of communication devices, whereby the circuit scale and power consumption of the communication device can be reduced.
Effects of the application
According to the present application, an interface circuit and a communication device that can reduce the circuit scale and power consumption can be provided.
Drawings
Fig. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment.
Fig. 2 is a diagram showing an example of the configuration of a main part of the communication device according to the embodiment.
Fig. 3 is a block diagram showing an example of the internal structure of the start-up circuit.
Fig. 4 is a timing chart showing a basic first operation example of the start-up circuit.
Fig. 5 is a timing chart showing a basic second operation example of the start-up circuit.
Fig. 6 is a timing chart showing a basic third operation example of the start-up circuit.
Fig. 7 is a timing chart showing a basic fourth operation example of the start-up circuit.
Fig. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment.
Fig. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment.
Fig. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment.
Fig. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment.
Fig. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment.
Fig. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment.
Fig. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment.
Fig. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment.
Fig. 16 is a diagram showing an output target of digital data in each operation example shown in fig. 8 to 15.
Fig. 17 is a diagram showing a configuration example in which an AD conversion circuit is shared by six communication devices.
Fig. 18 is a diagram showing an example of an output target of digital data in the configuration example shown in fig. 17.
Description of the reference numerals
1: an interface circuit;
2: a sensor;
3-1, 3-2: a communication interface;
4: a power amplifier circuit;
10. 10-1, 10-2, 10-3, 10-4, 10-5, 10-6: a communication device;
11-1, 11-2: a start-up circuit;
12-1, 12-2: a register;
20: an AD conversion circuit;
30: a control circuit;
100: a communication device;
111-1, 111-2: a control signal generating circuit;
112-1, 112-2: a synchronizing circuit.
Detailed Description
The interface circuit and the communication device according to the embodiments are described in detail below with reference to the drawings. The present application is not limited to the present embodiment. The embodiments are examples, and it is needless to say that partial substitutions or combinations of the structures shown in the different embodiments can be made. Description of matters common to embodiment 1 will be omitted after embodiment 2, and only the differences will be described. In particular, regarding the same operational effects based on the same structure, it will not be mentioned successively in each embodiment.
(embodiment 1)
Fig. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to the embodiment. Fig. 2 is a diagram showing an example of the configuration of a main part of the communication device according to the embodiment. As shown in fig. 1, the interface circuit 1 includes communication devices 10-1, 10-2, an AD conversion circuit 20, and a control circuit 30. In the present disclosure, the communication device 10-1 is, for example, a communication device for LTE in the 5GHz band, and the communication device 10-2 is, for example, a communication device for WiFi. Further, in the present disclosure, the AD conversion circuit 20 AD-converts the analog signal a_sig from the sensor 2 into digital data ts_data. In the present disclosure, the sensor 2 and the AD conversion circuit 20 are shared by the two communication devices 10-1 and 10-2. In the following description, since the two communication devices 10-1, 10-2 and their constituent elements are identical, symbols "-1", "-2", "_1", "_2" are omitted without distinguishing the two communication devices 10-1, 10-2 and their constituent elements.
As shown in fig. 2, in the case where the interface circuit 1 according to the embodiment is applied to the communication device 100, the sensor 2 is exemplified by a temperature sensor that detects the temperature of the power amplifier circuit 4 for high-frequency amplification, but the present application is not limited thereto, and may be an ultrasonic sensor, an infrared sensor, or a vibration sensor, for example. The sensor 2 may be an analog circuit, and may be a voltmeter, a ammeter, or the like, for example.
The communication device 10 outputs a read request signal of digital data ts_data AD-converted from an analog signal a_sig which is a detection value of the sensor 2.
The control circuit 30 reads out the digital data ts_data from the AD conversion circuit 20 in accordance with a read-out request signal (a start signal tkick and an introduction signal catch described later) output from the communication device 10, and outputs the read-out request signal to the communication device 10.
As shown in fig. 1, the communication device 10-1 includes a communication interface 3-1, a start-up circuit 11-1, and a register 12-1. The communication device 10-2 includes a communication interface 3-2, a start-up circuit 11-2, and a register 12-2.
In the present disclosure, the communication interface 3-1 is, for example, a serial communication interface in the LTE communication device 10-1 of the 5GHz band, and the communication interface 3-2 is, for example, a serial communication interface in the WiFi communication device 10-2.
The communication interface 3-1 outputs a read command wr_1 of the digital data ts_data and a communication clock signal clk_1 to the start-up circuit 11-1. The communication interface 3-2 outputs a read command wr_2 of the digital data ts_data and the communication clock signal clk_2 to the start-up circuit 11-2. In the present disclosure, the communication clock signal clk_1 and the communication clock signal clk_2 are clock signals that are not synchronized with each other. The communication clock signal clk_1 and the communication clock signal clk_2 may also be synchronized.
The start-up circuit 11-1 receives a read-out command wr_1 from the communication interface 3-1, and generates and outputs a start-up signal tkick_1 for generating an enable signal ts_en, which will be described later, based on the read-out command wr_1. The enable signal ts_en is a signal output from the control circuit 30 to activate the AD conversion circuit 20. The start signal tkick_1 is output to the control circuit 30 and the start circuit 11-2.
The start-up circuit 11-2 receives the read-out instruction wr_2 from the communication interface 3-2, and generates and outputs a start-up signal tkick_2 for generating the enable signal ts_en based on the read-out instruction wr_2. The start signal tkick_2 is output to the control circuit 30 and the start circuit 11-1.
When the data of the read command wr_1 from the communication interface 3-1 and the start signal tkick_2 from the start circuit 11-2 is "1", the start circuit 11-1 generates and outputs an introduction signal catch_1 for introducing the digital data ts_data from the AD conversion circuit 20, instead of the start signal tkick_1. The import signal catch_1 is output to the control circuit 30.
In addition, when the data of the read command wr_2 from the communication interface 3-2 and the start signal tkick_1 from the start circuit 11-1 is "1", the start circuit 11-2 generates and outputs an introduction signal catch_2 for introducing the digital data ts_data from the AD conversion circuit 20, instead of the start signal tkick_2. The import signal catch_2 is output to the control circuit 30.
The control circuit 30 controls the AD conversion circuit 20 based on the start signal tkick_1 and the lead-in signal catch_1 received as the read request signal from the start circuit 11-1, and the start signal tkick_2 and the lead-in signal catch_2 received as the read request signal from the start circuit 11-2. The control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 to the register 12-1 as the input data data_1. The control circuit 30 outputs the digital data ts_data AD-converted by the AD conversion circuit 20 to the register 12-2 as the input data data_2.
The register 12-1 outputs the import data data_1 from the control circuit 30 to the communication interface 3-1.
The register 12-2 outputs the import data data_2 from the control circuit 30 to the communication interface 3-2.
Next, basic operations of the start-up circuits 11-1 and 11-2 will be described. Fig. 3 is a block diagram showing an example of the internal structure of the start-up circuit. Fig. 4 is a timing chart showing a basic first operation example of the start-up circuit. Fig. 5 is a timing chart showing a basic second operation example of the start-up circuit. Fig. 6 is a timing chart showing a basic third operation example of the start-up circuit. Fig. 7 is a timing chart showing a basic fourth operation example of the start-up circuit. Fig. 4 shows an example in which the read command wr_1 is output from the communication interface 3-1. Fig. 5 shows an example in which the read command wr_2 is output from the communication interface 3-2 in a predetermined period P' after the read command wr_1 is output from the communication interface 3-1. Fig. 6 shows an example in which the read command wr_2 is output from the communication interface 3-2 after the predetermined period P'. Fig. 7 shows an example in which the read command wr_2 from the communication interface 3-2 is output during two cycles of the communication clock signal clk_2 after the read command wr_1 is output from the communication interface 3-1.
As shown in fig. 4, when the control signal generating circuit 111-1 of the start-up circuit 11-1 receives the read command wr_1 from the communication interface 3-1, the data value of the start-up signal tkick_1 is set to "1" in synchronization with the rising edge of the communication clock signal clk_1.
The synchronizing circuit 112-2 of the start-up circuit 11-2 sets the data value of the start-up synchronizing signal sync_tkick_1 to "1" in synchronization with the rising edge two cycles after the rising edge of the communication clock signal clk_2 from the rising edge of the start-up signal tkick_1.
After the lapse of the given period P, the control signal generation circuit 111-1 sets the data value of the start signal tkick_1 to "0" in synchronization with the rising edge of the start reset signal tkick_1_rst output from the control circuit 30.
The synchronizing circuit 112-2 sets the data value of the start-up synchronizing signal sync_tkick_1 to "0" in synchronization with the rising edge of the communication clock signal clk_2 two cycles after the falling edge of the start-up signal tkick_1.
As shown in fig. 5, when the control signal generation circuit 111-2 of the start-up circuit 11-2 receives the read command wr_2 from the communication interface 3-2 in the predetermined period P' in which the data value of the start-up synchronization signal sync_tkick_1 is "1", the data value of the introduction signal catch_2 is set to "1" in synchronization with the rising edge of the communication clock signal clk_2. Then, the control signal generation circuit 111-2 sets the data value of the lead-in signal catch_2 to "0" in synchronization with the rising edge of the lead-in reset signal catch_rst output from the control circuit 30.
As shown in fig. 6, when the control signal generation circuit 111-2 receives the read command wr_2 from the communication interface 3-2 during any one of the given period P in which the data value of the start signal tkick_1 is "1" and the given period P' in which the data value of the start synchronization signal sync_kclk_1 is "1", the data value of the start signal tkick_2 is set to "1" in synchronization with the rising edge of the communication clock signal elk_2.
As shown in fig. 7, the control signal generation circuit 111-2 sets the data value of the start signal tkick_2 to "1" in synchronization with the rising edge of the communication clock signal clk_2 when the read command wr_2 from the communication interface 3-2 is received during two periods of the communication clock signal elk_2 from when the data value of the start signal tkick_1 becomes "1" to when the data value of the start synchronization signal sync_tkick_1 becomes "1". Then, after the predetermined period p has elapsed, the control signal generation circuit 111-2 sets the data value of the start signal tkick_2 to "0" in synchronization with the rising edge of the start reset signal tkick_2_rst output from the control circuit 30.
The synchronizing circuit 112-1 sets the data value of the start-up synchronizing signal sync_tkick_2 to "0" in synchronization with the rising edge two cycles after the communication clock signal clk_1 from the falling edge of the start-up signal tkick_2.
Next, a specific operation of the interface circuit 1 according to the embodiment will be described. Fig. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. Fig. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. Fig. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. Fig. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. Fig. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. Fig. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. Fig. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. Fig. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. Fig. 8 to 11 show diagrams each having, as a start point, a point in time when the read command wr_1 is output from the communication interface 3-1 and the data value of the start signal tkick_1 becomes "1". Fig. 12 to 15 show diagrams each having, as a start point, a point in time when the read command wr_2 is output from the communication interface 3-2 and the data value of the start signal tkick_2 becomes "1".
In the present disclosure, the clock periods of the communication clock signal clk_1 and the communication clock signal clk_2 are considered to be sufficiently small relative to the clock period of the sampling clock signal ts_clk in the AD conversion circuit 20. That is, given periods P, P ', p' shown in fig. 4 to 7 are regarded as being approximately equal. As shown in fig. 8 to 15, in the present disclosure, a period of 10 clock cycles including the sampling clock signal ts_clk from the start signal tkick_1 or the start signal tkick_2 being "1" is referred to as a "standby period P1" in the AD conversion circuit 20, a period of 8 clock cycles including the sampling clock signal ts_clk after the standby period P1 is referred to as an "AD conversion period P2" in the AD conversion circuit 20, and a total period of the standby period P1 and the AD conversion period P2 is referred to as an "operation period P0" of the AD conversion circuit 20. The control circuit 30 has a function of counting the sampling clock signal ts_clk in the AD conversion circuit 20. The standby period P1 corresponds to the given periods P, P ', P' shown in fig. 4 to 7.
The number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2 are examples, and are not limited to the above number of clock cycles. For example, the number of clock cycles included in the standby period P1 may be any number of clock cycles that can ensure a time until the AD conversion in the AD conversion circuit 20 stabilizes. In the present embodiment, the case where the digital data ts_data in the AD conversion circuit 20 is 8-bit data is exemplified, but for example, when the digital data ts_data in the AD conversion circuit 20 is 12-bit data, the AD conversion period P2 may be 12 clock cycles including the sampling clock signal ts_clk. The present disclosure is not limited by the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2.
Fig. 8 to 11 show examples in which the standby period P1, the AD conversion period P2, and the operation period P0 are counted at the time point when the read command wr_1 is output from the communication interface 3-1 and the data value of the start signal tkick_1 output from the start circuit 11-1 becomes "1". That is, in the example shown in fig. 8 to 11, the AD-converted digital data ts_data is introduced into the register 12-1 as the introduction data data_1 based on the read command wr_1 from the communication interface 3-1.
The control circuit 30 starts outputting the sampling clock signal ts_clk in the AD conversion circuit 20 at a point in time when the data value of the start signal tkick_1 becomes "1", and sets the data value of the enable signal ts_en to "1", starting counting of the sampling clock signal ts_clk.
When 10 clock cycles of the sampling clock signal ts_clk have elapsed in the standby period P1, the control circuit 30 sets the data value of the AD conversion command xtcon to "1" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the start-up reset signal tkick_1_rst. Thereby, the data value of the start signal tkick_1 is reset to "0".
The AD conversion circuit 20 converts the analog signal a_sigad from the sensor 2 into digital data ts_data in 8 clock cycles of the sampling clock signal ts_clk of the AD conversion period P2 thereafter.
When 8 clock cycles of the sampling clock signal ts_clk have elapsed in the AD conversion period P2, the control circuit 30 reads out the AD-converted digital data ts_data from the AD conversion circuit 20, and outputs the digital data ts_data as the input data data_1 to the register 12-1. Further, the control circuit 30 sets the data values of the enable signal ts_en and the AD conversion instruction xtcon to "0" in synchronization with the falling edge of the sampling clock signal ts_clk.
In the example shown in fig. 8 and 9, in the standby period P1, the data value of the start signal tkick_2 output from the start circuit 11-2 is "0", that is, the read command wr_2 is not output from the communication interface 3-2. In this case, the control circuit 30 does not output the AD-converted digital data ts_data to the register 12-2.
Fig. 9 shows an example in which the data value of the start signal tkick_2 outputted from the start circuit 11-2 in the AD conversion period P2 is "1", that is, the read command wr_2 is outputted from the communication interface 3-2. In this case, the control circuit 30 starts counting 10 clock cycles of the sampling clock signal ts_clk in the new standby period P1 at the point in time when the data value of the start signal tkick_2 becomes "1". In this case, the control circuit 30 maintains the data value "1" of the enable signal ts_en.
Fig. 10 shows an example in which the data value of the lead-in signal catch_2 output from the start circuit 11-2 in the standby period P1 is "1", that is, the read command wr_2 is output from the communication interface 3-2. In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the imported data data_1 and to the register 12-2 as the imported data data_2.
Further, if 8 clock cycles of the sampling clock signal ts_clk have elapsed in the AD conversion period P2, the control circuit 30 sets the data values of the enable signal ts_en and the AD conversion command xtcon to "0" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the import reset signal catch_rst. Thereby, the data value of the lead-in signal catch_2 is reset to "0".
Fig. 11 shows an example in which the data value of the start signal tkick_1 outputted from the start circuit 11-1 is "1", and the data value of the start signal tkick_2 outputted from the start circuit 11-2 is "1". Here, the fact that the data value of the start signal tkick_1 and the data value of the start signal tkick_2 are simultaneously "1" means that, as shown in fig. 7, the read command wr_2 from the communication interface 3-2 is input during two periods from when the data value of the start signal tkick_1 is "1" to when the data value of the start synchronization signal sync_tkick_1 is "1" of the communication clock signal clk_2. In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the imported data data_1 and to the register 12-2 as the imported data data_2.
Fig. 12 to 15 show examples in which the standby period P1, the AD conversion period P2, and the operation period P0 are counted at the time point when the read command wr_2 is output from the communication interface 3-2 and the data value of the start signal tkick_2 output from the start circuit 11-2 becomes "1". That is, in the example shown in fig. 12 to 15, the AD-converted digital data ts_data is introduced into the register 12-2 as the introduction data data_2 based on the read command wr_2 from the communication interface 3-2.
The control circuit 30 starts outputting the sampling clock signal ts_clk in the AD conversion circuit 20 at a point in time when the data value of the start signal tkick_2 becomes "1", and sets the data value of the enable signal ts_en to "1", starting counting of the sampling clock signal ts_clk.
When 10 clock cycles of the sampling clock signal ts_clk have elapsed in the standby period P1, the control circuit 30 sets the data value of the AD conversion command xtcon to "1" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the start-up reset signal tkick_2_rst. Thereby, the data value of the start signal tkick_2 is reset to "0".
The AD conversion circuit 20 converts the analog signal a_sigad from the sensor 2 into digital data ts_data in 8 clock cycles of the sampling clock signal ts_clk of the AD conversion period P2 thereafter.
When 8 clock cycles of the sampling clock signal ts_clk have elapsed in the AD conversion period P2, the control circuit 30 reads out the AD-converted digital data ts_data from the AD conversion circuit 20, and outputs the digital data as the input data data_2 to the register 12-2. Further, the control circuit 30 sets the data values of the enable signal ts_en and the AD conversion instruction xtcon to "0" in synchronization with the falling edge of the sampling clock signal ts_clk.
In the example shown in fig. 12 and 13, in the standby period P1, the data value of the start signal tkick_1 output from the start circuit 11-1 is "0", that is, the read command wr_1 is not output from the communication interface 3-1. In this case, the control circuit 30 does not output the AD-converted digital data ts_data to the register 12-1.
Fig. 13 shows an example in which the data value of the start signal tkick_1 output from the start circuit 11-1 is "1" in the AD conversion period P2, that is, the read command wr_1 is output from the communication interface 3-1. In this case, the control circuit 30 starts counting 10 clock cycles of the sampling clock signal ts_clk in the new standby period P1 at the point in time when the data value of the start signal tkick_1 becomes "1". In this case, the control circuit 30 maintains the data value "1" of the enable signal ts_en.
Fig. 14 shows an example in which the data value of the lead-in signal catch_1 output from the start circuit 11-1 is "1" in the standby period P1, that is, the read command wr_1 is output from the communication interface 3-1. In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-2 as the imported data data_2 and to the register 12-1 as the imported data data_1.
Further, if 8 clock cycles of the sampling clock signal ts_clk have elapsed in the AD conversion period P2, the control circuit 30 sets the data values of the enable signal ts_en and the AD conversion command xtcon to "0" in synchronization with the falling edge of the sampling clock signal ts_clk, and outputs the import reset signal catch_rst. Thereby, the data value of the lead-in signal catch_1 is reset to "0".
Fig. 15 shows an example in which the data value of the start signal tkick_2 output from the start circuit 11-2 is "1", and the data value of the start signal tkick_1 output from the start circuit 11-1 is "1". In this case, the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-2 as the imported data data_2 and to the register 12-1 as the imported data data_1.
Fig. 16 is a diagram showing an output target of digital data in each operation example shown in fig. 8 to 15. As shown in fig. 16, the control circuit 30 sets the communication device 10-1 to be the output target of the digital data ts_data at the point in time when the data value of the start signal tkick_1 output from the start circuit 11-1 becomes "1". In addition, if the data value of the lead-in signal catch_2 output from the start-up circuit 11-2 becomes "1" in the standby period P1 of the AD conversion circuit 20 immediately after the data value of the start-up signal tkick_1 output from the start-up circuit 11-1 becomes "1", the control circuit 30 sets the communication device 10-2 as an output target of the digital data ts_data.
As shown in fig. 16, the control circuit 30 sets the communication device 10-2 to be the output target of the digital data ts_data at the point in time when the data value of the start signal tkick_2 output from the start circuit 11-2 becomes "1". Further, if the data value of the lead-in signal catch_1 output from the start-up circuit 11-1 becomes "1" in the standby period P1 of the AD conversion circuit 20 immediately after the data value of the start-up signal tkick_2 output from the start-up circuit 11-2 becomes "1", the control circuit 30 sets the communication device 10-1 as an output target of the digital data ts_data.
In addition, fig. 15 shows an example in which the data value of the start signal tkick_2 output from the start circuit 11-2 is "1" and the data value of the start signal tkick_1 output from the start circuit 11-1 is "1", but in fig. 16, when the data value of the start signal tkick_1 output from the start circuit 11-1 is "1" and the data value of the start signal tkick_2 output from the start circuit 11-2 is "1", the control circuit 30 outputs the AD-converted digital data ts_data to the register 12-1 as the input data data_1 and to the register 12-2 as the input data data_2.
In the present embodiment, since the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2 as described above, the circuit scale and power consumption of the communication apparatus 100 can be reduced. Specifically, in the present embodiment, the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2, as compared with a configuration in which an analog circuit and an AD conversion circuit are provided for each communication device (that is, a configuration including a plurality of analog circuits, a plurality of AD conversion circuits, and a plurality of communication devices). By reducing the AD conversion circuit, the circuit area can be reduced. In addition, by reducing the AD conversion circuits, the power consumed by the plurality of AD conversion circuits can also be reduced.
Further, the time required for reading out the digital data ts_data can be shortened. Specifically, in the present embodiment, not only one AD conversion circuit but also a control circuit for reading out digital data in response to read-out request signals from a plurality of communication devices is provided in common. If only the AD conversion circuit is shared, the operation of one communication device is completed and then the operation of the other communication device is started. As a result, the AD conversion circuit needs to operate by an amount corresponding to the number of communication devices. However, in the embodiment of the present application, the control circuit controls the operation period of the AD conversion circuit 20 as described above.
In the above-described embodiment, the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2, but the AD conversion circuit 20 may be shared by a plurality of three or more communication devices.
Fig. 17 is a diagram showing a configuration example in which an AD conversion circuit is shared by six communication devices. Fig. 18 is a diagram showing an example of an output target of digital data in the configuration example shown in fig. 17.
In the configuration example shown in fig. 17, as shown in example 1 of fig. 18, the start signal tkick_1 is output from the communication device 10-1, and the lead-in signal catch_5 is output from the communication device 10-5 during the standby period P1, and in this case, the control circuit 30 sets the communication device 10-1 and the communication device 10-5 as the output target of the digital data ts_data.
In the configuration example shown in fig. 17, as shown in example 2 of fig. 18, the start signal tkick_4 is output from the communication device 10-4, the lead-in signal catch_1 is output from the communication device 10-1 and the lead-in signal catch_6 is output from the communication device 10-6 in the standby period P1, and in this case, the control circuit 30 sets the communication device 10-1, the communication device 10-4, and the communication device 10-6 as the output targets of the digital data ts_data.
In the configuration example shown in fig. 17, as shown in example 3 of fig. 18, the start signal tkick_2 is output from the communication device 10-2, the lead-in signal catch_3 is output from the communication device 10-3 and the lead-in signal catch_5 is output from the communication device 10-5 in the standby period P1, and in this case, the control circuit 30 sets the communication device 10-2, the communication device 10-3, and the communication device 10-5 as the output target of the digital data ts_data.
In the configuration example shown in fig. 17, as shown in example 4 of fig. 18, the start signal tkick_5 is output from the communication device 10-5, the lead-in signal catch_1 is output from the communication device 10-1, the lead-in signal catch_2 is output from the communication device 10-2, and the lead-in signal catch_6 is output from the communication device 10-6 in the standby period P1, and in this case, the control circuit 30 sets the communication device 10-1, the communication device 10-2, the communication device 10-5, and the communication device 10-6 to be the output target of the digital data ts_data.
In the configuration example shown in fig. 17, as shown in example 5 of fig. 18, the start signal tkick_3 and the start signal tkick_6 are simultaneously output from the communication device 10-3 and the communication device 10-6, and in this case, the control circuit 30 sets the communication device 10-3 and the communication device 10-6 as the output target of the digital data ts_data.
As described above, in the interface circuit 1 according to the embodiment, the AD conversion circuit 20 can be shared by the plurality of communication devices 10. This can reduce the circuit scale and power consumption of the communication device 100. In addition, the time required for reading out data can be shortened.
The embodiments described above are for easy understanding of the present application and are not intended to limit the present application. The present application is capable of modification/improvement without departing from the gist thereof, and the present application also includes equivalents thereof.
Further, the present disclosure can take the following configuration as described above or instead of the above.
(1) An interface circuit according to an aspect of the present application includes: a plurality of communication devices; an AD conversion circuit for converting the analog signal AD into digital data; and a control circuit that reads out the digital data in accordance with read-out request signals from the plurality of communication devices.
In a configuration in which an AD conversion circuit is provided for each of a plurality of communication devices, a current consumption corresponding to the plurality of AD conversion circuits is required. In the above configuration, the AD conversion circuit is shared by a plurality of communication devices. This can reduce the circuit scale and power consumption of the interface circuit, compared with a configuration in which an AD conversion circuit is provided for each of a plurality of communication devices.
(2) In the interface circuit of the above (1), the control circuit may output the digital data to a first communication device of the plurality of communication devices when a read request signal from the first communication device is received, and may output the digital data to a second communication device different from the first communication device when a read request signal from the second communication device is received.
In this configuration, the AD conversion circuit can be shared by a plurality of communication devices.
(3) In the interface circuit of the above (1), the control circuit may output the digital data to a second communication device different from the first communication device when the AD conversion circuit needs a standby period after receiving the read request signal from the first communication device among the plurality of communication devices and the read request signal from the second communication device is received in the standby period.
If only the AD conversion circuit is shared, the operation of one communication device is completed and then the operation of the other communication device is started. As a result, the AD conversion circuit needs to operate by an amount corresponding to the number of communication devices. In the interface circuit of the present configuration, the time required for reading data can be shortened by the above-described processing.
(4) In the interface circuit of (1), the communication device includes: a communication interface for outputting a read instruction of the digital data; and a start-up circuit that generates, as the read-out request signal, a start-up signal for causing the AD conversion circuit to start up or an import signal for importing the digital data, the communication device including a first communication device and a second communication device different from the first communication device, the start-up circuit of the second communication device outputting the import signal when the AD conversion circuit needs a standby period after the start-up signal is output from the start-up circuit of the first communication device and the read-out instruction output from a communication interface of the second communication device is received during the standby period.
In this configuration, digital data is simultaneously output to both the communication device that outputs the start signal and the communication device that outputs the lead-in signal during standby. This can shorten the time required for reading data. Further, the circuit scale of the starting circuit can be reduced.
(5) The communication device according to one aspect of the present application includes: an interface circuit of any one of the above (1) to (4); a power amplifier circuit that amplifies the high frequency signal; and a sensor that detects a temperature of the power amplifier circuit and outputs the detected value as the analog signal.
In an interface circuit having a configuration in which each of a plurality of communication devices is provided with an AD conversion circuit, a current consumption corresponding to the plurality of AD conversion circuits is required. In the configuration using the interface circuit having the present configuration in which the AD conversion circuit is shared by the plurality of communication devices, the circuit scale and power consumption of the interface circuit can be reduced as compared with a configuration in which the AD conversion circuit is provided for each of the plurality of communication devices. Therefore, the circuit scale and power consumption of the communication device can be reduced. Further, if only the AD conversion circuit is shared, after the operation of one communication device is completed, the operation of the other communication device is started. As a result, the AD conversion circuit needs to operate by an amount corresponding to the number of communication devices. In the configuration using the interface circuit of the present configuration, the time required for reading data can be shortened by the above-described processing.
According to the present disclosure, the circuit scale and the power consumption can be reduced, and furthermore, the time required for reading data can be shortened.
Claims (3)
1. An interface circuit is provided with:
a plurality of communication devices;
an AD conversion circuit for converting the analog signal AD into digital data; and
a control circuit for reading out the digital data in accordance with read-out request signals from a plurality of the communication devices,
the AD conversion circuit needs a standby period after receiving a read request signal from a first communication device among the plurality of communication devices, and in a case where a read request signal from a second communication device different from the first communication device is received in the standby period, the control circuit outputs the digital data to the second communication device.
2. An interface circuit is provided with:
a plurality of communication devices;
an AD conversion circuit for converting the analog signal AD into digital data; and
a control circuit for reading out the digital data in accordance with read-out request signals from a plurality of the communication devices,
the communication device is provided with:
a communication interface for outputting a read instruction of the digital data; and
a start-up circuit configured to generate, as the read-out request signal, a start-up signal for starting up the AD conversion circuit or an import signal for importing the digital data, based on the read-out instruction,
the communication device comprises a first communication device and a second communication device different from the first communication device,
the AD conversion circuit needs a standby period after the start signal is output from the start circuit of the first communication device, and the start circuit of the second communication device outputs the lead-in signal when the read instruction output from the communication interface of the second communication device is received in the standby period.
3. A communication device is provided with:
the interface circuit of claim 1 or 2;
a power amplifier circuit that amplifies the high frequency signal; and
and a sensor that detects the temperature of the power amplifier circuit and outputs the detected value as the analog signal.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018233833 | 2018-12-13 | ||
| JP2018-233833 | 2018-12-13 | ||
| JP2019-170793 | 2019-09-19 | ||
| JP2019170793A JP2020098565A (en) | 2018-12-13 | 2019-09-19 | Interface circuit and communication device |
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| Publication Number | Publication Date |
|---|---|
| CN111327318A CN111327318A (en) | 2020-06-23 |
| CN111327318B true CN111327318B (en) | 2023-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911272177.6A Active CN111327318B (en) | 2018-12-13 | 2019-12-11 | Interface circuit and communication device |
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| Country | Link |
|---|---|
| JP (1) | JP2020098565A (en) |
| CN (1) | CN111327318B (en) |
| TW (1) | TWI747075B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4562545A (en) * | 1981-10-30 | 1985-12-31 | Hitachi, Ltd. | Method of taking-in input data for motorcar control |
| CN106573583A (en) * | 2014-08-22 | 2017-04-19 | 三菱电机株式会社 | Vehicle-mounted electronic control device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8792521B2 (en) * | 2011-09-23 | 2014-07-29 | Broadcom Corporation | Multi-standard front end using wideband data converters |
| TWI652913B (en) * | 2016-10-28 | 2019-03-01 | 絡達科技股份有限公司 | Multi-mode multi-band transceiver, radio frequency front-end circuit and radio frequency system using the same |
-
2019
- 2019-09-19 JP JP2019170793A patent/JP2020098565A/en active Pending
- 2019-11-07 TW TW108140436A patent/TWI747075B/en active
- 2019-12-11 CN CN201911272177.6A patent/CN111327318B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4562545A (en) * | 1981-10-30 | 1985-12-31 | Hitachi, Ltd. | Method of taking-in input data for motorcar control |
| CN106573583A (en) * | 2014-08-22 | 2017-04-19 | 三菱电机株式会社 | Vehicle-mounted electronic control device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI747075B (en) | 2021-11-21 |
| TW202029667A (en) | 2020-08-01 |
| JP2020098565A (en) | 2020-06-25 |
| CN111327318A (en) | 2020-06-23 |
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