CN111327318A

CN111327318A - Interface circuit and communication device

Info

Publication number: CN111327318A
Application number: CN201911272177.6A
Authority: CN
Inventors: 松村俊树; 新富雄二; 松村哲; 中牟田和周
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2018-12-13
Filing date: 2019-12-11
Publication date: 2020-06-23
Anticipated expiration: 2039-12-11
Also published as: TWI747075B; TW202029667A; JP2020098565A; CN111327318B

Abstract

The invention provides an interface circuit and a communication device capable of reducing circuit scale and power consumption. The interface circuit (1) is provided with: a plurality of communication devices (10-1, 10-2); an AD conversion circuit (20) for AD converting the analog signal into digital data; and a control circuit (30) that reads out the digital data in accordance with read-out request signals from the plurality of communication devices (10-1, 10-2).

Description

Interface circuit and communication device

Technical Field

The invention relates to an interface circuit and a communication device.

Background

In recent years, mobile communication terminals such as mobile phones and smart phones are required to be capable of multi-band and multi-mode operation for multiple frequencies and wireless systems with one terminal. Such a communication device that can cope with multi-band and multi-mode needs to process a plurality of transmission/reception signals at high speed without deteriorating quality. For example, LAA (Licensed-Assisted Access) is standardized, in which an unlicensed band of a 5GHz band used in a wireless LAN is used as a secondary cell of Carrier Aggregation (CA) in LTE-Advanced, thereby improving throughput.

A communication device generally has a structure in which a gain due to a temperature change is compensated by monitoring a temperature. For example, a configuration is disclosed in which an analog signal from one temperature sensor is AD-converted and introduced (for example, patent document 1).

Prior art documents

Patent document

Patent document 1: specification of U.S. Pat. No. 8526995

For example, in a configuration in which a communication device for wireless LAN and a communication device for LTE are present in a mixed manner, if a temperature sensor and an AD conversion circuit are provided for each communication device, there is a problem that the circuit scale and power consumption increase.

Disclosure of Invention

Problems to be solved by the invention

The present invention has been made in view of the above circumstances, and an object thereof is to realize an interface circuit and a communication device capable of reducing the circuit scale and power consumption.

Means for solving the problems

An interface circuit according to an aspect of the present invention includes: a plurality of communication devices; an AD conversion circuit for AD converting the analog signal into digital data; and a control circuit that reads out the digital data in accordance with read-out request signals from the plurality of communication devices.

In this configuration, the AD conversion circuit is shared by a plurality of communication devices. This reduces the circuit scale and power consumption of the interface circuit.

A communication device according to an aspect of the present invention includes: the above-mentioned interface circuit; a power amplifier circuit that amplifies the high-frequency signal; and a sensor that detects a temperature of the power amplifier circuit and outputs a detected value as the analog signal.

In this configuration, the AD conversion circuit is shared by a plurality of communication devices, whereby the circuit scale and power consumption of the communication apparatus can be reduced.

Effects of the invention

According to the present invention, it is possible to provide an interface circuit and a communication device capable of reducing the circuit scale and power consumption.

Drawings

Fig. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to an embodiment.

Fig. 2 is a diagram showing an example of a configuration of a main part of a communication apparatus according to an embodiment.

Fig. 3 is a block diagram showing an example of the internal configuration of the start-up circuit.

Fig. 4 is a timing chart showing a basic first operation example of the startup circuit.

Fig. 5 is a timing chart showing a basic second operation example of the startup circuit.

Fig. 6 is a timing chart showing a basic third operation example of the startup circuit.

Fig. 7 is a timing chart showing a basic fourth operation example of the startup circuit.

Fig. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment.

Fig. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment.

Fig. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment.

Fig. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment.

Fig. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment.

Fig. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment.

Fig. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment.

Fig. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment.

Fig. 16 is a diagram showing an output target of digital data in each operation example shown in fig. 8 to 15.

Fig. 17 is a diagram showing a configuration example in which the AD conversion circuit is shared by six communication devices.

Fig. 18 is a diagram showing an example of digital data output targets in the configuration example shown in fig. 17.

Description of the reference numerals

1: an interface circuit;

2: a sensor;

3-1, 3-2: a communication interface;

4: a power amplifier circuit;

10. 10-1, 10-2, 10-3, 10-4, 10-5, 10-6: a communication device;

11-1, 11-2: a start-up circuit;

12-1, 12-2: a register;

20: an AD conversion circuit;

30: a control circuit;

100: a communication device;

111-1, 111-2: a control signal generation circuit;

112-1, 112-2: a synchronization circuit.

Detailed Description

Hereinafter, an interface circuit and a communication device according to an embodiment will be described in detail with reference to the drawings. The present invention is not limited to the embodiments. It is needless to say that the respective embodiments are examples, and partial replacement or combination of the structures described in the different embodiments can be performed. In embodiment 2 and thereafter, descriptions of common matters with embodiment 1 are omitted, and only differences will be described. In particular, the same operational effects based on the same structure will not be mentioned in each embodiment.

(embodiment mode 1)

Fig. 1 is a block diagram showing an example of a schematic configuration of an interface circuit according to an embodiment. Fig. 2 is a diagram showing an example of a configuration of a main part of a communication apparatus according to an embodiment. As shown in fig. 1, the interface circuit 1 includes communication devices 10-1 and 10-2, an AD conversion circuit 20, and a control circuit 30. In the present disclosure, the communication device 10-1 is, for example, a communication device for LTE of a 5GHz band, and the communication device 10-2 is, for example, a communication device for WiFi. In the present disclosure, the AD conversion circuit 20 AD converts the analog signal a _ sig from the sensor 2 into digital data ts _ data. In the present disclosure, the sensor 2 and the AD conversion circuit 20 are shared by the two communication devices 10-1 and 10-2. In the following description, since the two communication devices 10-1, 10-2 and their constituent elements are the same, the symbols "-1", "-2", "_ 1", "_ 2" are omitted without distinguishing the two communication devices 10-1, 10-2 and their constituent elements.

As shown in fig. 2, when the interface circuit 1 according to the embodiment is applied to the communication device 100, the sensor 2 may be, for example, a temperature sensor that detects the temperature of the power amplifier circuit 4 for high-frequency amplification, but is not limited thereto, and may be, for example, an ultrasonic sensor, an infrared sensor, or a vibration sensor. The sensor 2 may be an analog circuit, and may be a voltmeter, an ammeter, or the like.

The communication device 10 outputs a read request signal of digital data ts _ data obtained by AD converting an analog signal a _ sig which is a detection value of the sensor 2.

The control circuit 30 reads out the digital data ts _ data from the AD conversion circuit 20 based on the read request signal (a start signal tkick and an introduction signal catch described later) output from the communication device 10, and outputs the digital data ts _ data to the communication device 10.

As shown in fig. 1, the communication device 10-1 includes a communication interface 3-1, a start circuit 11-1, and a register 12-1. The communication device 10-2 is provided with a communication interface 3-2, a start circuit 11-2, and a register 12-2.

In the present disclosure, the communication interface 3-1 is, for example, a serial communication interface in the communication device 10-1 for LTE of a 5GHz band, and the communication interface 3-2 is, for example, a serial communication interface in the communication device 10-2 for WiFi.

The communication interface 3-1 outputs a read instruction wr _1 of the digital data ts _ data and a communication clock signal clk _1 to the startup circuit 11-1. The communication interface 3-2 outputs the read instruction wr _2 of the digital data ts _ data and the communication clock signal clk _2 to the start-up circuit 11-2. In the present disclosure, the communication clock signal clk _1 and the communication clock signal clk _2 are clock signals that are not synchronized with each other. Communication clock signal clk _1 and communication clock signal clk _2 may also be synchronized.

The start circuit 11-1 receives a read command wr _1 from the communication interface 3-1, and generates and outputs a start signal tkick _1 for generating an enable signal ts _ en, which will be described later, based on the read command wr _ 1. The enable signal ts _ en is a signal output from the control circuit 30 to activate the AD conversion circuit 20. The start signal tkick _1 is output to the control circuit 30 and the start circuit 11-2.

The start circuit 11-2 receives a read instruction wr _2 from the communication interface 3-2, and generates and outputs a start signal tkick _2 for generating an enable signal ts _ en based on the read instruction wr _ 2. The start signal tkick _2 is output to the control circuit 30 and the start circuit 11-1.

When the data of the read command wr _1 from the communication interface 3-1 and the start signal tkick _2 from the start circuit 11-2 is "1", the start circuit 11-1 generates and outputs an introduction signal catch _1 for introducing the digital data ts _ data from the AD conversion circuit 20, instead of the start signal tkick _ 1. The introduction signal catch _1 is output to the control circuit 30.

When the data of the read command wr _2 from the communication interface 3-2 and the start signal tkick _1 from the start circuit 11-1 is "1", the start circuit 11-2 generates and outputs an introduction signal catch _2 for introducing the digital data ts _ data from the AD conversion circuit 20, instead of the start signal tkick _ 2. The introduction signal catch _2 is output to the control circuit 30.

The control circuit 30 controls the AD conversion circuit 20 based on the boot signal tkick _1 and the introduction signal catch _1 received as the read request signal from the boot circuit 11-1, and the boot signal tkick _2 and the introduction signal catch _2 received as the read request signal from the boot circuit 11-2. The control circuit 30 outputs the digital data ts _ data AD-converted by the AD conversion circuit 20 to the register 12-1 as the input data _ 1. The control circuit 30 outputs the digital data ts _ data AD-converted by the AD conversion circuit 20 to the register 12-2 as the input data _ 2.

The register 12-1 outputs the import data _1 from the control circuit 30 to the communication interface 3-1.

The register 12-2 outputs the import data _2 from the control circuit 30 to the communication interface 3-2.

Next, the basic operation of the start-up circuit 11-1 and the start-up circuit 11-2 will be described. Fig. 3 is a block diagram showing an example of the internal configuration of the start-up circuit. Fig. 4 is a timing chart showing a basic first operation example of the startup circuit. Fig. 5 is a timing chart showing a basic second operation example of the startup circuit. Fig. 6 is a timing chart showing a basic third operation example of the startup circuit. Fig. 7 is a timing chart showing a basic fourth operation example of the startup circuit. Fig. 4 shows an example in which the read command wr _1 is output from the communication interface 3-1. Fig. 5 shows an example in which the read command wr _2 is output from the communication interface 3-2 in a predetermined period P' after the read command wr _1 is output from the communication interface 3-1. Fig. 6 shows an example in which the read instruction wr _2 is output from the communication interface 3-2 after a given period P'. Fig. 7 shows an example in which the read instruction wr _2 from the communication interface 3-2 is output during two cycles of the communication clock signal clk _2 after the read instruction wr _1 is output from the communication interface 3-1.

As shown in fig. 4, when the control signal generation circuit 111-1 of the start circuit 11-1 receives the read command wr _1 from the communication interface 3-1, the data value of the start signal tkick _1 is set to "1" in synchronization with the rising edge of the communication clock signal clk _ 1.

The synchronizing circuit 112-2 of the start circuit 11-2 sets the data value of the start synchronizing signal sync _ tkick _1 to "1" in synchronization with the rising edge of the communication clock signal clk _2 two cycles after the rising edge of the start signal tkick _ 1.

After a given period P has elapsed, the control signal generation circuit 111-1 sets the data value of the start signal tkick _1 to "0" in synchronization with the rising edge of the start reset signal tkick _1_ rst output from the control circuit 30.

The synchronizing circuit 112-2 sets the data value of the start synchronizing signal sync _ tkick _1 to "0" in synchronization with the rising edge of the communication clock signal clk _2 two cycles after the falling edge of the start signal tkick _ 1.

As shown in fig. 5, when the control signal generation circuit 111-2 of the start circuit 11-2 receives the read command wr _2 from the communication interface 3-2 in the predetermined period P' in which the data value of the start synchronization signal sync _ tkick _1 is "1", the data value of the introduction signal catch _2 is set to "1" in synchronization with the rising edge of the communication clock signal clk _ 2. Then, the control signal generation circuit 111-2 sets the data value of the introduction signal catch _2 to "0" in synchronization with the rising edge of the introduction reset signal catch _ rst output from the control circuit 30.

As shown in fig. 6, when the control signal generation circuit 111-2 receives the read command wr _2 from the communication interface 3-2 during any one of the predetermined period P during which the data value of the start signal tkick _1 is "1" and the predetermined period P' during which the data value of the start synchronization signal sync _ kick _1 is "1", the data value of the start signal tkick _2 is set to "1" in synchronization with the rising edge of the communication clock signal elk _ 2.

As shown in fig. 7, when the control signal generation circuit 111-2 receives the read command wr _2 from the communication interface 3-2 in two cycles of the communication clock signal elk _2 from when the data value of the start signal tkick _1 becomes "1" to when the data value of the start synchronization signal sync _ tkick _1 becomes "1", the data value of the start signal tkick _2 is set to "1" in synchronization with the rising edge of the communication clock signal clk _ 2. Then, after the given period p has elapsed, the control signal generation circuit 111-2 sets the data value of the start signal tkick _2 to "0" in synchronization with the rising edge of the start reset signal tkick _2_ rst output from the control circuit 30.

The synchronizing circuit 112-1 sets the data value of the start synchronizing signal sync _ tkick _2 to "0" in synchronization with the rising edge of the communication clock signal clk _1 after two cycles from the falling edge of the start signal tkick _ 2.

Next, a specific operation of the interface circuit 1 according to the embodiment will be described. Fig. 8 is a timing chart showing a specific first operation example of the interface circuit according to the embodiment. Fig. 9 is a timing chart showing a specific second operation example of the interface circuit according to the embodiment. Fig. 10 is a timing chart showing a specific third operation example of the interface circuit according to the embodiment. Fig. 11 is a timing chart showing a specific fourth operation example of the interface circuit according to the embodiment. Fig. 12 is a timing chart showing a specific fifth operation example of the interface circuit according to the embodiment. Fig. 13 is a timing chart showing a specific sixth operation example of the interface circuit according to the embodiment. Fig. 14 is a timing chart showing a specific seventh operation example of the interface circuit according to the embodiment. Fig. 15 is a timing chart showing a specific eighth operation example of the interface circuit according to the embodiment. Fig. 8 to 11 show diagrams starting from a point in time when the read command wr _1 is output from the communication interface 3-1 and the data value of the start signal tkick _1 becomes "1". Fig. 12 to 15 show diagrams starting from a point in time when the read command wr _2 is output from the communication interface 3-2 and the data value of the start signal tkick _2 becomes "1".

In the present disclosure, the clock periods of the communication clock signal clk _1 and the communication clock signal clk _2 are regarded as sufficiently small with respect to the clock period of the sampling clock signal ts _ clk in the AD conversion circuit 20. That is, the predetermined periods P, P ', p, and p' shown in fig. 4 to 7 are regarded as being substantially equal to each other. As shown in fig. 8 to 15, in the present disclosure, a period of 10 clock cycles including the sampling clock signal ts _ clk from when the data value of the start signal tkick _1 or the start signal tkick _2 becomes "1" is defined as "standby period P1" in the AD conversion circuit 20, a period of 8 clock cycles including the sampling clock signal ts _ clk after the standby period P1 is defined as "AD conversion period P2" in the AD conversion circuit 20, and a total period of the standby period P1 and the AD conversion period P2 is defined as "operation period P0" in the AD conversion circuit 20. The control circuit 30 has a function of counting the sampling clock signal ts _ clk in the AD conversion circuit 20. The standby period P1 corresponds to the predetermined periods P, P ', P' shown in fig. 4 to 7.

The number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2 are examples, and are not limited to the above number of clock cycles. For example, the number of clock cycles included in the standby period P1 may be any number of clock cycles that can secure a time until the AD conversion in the AD conversion circuit 20 is stable. Note that, in the present embodiment, the case where the digital data ts _ data in the AD conversion circuit 20 is 8-bit data is exemplified, but for example, when the digital data ts _ data in the AD conversion circuit 20 is 12-bit data, the AD conversion period P2 may be in the form of 12 clock cycles including the sampling clock signal ts _ clk. The present disclosure is not limited by the number of clock cycles included in the standby period P1 and the number of clock cycles included in the AD conversion period P2.

Fig. 8 to 11 show an example in which counting of the standby period P1, the AD conversion period P2, and the operation period P0 is started at a time point when the read command wr _1 is output from the communication interface 3-1 and the data value of the startup signal tkick _1 output from the startup circuit 11-1 becomes "1". That is, in the example shown in fig. 8 to 11, the digital data ts _ data after AD conversion is imported as import data _1 to the register 12-1 based on the read command wr _1 from the communication interface 3-1.

The control circuit 30 starts the output of the sampling clock signal ts _ clk in the AD conversion circuit 20 at the time point when the data value of the start signal tkick _1 becomes "1", sets the data value of the enable signal ts _ en to "1", and starts the counting of the sampling clock signal ts _ clk.

If 10 clock cycles of the sampling clock signal ts _ clk have elapsed in the standby period P1, the control circuit 30 sets the data value of the AD conversion instruction xTCONV to "1" in synchronization with the falling edge of the sampling clock signal ts _ clk, and outputs the start reset signal tkick _1_ rst. Thus, the data value of the start signal tkick _1 is reset to "0".

The AD conversion circuit 20 converts the analog signal a _ sigAD from the sensor 2 into digital data ts _ data in 8 clock cycles of the sampling clock signal ts _ clk in the AD conversion period P2 thereafter.

When 8 clock cycles of the sampling clock signal ts _ clk have elapsed in the AD conversion period P2, the control circuit 30 reads out the digital data ts _ data after the AD conversion from the AD conversion circuit 20, and outputs the digital data ts _ data as the input data _1 to the register 12-1. The control circuit 30 sets the enable signal ts _ en and the data value of the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts _ clk.

In the example shown in fig. 8 and 9, in the standby period P1, the data value of the start signal tkick _2 output from the start circuit 11-2 is "0", that is, the read command wr _2 is not output from the communication interface 3-2. In this case, the control circuit 30 does not output the AD-converted digital data ts _ data to the register 12-2.

Fig. 9 shows an example in which the data value of the boot signal tkick _2 output from the boot circuit 11-2 during the AD conversion period P2 is "1", that is, the read command wr _2 is output from the communication interface 3-2. In this case, the control circuit 30 starts counting of 10 clock cycles of the sampling clock signal ts _ clk in the new standby period P1 at the time point when the data value of the start signal tkick _2 becomes "1". Further, in this case, the control circuit 30 maintains the data value "1" of the enable signal ts _ en.

Fig. 10 shows an example in which the data value of the lead-in signal catch _2 outputted from the startup circuit 11-2 during the standby period P1 is "1", that is, the read command wr _2 is outputted from the communication interface 3-2. In this case, the control circuit 30 outputs the AD-converted digital data ts _ data to the register 12-1 as the import data _1 and outputs the AD-converted digital data ts _ data to the register 12-2 as the import data _ 2.

Further, when 8 clock cycles of the sampling clock signal ts _ clk have elapsed in the AD conversion period P2, the control circuit 30 sets the data values of the enable signal ts _ en and the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts _ clk, and outputs the lead-in reset signal catch _ rst. Thereby, the data value of the lead-in signal catch _2 is reset to "0".

Fig. 11 shows an example in which the data value of the start signal tkick _1 output from the start circuit 11-1 becomes "1", and the data value of the start signal tkick _2 output from the start circuit 11-2 becomes "1". Here, the fact that the data value of the start signal tkick _1 and the data value of the start signal tkick _2 are simultaneously "1" means that, as shown in fig. 7, the read command wr _2 from the communication interface 3-2 is input during two cycles of the communication clock signal clk _2 from when the data value of the start signal tkick _1 becomes "1" until the data value of the start synchronization signal sync _ tkick _1 becomes "1". In this case, the control circuit 30 outputs the AD-converted digital data ts _ data to the register 12-1 as the import data _1 and outputs the AD-converted digital data ts _ data to the register 12-2 as the import data _ 2.

Fig. 12 to 15 show an example in which counting of the standby period P1, the AD conversion period P2, and the operation period P0 is started at a time point when the read command wr _2 is output from the communication interface 3-2 and the data value of the startup signal tkick _2 output from the startup circuit 11-2 becomes "1". That is, in the example shown in fig. 12 to 15, the digital data ts _ data after AD conversion is imported as the import data _2 to the register 12-2 based on the read command wr _2 from the communication interface 3-2.

The control circuit 30 starts the output of the sampling clock signal ts _ clk in the AD conversion circuit 20 at the time point when the data value of the start signal tkick _2 becomes "1", sets the data value of the enable signal ts _ en to "1", and starts the counting of the sampling clock signal ts _ clk.

If 10 clock cycles of the sampling clock signal ts _ clk have elapsed in the standby period P1, the control circuit 30 sets the data value of the AD conversion instruction xTCONV to "1" in synchronization with the falling edge of the sampling clock signal ts _ clk, and outputs the start reset signal tkick _2_ rst. Thus, the data value of the start signal tkick _2 is reset to "0".

When 8 clock cycles of the sampling clock signal ts _ clk have elapsed in the AD conversion period P2, the control circuit 30 reads the digital data ts _ data after the AD conversion from the AD conversion circuit 20 and outputs the digital data ts _ data as the input data _2 to the register 12-2. The control circuit 30 sets the enable signal ts _ en and the data value of the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts _ clk.

In the example shown in fig. 12 and 13, in the standby period P1, the data value of the startup signal tkick _1 output from the startup circuit 11-1 is "0", that is, the read command wr _1 is not output from the communication interface 3-1. In this case, the control circuit 30 does not output the AD-converted digital data ts _ data to the register 12-1.

Fig. 13 shows an example in which the data value of the boot signal tkick _1 output from the boot circuit 11-1 is "1", that is, the read command wr _1 is output from the communication interface 3-1 in the AD conversion period P2. In this case, the control circuit 30 starts counting of 10 clock cycles of the sampling clock signal ts _ clk in the new standby period P1 at the time point when the data value of the start signal tkick _1 becomes "1". Further, in this case, the control circuit 30 maintains the data value "1" of the enable signal ts _ en.

Fig. 14 shows an example in which, in the standby period P1, the data value of the lead-in signal catch _1 output from the startup circuit 11-1 is "1", that is, the read command wr _1 is output from the communication interface 3-1. In this case, the control circuit 30 outputs the AD-converted digital data ts _ data to the register 12-2 as the import data _2 and outputs the AD-converted digital data ts _ data to the register 12-1 as the import data _ 1.

Further, when 8 clock cycles of the sampling clock signal ts _ clk have elapsed in the AD conversion period P2, the control circuit 30 sets the data values of the enable signal ts _ en and the AD conversion command xTCONV to "0" in synchronization with the falling edge of the sampling clock signal ts _ clk, and outputs the lead-in reset signal catch _ rst. Thereby, the data value of the lead-in signal catch _1 is reset to "0".

Fig. 15 shows an example in which the data value of the start signal tkick _2 output from the start circuit 11-2 is "1", and the data value of the start signal tkick _1 output from the start circuit 11-1 is "1". In this case, the control circuit 30 outputs the AD-converted digital data ts _ data to the register 12-2 as the import data _2 and outputs the AD-converted digital data ts _ data to the register 12-1 as the import data _ 1.

Fig. 16 is a diagram showing an output target of digital data in each operation example shown in fig. 8 to 15. As shown in fig. 16, the control circuit 30 sets the communication device 10-1 as the output destination of the digital data ts _ data at the time point when the data value of the start signal tkick _1 output from the start circuit 11-1 becomes "1". Further, in the standby period P1 of the AD conversion circuit 20 immediately after the data value of the startup signal tkick _1 output from the startup circuit 11-1 becomes "1", the control circuit 30 sets the communication device 10-2 as the output destination of the digital data ts _ data when the data value of the lead-in signal catch _2 output from the startup circuit 11-2 becomes "1".

Further, as shown in fig. 16, the control circuit 30 sets the communication device 10-2 as the output target of the digital data ts _ data at the time point when the data value of the start signal tkick _2 output from the start circuit 11-2 becomes "1". Further, in the standby period P1 of the AD conversion circuit 20 immediately after the data value of the startup signal tkick _2 outputted from the startup circuit 11-2 becomes "1", the data value of the lead-in signal catch _1 outputted from the startup circuit 11-1 becomes "1", and the control circuit 30 sets the communication device 10-1 as the output destination of the digital data ts _ data.

Fig. 15 shows an example in which the data value of the start signal tkick _2 output from the start circuit 11-2 is "1" and the data value of the start signal tkick _1 output from the start circuit 11-1 is "1", but in fig. 16, when the data value of the start signal tkick _2 output from the start circuit 11-2 is "1" simultaneously with the data value of the start signal tkick _1 output from the start circuit 11-1 being "1", the control circuit 30 outputs the AD-converted digital data ts _ data to the register 12-1 as the lead-in data _1 and outputs the AD-converted digital data ts _ data to the register 12-2 as the lead-in data _ 2.

In the present embodiment, since the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2 as described above, the circuit scale and power consumption of the communication apparatus 100 can be reduced. Specifically, in the present embodiment, the AD conversion circuit 20 is shared by the two communication devices 10-1 and 10-2, compared to a configuration in which an analog circuit and an AD conversion circuit are provided for each communication device (that is, a configuration in which a plurality of analog circuits, a plurality of AD conversion circuits, and a plurality of communication devices are provided). By reducing the number of AD conversion circuits, the circuit area can be reduced. Further, by reducing the number of AD conversion circuits, power consumed by the plurality of AD conversion circuits can be reduced.

Further, the time required for reading out the digital data ts _ data can be shortened. Specifically, in this embodiment, not only one AD conversion circuit is shared, but also a control circuit that reads digital data in response to read request signals from a plurality of communication devices is provided. If the AD conversion circuit is shared, the operation of one communication device is completed and then the operation of the other communication device is started. As a result, the operation period of the AD conversion circuit needs to be equal to the number of communication devices. However, in the embodiment of the present application, the control circuit performs control as described above, thereby shortening the operation period of the AD conversion circuit 20.

Although the AD conversion circuit 20 is shared by two communication devices 10-1 and 10-2 in the above-described embodiment, the AD conversion circuit 20 may be shared by three or more communication devices.

Fig. 17 is a diagram showing a configuration example in which the AD conversion circuit is shared by six communication devices. Fig. 18 is a diagram showing an example of digital data output targets in the configuration example shown in fig. 17.

In the configuration example shown in fig. 17, as shown in example 1 of fig. 18, the communication device 10-1 outputs the start signal tkick _1, and the communication device 10-5 outputs the lead-in signal catch _5 in the standby period P1, and in this case, the control circuit 30 sets the communication device 10-1 and the communication device 10-5 as the output target of the digital data ts _ data.

In the configuration example shown in fig. 17, as shown in example 2 of fig. 18, the start signal tkick _4 is output from the communication device 10-4, the lead-in signal catch _1 is output from the communication device 10-1 in the standby period P1, and the lead-in signal catch _6 is output from the communication device 10-6, and in this case, the control circuit 30 sets the communication device 10-1, the communication device 10-4, and the communication device 10-6 as the output targets of the digital data ts _ data.

In the configuration example shown in fig. 17, as shown in example 3 of fig. 18, the boot signal tkick _2 is output from the communication device 10-2, the lead-in signal catch _3 is output from the communication device 10-3, and the lead-in signal catch _5 is output from the communication device 10-5 in the standby period P1, and in this case, the control circuit 30 sets the communication device 10-2, the communication device 10-3, and the communication device 10-5 as the output targets of the digital data ts _ data.

Further, in the configuration example shown in fig. 17, as shown in example 4 of fig. 18, the start signal tkick _5 is output from the communication device 10-5, the lead-in signal catch _1 is output from the communication device 10-1, the lead-in signal catch _2 is output from the communication device 10-2, and the lead-in signal catch _6 is output from the communication device 10-6 in the standby period P1, in which case the control circuit 30 sets the communication device 10-1, the communication device 10-2, the communication device 10-5, and the communication device 10-6 as the output target of the digital data ts _ data.

In the configuration example shown in fig. 17, as shown in example 5 of fig. 18, the start signal tkick _3 and the start signal tkick _6 are simultaneously output from the communication device 10-3 and the communication device 10-6, and in this case, the control circuit 30 sets the communication device 10-3 and the communication device 10-6 as the output target of the digital data ts _ data.

As described above, in the interface circuit 1 according to the embodiment, the AD conversion circuit 20 can be shared by a plurality of communication devices 10. This can reduce the circuit scale and power consumption of the communication device 100. In addition, the time required for reading data can be shortened.

The above embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention can be modified and improved without departing from the gist thereof, and the present invention also includes equivalents thereof.

The present disclosure may adopt the following configurations as described above or instead of the above.

(1) An interface circuit according to an aspect of the present invention includes: a plurality of communication devices; an AD conversion circuit for AD converting the analog signal into digital data; and a control circuit that reads out the digital data in accordance with read-out request signals from the plurality of communication devices.

In a configuration in which a plurality of communication devices are each provided with an AD conversion circuit, a consumption current of an amount corresponding to the plurality of AD conversion circuits is required. In the above configuration, the AD conversion circuit is shared by a plurality of communication devices. Thus, the circuit scale and power consumption of the interface circuit can be reduced as compared with a configuration in which an AD conversion circuit is provided for each of the plurality of communication devices.

(2) In the interface circuit of the above (1), the control circuit outputs the digital data to a first communication device among the plurality of communication devices when receiving a read request signal from the first communication device, and outputs the digital data to a second communication device different from the first communication device when receiving a read request signal from the second communication device.

In this configuration, the AD conversion circuit can be shared by a plurality of communication devices.

(3) In the interface circuit of the above (1), the AD conversion circuit needs a standby period after receiving a read request signal from a first communication device among the plurality of communication devices, and the control circuit outputs the digital data to a second communication device different from the first communication device when receiving a read request signal from the second communication device during the standby period.

If the AD conversion circuit is shared, the operation of one communication device is completed and then the operation of the other communication device is started. As a result, the operation period of the AD conversion circuit needs to be equal to the number of communication devices. In the interface circuit having the present configuration, the time required for reading data can be shortened by the above processing.

(4) In the interface circuit according to the above (1), the communication device includes: a communication interface for outputting a read instruction of the digital data; and a start circuit that generates, as the read request signal, a start signal for starting up the AD converter circuit or an introduction signal for introducing the digital data in accordance with the read instruction, wherein the communication device includes a first communication device and a second communication device different from the first communication device, and the start circuit of the second communication device outputs the introduction signal when the AD converter circuit needs a standby period after the start signal is output from the start circuit of the first communication device and the read instruction output from a communication interface of the second communication device is received during the standby period.

In this configuration, digital data is simultaneously output to both the communication device that outputs the start signal and the communication device that outputs the lead-in signal during the standby period. This can shorten the time required for reading data. Further, the circuit scale of the start-up circuit can be reduced.

(5) A communication device according to an aspect of the present invention includes: any one of the interface circuits of (1) to (4) above; a power amplifier circuit that amplifies the high-frequency signal; and a sensor that detects a temperature of the power amplifier circuit and outputs a detected value as the analog signal.

In an interface circuit having a configuration in which a plurality of communication devices are each provided with an AD conversion circuit, a consumption current of an amount corresponding to the plurality of AD conversion circuits is required. In the configuration using the interface circuit of the present configuration in which the AD conversion circuit is shared by a plurality of communication devices, the circuit scale and power consumption of the interface circuit can be reduced as compared with the configuration in which the AD conversion circuit is provided for each of the plurality of communication devices. Therefore, the circuit scale and power consumption of the communication device can be reduced. Further, if the AD conversion circuit is shared only, after the operation of one communication device is completed, the operation of the other communication device is started. As a result, the operation period of the AD conversion circuit needs to be equal to the number of communication devices. In the configuration using the interface circuit of this configuration, the time required for reading data can be shortened by the above processing.

According to the present disclosure, the circuit scale and power consumption can be reduced, and the time required for reading data can be shortened.

Claims

1. An interface circuit is provided with:

a plurality of communication devices;

an AD conversion circuit for AD converting the analog signal into digital data; and

and a control circuit for reading out the digital data in accordance with a read-out request signal from the plurality of communication devices.

2. The interface circuit of claim 1,

the control circuit outputs the digital data to a first communication device among the plurality of communication devices in a case where a read request signal is received from the first communication device,

the control circuit outputs the digital data to a second communication device different from the first communication device when receiving a read request signal from the second communication device.

3. The interface circuit of claim 1,

the control circuit outputs the digital data to a second communication device different from the first communication device when the AD conversion circuit requires a standby period after receiving a read request signal from the first communication device among the plurality of communication devices and receives a read request signal from the second communication device during the standby period.

4. The interface circuit of claim 1,

the communication device includes:

a communication interface for outputting a read instruction of the digital data; and

a start circuit that generates, as the read request signal, a start signal for starting the AD converter circuit or an introduction signal for introducing the digital data, based on the read command,

the communication device includes a first communication device and a second communication device different from the first communication device,

the AD conversion circuit needs a standby period after the start signal is output from the start circuit of the first communication device, and the start circuit of the second communication device outputs the lead-in signal when the read command output from the communication interface of the second communication device is received in the standby period.

5. A communication device is provided with:

the interface circuit of any one of claims 1 to 4;

a power amplifier circuit that amplifies the high-frequency signal; and

and a sensor that detects a temperature of the power amplifier circuit and outputs a detected value as the analog signal.