CN111313886B

CN111313886B - SR latch circuit based on interconnection line capacitance

Info

Publication number: CN111313886B
Application number: CN201911171038.4A
Authority: CN
Inventors: 张跃军; 赵志伟; 李林
Original assignee: Ningbo University
Current assignee: Ningbo University
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2023-04-28
Anticipated expiration: 2039-11-26
Also published as: CN111313886A

Abstract

The invention discloses an SR latch circuit based on interconnection line capacitance, which comprises a first NOR gate circuit and a second NOR gate circuit, wherein the first NOR gate circuit comprises a first node isolation module, a first capacitance adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first capacitance adjusting module comprises a third MOS tube and a fourth MOS tube, the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a P-type MOS tube, the second NOR gate circuit comprises a second node isolation module, a second capacitance adjusting module and a second sampling module, the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the second capacitance adjusting module comprises a ninth MOS tube and a tenth MOS tube, and the second sampling module comprises a seventh MOS tube and an eighth MOS tube; the advantage is that it has the ability to resist line crosstalk, and still can output correct logic signals when being disturbed by crosstalk noise.

Description

SR latch circuit based on interconnection line capacitance

Technical Field

The present invention relates to SR latch circuits, and more particularly, to an SR latch circuit based on interconnect line capacitance.

Background

Sequential logic can construct a finite state machine and be fused with combinational logic to construct a multi-functional integrated circuit. Sequential logic circuits have become a fundamental structure of today's integrated circuit development. The memory element is one of the most critical elements in the sequential logic circuit, and the SR latch circuit is the foundation for constructing various memory elements, so the SR latch circuit is studied deeply, and has profound significance for promoting the overall development of the integrated circuit.

As the spatial dimensions of metal interconnects in integrated circuits become smaller, problems, such as noise, are caused. The industry is to alleviate the trend of increasing resistance caused by smaller and smaller line widths of metal interconnect lines in integrated circuits, so that the aspect ratio of the metal interconnect lines is continuously increased along with the reduction of the process size. Increasing the vertical thickness of the metal interconnect increases the lateral capacitance, which results in a constant increase in the specific gravity of the multilayer intermetallic lateral capacitance to the total capacitance between the wires.

The conventional SR latch circuit is generally composed of two complementary CMOS nor gates, which are composed of two PMOS transistors and two NMOS transistors. When two complementary CMOS NOR gates are connected through a physical long-distance metal interconnection line, the space size of the metal interconnection line is smaller and smaller, so that the transverse capacitance between multiple layers of metals is increased, at the moment, the signals of the complementary CMOS NOR gates are extremely easy to be interfered by crosstalk noise to output wrong logic signals, so that the complementary CMOS NOR gates are abnormal in function, further, the SR latch circuit is abnormal in function, and finally, the integrated circuit is invalid.

Disclosure of Invention

The invention aims to provide an SR latch circuit based on interconnection line capacitance, which has the capacity of resisting line crosstalk and can still output correct logic signals when being interfered by crosstalk noise.

The technical scheme adopted for solving the technical problems is as follows: an SR latch circuit based on interconnection line capacitance comprises a first NOR gate circuit and a second NOR gate circuit, wherein the first NOR gate circuit comprises a first node isolation module, a first capacitance adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are N-type MOS tubes, the drain electrode of the first MOS tube is connected with a power supply, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the connecting end of the source electrode of the first MOS tube is the output end of the first node isolation module, the source electrode of the second MOS tube is grounded, the grid electrode of the first MOS tube, the substrate of the first MOS tube, the grid electrode of the second MOS tube and the substrate of the second MOS tube are all grounded, the first capacitance adjusting module comprises a third MOS tube and a fourth MOS tube, the third MOS tube and the fourth MOS tube are N-type MOS tubes, the grid electrode of the third MOS tube is connected with the grid electrode of the fourth MOS tube, the connecting end of the grid electrode of the third MOS tube is the output end of the first capacitance adjusting module, the output end of the first capacitance adjusting module is connected with the output end of the first node isolating module, the source electrode of the third MOS tube, the drain electrode of the third MOS tube is connected with the substrate of the third MOS tube, the connecting end of the third MOS tube is the first input end of the first capacitance adjusting module, the first input end of the first capacitance adjusting module is the first input end of the first NOR gate circuit, the source electrode of the fourth MOS tube, the drain electrode of the fourth MOS tube and the substrate of the fourth MOS tube are connected, the connecting end of the fourth MOS tube is the second input end of the first capacitance adjusting module, the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, and the channel length adjusting range of the fourth MOS tube is 400-550 nm; the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a P-type MOS tube, the sixth MOS tube is an N-type MOS tube, the source electrode of the fifth MOS tube is connected with a power supply, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the connecting end of the fifth MOS tube is an input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the connecting end of the drain electrode of the fifth MOS tube is the output end of the first sampling module, the substrate of the fifth MOS tube is connected with the power supply, the substrate of the sixth MOS tube is grounded, the channel width of the fifth MOS tube is 50-60 nm, the channel width of the sixth MOS tube is in the channel width adjustment range of 80-150 nm, and the channel width of the sixth MOS tube is in the channel adjustment range of 80-60 nm; the second NOR gate circuit comprises a second node isolation module, a second capacitance adjusting module and a second sampling module, wherein the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the eleventh MOS tube and the twelfth MOS tube are N-type MOS tubes, the drain electrode of the eleventh MOS tube is connected with a power supply, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, the connecting end of the source electrode of the eleventh MOS tube is the output end of the second node isolation module, the source electrode of the twelfth MOS tube is grounded, the grid electrode of the eleventh MOS tube and the substrate of the twelfth MOS tube are all grounded, the second capacitance adjusting module comprises a ninth MOS tube and a tenth MOS tube, the grid electrode of the ninth MOS tube and the tenth MOS tube are N-type MOS tubes, the grid electrode of the ninth MOS tube and the drain electrode of the tenth MOS tube are connected with the output end of the ninth MOS tube, the output end of the ninth MOS tube is connected with the output end of the ninth MOS tube, and the output end of the ninth MOS tube is connected with the output end of the ninth MOS tube; the first input end of the second capacitance value adjusting module is the first input end of the second NOR gate circuit, the source electrode of the tenth MOS tube, the drain electrode of the tenth MOS tube and the substrate of the tenth MOS tube are connected, the connecting end of the tenth MOS tube is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second NOR gate circuit, the channel width adjusting range of the ninth MOS tube is 300-450 nm, the channel length adjusting range of the ninth MOS tube is 400-550 nm, the channel width adjusting range of the tenth MOS tube is 300-450 nm, and the channel length adjusting range of the tenth MOS tube is 400-550 nm; the second sampling module comprises a seventh MOS tube and an eighth MOS tube, the seventh MOS tube is a P-type MOS tube, the eighth MOS tube is an N-type MOS tube, the source electrode of the seventh MOS tube is connected with a power supply, the substrate of the seventh MOS tube is connected with the power supply, the grid electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube and the connecting end of the seventh MOS tube is the input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube and the connecting end of the eighth MOS tube is the output end of the second sampling module, the substrate of the eighth MOS tube is grounded, the channel width adjustment range of the seventh MOS tube is 50-60 nm, the channel width adjustment range of the eighth MOS tube is 80-150 nm, and the channel length adjustment range of the eighth MOS tube is 80-150 nm. The second input end of the first NOR gate circuit is the first input end of the SR latch circuit, the first input end of the second NOR gate circuit is the second input end of the SR latch circuit, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the first output end of the SR latch circuit, and the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit, and the connecting end of the second NOR gate circuit is the second output end of the SR latch circuit.

Compared with the prior art, the invention has the advantages that the first NOR gate circuit is formed by the first node isolation module, the first capacitance adjusting module and the first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first capacitance adjusting module comprises a third MOS tube and a fourth MOS tube, the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the second node isolation module, the second capacitance adjusting module and the second sampling module form a second NOR gate circuit, the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the second capacitance adjusting module comprises a ninth MOS tube and a tenth MOS tube, and the second sampling module comprises a seventh MOS tube and an eighth MOS tube. When the distance between two metal wires is smaller or the longitudinal relative area of the metal layers of the interconnection wires is changed, the action degree of the interfered wire on the interfered wire is changed, and the coupling capacitance between the interfered wire and the interfered wire is changed, then the values of the channel width W and the channel length L of a third MOS tube M3, a fourth MOS tube M4, a ninth MOS tube M9 and a tenth MOS tube M10 in the first capacitance adjusting module and the second capacitance adjusting module are properly adjusted, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, the channel length adjusting range of the fourth MOS tube is 400-550 nm, the channel width adjusting range of the ninth MOS tube is 300-450 nm, the channel length adjusting range of the ninth MOS tube is 400-550 nm, the channel width adjusting range of the tenth MOS tube is 300-450 nm, the channel length adjustment range of the tenth MOS tube is 400-550 nm, meanwhile, in order to avoid the problem of overlarge voltage values generated at the output end of the first node isolation module and the output end of the second node isolation module, the channel width W and the channel length L of an inverter formed by properly adjusting the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are used for enabling the output end Q and the inverted output end Q' of the latch to output correct logic signals, the channel width adjustment range of the fifth MOS tube is 50-60 nm, the channel length adjustment range of the fifth MOS tube is 80-120 nm, the channel width adjustment range of the sixth MOS tube is 50-60 nm, the channel length adjustment range of the sixth MOS tube is 150-200 nm, the channel width adjustment range of the seventh MOS tube is 50-60 nm, the channel length adjustment range of the seventh MOS tube is 80-120 nm, the channel width adjustment range of the eighth MOS tube is 50-60 nm, the channel length adjusting range of the eighth MOS tube is 150-200 nm, after the silicon substrate and the grid electrode of the first MOS tube, the second MOS tube, the eleventh MOS tube and the twelfth MOS tube are grounded, the large resistor is respectively formed and then connected with the power supply VDD and the ground VSS in series, so as to simulate the VDD in an actual device to reach a disturbed metal wire through the SiO2 insulating medium layer, the first MOS tube, the second MOS tube, the eleventh MOS tube and the twelfth MOS tube are always in a closed state and only used for large resistor in the working process of the SR latch circuit, stable isolation conditions are provided for signal input connected into the first NOR gate circuit and the second NOR gate circuit, the third MOS tube, the fourth MOS tube, the ninth MOS tube and the tenth MOS tube in the first capacitance adjusting module and the second capacitance adjusting module adopt specific sizes to balance the influence of surrounding interference wires on the disturbed wire, the size of the coupling capacitance value is kept relatively stable, so that the first NOR gate circuit and the second NOR gate circuit work normally, and the two inverters formed by the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube enable low-level signals at the output end of the first node isolation module and the output end of the second node isolation module to be correctly identified and output correct NAND logic signals.

Drawings

FIG. 1 is a circuit diagram of an SR latch circuit based on interconnection line capacitance of the present invention;

FIG. 2 is a simulation graph of a first NOR gate circuit of the SR latch circuit based on interconnection line capacitance of the present invention;

FIG. 3 is a graph of a simulation of the delay of the falling edge of the output of the first NOR gate of the SR latch circuit based on interconnection line capacitance of the present invention;

FIG. 4 is a graph of a simulation of the delay of the rising edge of the output of the first NOR gate of the SR latch circuit based on interconnection line capacitance of the present invention;

FIG. 5 is a simulated graph of an SR latch circuit based on interconnect line capacitance in accordance with the present invention;

FIG. 6 is a graph of a simulation of the delay of the output of the first output of the SR latch circuit based on interconnect capacitance of the present invention with a falling edge;

FIG. 7 is a graph of a simulation of the delay of the output of the first output of the SR latch circuit based on the interconnection line capacitance.

Detailed Description

The invention is described in further detail below with reference to the embodiments of the drawings.

Examples: as shown in FIG. 1, the SR latch circuit based on interconnection line capacitance comprises a first NOR gate circuit and a second NOR gate circuit, wherein the first NOR gate circuit comprises a first node isolation module, a first capacitance adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube M1 and a second MOS tube M2, the first MOS tube M1 and the second MOS tube M2 are N-type MOS tubes, the drain electrode of the first MOS tube M1 is connected with a power supply, the source electrode of the first MOS tube M1 and the drain electrode of the second MOS tube M2 are connected and the connecting end of the source electrode of the first MOS tube M1 and the drain electrode of the second MOS tube M2 is the output end V1 of the first node isolation module, the source electrode of the second MOS tube M2 is grounded, and the grid electrode of the first MOS tube M1, the substrate of the first MOS tube M1 and the grid electrode of the second MOS tube M2The substrate of the electrode and the second MOS tube M2 are grounded, the first capacitance value adjusting module comprises a third MOS tube M3 and a fourth MOS tube M4, the third MOS tube M3 and the fourth MOS tube M4 are N-type MOS tubes, the grid electrode of the third MOS tube M3 and the grid electrode of the fourth MOS tube M4 are connected and the connecting end is the output end of the first capacitance value adjusting module, the output end of the first capacitance value adjusting module is connected with the output end of the first node isolation module, the source electrode of the third MOS tube M3, the drain electrode of the third MOS tube M3 and the substrate of the third MOS tube M3 are connected and the connecting end is the first input end of the first capacitance value adjusting module, the first input end of the first capacitance value adjusting module is the first input end of a first NOR gate circuit, the source electrode of the fourth MOS tube M4, the drain electrode of the fourth MOS tube M4 and the substrate of the fourth MOS tube M4 are connected, the connecting end of the source electrode of the fourth MOS tube M4 is the second input end of the first capacitance value adjusting module, the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS tube M3 is 450-550 nm, the channel length adjusting range of the third MOS tube M3 is 400-550 nm, the channel width adjusting range of the fourth MOS tube M4 is 300-450 nm, and the channel length adjusting range of the fourth MOS tube M4 is 400-550 nm; the first sampling module comprises a fifth MOS tube M5 and a sixth MOS tube M6, the fifth MOS tube M5 is a P-type MOS tube, the sixth MOS tube M6 is an N-type MOS tube, the source electrode of the fifth MOS tube M5 is connected with a power supply, the grid electrode of the fifth MOS tube M5 and the grid electrode of the sixth MOS tube M6 are connected and the connecting end of the fifth MOS tube M6 is an input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the sixth MOS tube M6 and the connecting end of the sixth MOS tube M6 is an output end of the first sampling module, the substrate of the first sampling module is connected with a power supply, the substrate of the sixth MOS tube M6 is grounded, the channel width adjustment range of the fifth MOS tube M5 is 50-60 nm, the channel length adjustment range of the sixth MOS tube M6 is 150-120 nm, the channel width adjustment range of the sixth MOS tube M6 is 50-60 nm, and the channel length adjustment range of the sixth MOS tube M6 is 150-200 nm; the second NOR gate circuit comprises a second node isolation module, a second capacitance adjusting module and a second sampling module, wherein the second node isolation module comprises an eleventh MOS tube M11 and a twelfth MOS tubeThe MOS tube M12, the eleventh MOS tube M11 and the twelfth MOS tube M12 are both N-type MOS tubes, the drain electrode of the eleventh MOS tube M11 is connected with the power supply, the source electrode of the eleventh MOS tube M11 is connected with the drain electrode of the twelfth MOS tube M12, the connecting end of the eleventh MOS tube M11 is the output end V2 of the second node isolation module, the source electrode of the twelfth MOS tube M12 is grounded, the grid electrode of the eleventh MOS tube M11, the substrate of the eleventh MOS tube M11, the grid electrode of the twelfth MOS tube M12 and the substrate of the twelfth MOS tube M12 are all grounded, the second capacitance adjusting module comprises a ninth MOS tube M9 and a tenth MOS tube M10, the grid electrode of the ninth MOS tube M9 and the tenth MOS tube M10 are both N-type MOS tubes, the grid electrode of the ninth MOS tube M9 and the grid electrode of the tenth MOS tube M10 are connected with the output end of the second capacitance adjusting module, the output end of the second capacitance adjusting module is connected with the output end of the second node isolation module, and the source electrode of the ninth MOS tube M9, the drain electrode of the ninth MOS tube M9 and the substrate of the ninth MOS tube M9 are connected with the input end of the ninth MOS tube M9; the first input end of the second capacitance value adjusting module is the first input end of a second NOR gate circuit, the source electrode of the tenth MOS tube M10, the drain electrode of the tenth MOS tube M10 and the substrate of the tenth MOS tube M10 are connected, the connecting end of the tenth MOS tube M10 is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second NOR gate circuit, the channel width adjusting range of the ninth MOS tube M9 is 300-450 nm, the channel length adjusting range of the ninth MOS tube M9 is 400-550 nm, the channel width adjusting range of the tenth MOS tube M10 is 300-450 nm, and the channel length adjusting range of the tenth MOS tube M10 is 400-550 nm; the second sampling module comprises a seventh MOS tube M7 and an eighth MOS tube M8, the seventh MOS tube M7 is a P-type MOS tube, the eighth MOS tube M8 is an N-type MOS tube, the source electrode of the seventh MOS tube M7 is connected with a power supply, the substrate of the seventh MOS tube M7 is connected with the power supply, the grid electrode of the seventh MOS tube M7 is connected with the grid electrode of the eighth MOS tube M8 and the connecting end of the grid electrode is an input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the eighth MOS tube M8 and the connecting end of the drain electrode is an output end of the second sampling module, the output end of the second sampling module is an output end of a second NOR gate circuit, the substrate of the eighth MOS tube M8 is grounded, the source electrode of the eighth MOS tube M8 is grounded, and the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the eighth MOS tube M7The channel width adjusting range is 50-60 nm, the channel length adjusting range of the seventh MOS tube M7 is 80-120 nm, the channel width adjusting range of the eighth MOS tube M8 is 50-60 nm, and the channel length adjusting range of the eighth MOS tube M8 is 150-200 nm. The second input end of the first NOR gate circuit is a first input end of the SR latch circuit, is connected with a first input signal S, the first input end of the second NOR gate circuit is a second input end of the SR latch circuit, is connected with a second input signal R, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit and the connection end of the second NOR gate circuit is a first output end of the SR latch circuit, a first output signal Q is output, the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit and the connection end of the second NOR gate circuit is a second output end of the SR latch circuit, and a second output signal Q is output ^’ 。

The first nor gate circuit of the SR latch circuit based on the interconnection line capacitance of the present invention is simulated, the simulation curve of which is shown in fig. 2, and it can be seen from analysis of fig. 2: at 2.5ns, s=0, Q' =0, and after the voltage signal is induced at node V, q=1 is obtained by sampling with a low-threshold inverter; at 3.5ns, s=1, Q' =1, generating 710mV of induced voltage at node V between high and low level signals, sampling with low threshold inverter to obtain q=0; at 4.5ns, s=0, Q' =1, the 490mV induced voltage at node V1 is sampled with a low threshold inverter to obtain q=0; at 5.5ns, s=1, Q' =0, and a 490mV induced voltage between the high and low level signals is generated at node V, sampled by a low threshold inverter, and shaped to q=0.

The delay of the first nor gate circuit output falling edge of the SR latch circuit based on the interconnection line capacitance is simulated, the delay simulation curve is shown in fig. 3, and the analysis of fig. 3 can be known: the fall delay time was 8.9ps.

The delay of the first nor gate circuit output rising edge of the SR latch circuit based on the interconnection line capacitance is simulated, the delay simulation curve is shown in fig. 4, and the analysis of fig. 4 can be known: the rise delay time of the output terminal is 10.8ps.

The SR latch circuit based on the interconnection line capacitance of the present invention is simulated, the simulation curve is shown in fig. 5, and it can be seen from analysis of fig. 5: at 3ns, r=0, s=0, and an induced voltage signal is generated at node V1, and q=0 is obtained after sampling by using a low threshold inverter; at 4.5ns, r=1, s=1, and the Q signal output is unstable after the induced voltage generated at node V1 is sampled by the low threshold inverter; at 7.5ns, r=0, s=1, the induced voltage is generated at node V1, and q=0 is obtained after sampling with a low threshold inverter; at 9ns, r=1, s=0, and the induced voltage at node V1 is sampled with a low threshold inverter to yield q=0.

The delay of the first output end of the SR latch circuit based on the interconnection line capacitance in the invention when outputting the falling edge is simulated, the delay simulation curve is shown in fig. 6, and the analysis of fig. 6 can be known: the falling delay time of the output end signal Q is 117.2ps; the fall delay time of the output terminal Q' is 117.2ps.

The delay of the first output end of the SR latch circuit based on the interconnection line capacitance in the invention when outputting the rising edge is simulated, the delay simulation curve is shown in fig. 7, and the analysis of fig. 7 can be known: the rising delay time of the output end signal Q is 55.9ps; the rise delay time of the output terminal Q' is 59.4ps.

Claims

1. The SR latch circuit based on interconnection line capacitance comprises a first NOR gate circuit and a second NOR gate circuit, and is characterized in that the first NOR gate circuit comprises a first node isolation module, a first capacitance adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are N-type MOS tubes, the drain electrode of the first MOS tube is connected with a power supply, the source electrode of the first MOS tube and the drain electrode of the second MOS tube are connected with the output end of the first MOS tube, the source electrode of the second MOS tube is grounded, the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the substrate of the second MOS tube are grounded, the first capacitance adjusting module comprises a third MOS tube and a fourth MOS tube, the third MOS tube and the drain electrode of the fourth MOS tube are connected with the output end of the first MOS tube, the output end of the first MOS tube is connected with the grid electrode of the first MOS tube, the output end of the second MOS tube is connected with the grid electrode of the first MOS tube is connected with the output end of the first MOS tube, the second MOS tube is connected with the first MOS tube is connected with the grid electrode of the second MOS tube, the second MOS tube is grounded, the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, and the channel length adjusting range of the fourth MOS tube is 450-550 nm; the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a P-type MOS tube, the sixth MOS tube is an N-type MOS tube, the source electrode of the fifth MOS tube is connected with a power supply, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the connecting end of the fifth MOS tube is an input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the connecting end of the drain electrode of the fifth MOS tube is the output end of the first sampling module, the substrate of the fifth MOS tube is connected with the power supply, the substrate of the sixth MOS tube is grounded, the channel width of the fifth MOS tube is 60nm, the channel width of the sixth MOS tube is in the channel width adjusting range of 80-150 nm, and the channel width of the sixth MOS tube is in the channel adjusting range of 80-150 nm; the second NOR gate circuit comprises a second node isolation module, a second capacitance adjusting module and a second sampling module, wherein the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the eleventh MOS tube and the twelfth MOS tube are N-type MOS tubes, the drain electrode of the eleventh MOS tube is connected with a power supply, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, the connecting end of the source electrode of the eleventh MOS tube is the output end of the second node isolation module, the source electrode of the twelfth MOS tube is grounded, the grid electrode of the eleventh MOS tube and the substrate of the twelfth MOS tube are all grounded, the second capacitance adjusting module comprises a ninth MOS tube and a tenth MOS tube, the grid electrode of the ninth MOS tube and the tenth MOS tube are N-type MOS tubes, the grid electrode of the ninth MOS tube and the drain electrode of the tenth MOS tube are connected with the output end of the ninth MOS tube, the output end of the ninth MOS tube is connected with the output end of the ninth MOS tube, and the output end of the ninth MOS tube is connected with the output end of the ninth MOS tube; the first input end of the second capacitance value adjusting module is the first input end of the second NOR gate circuit, the source electrode of the tenth MOS tube, the drain electrode of the tenth MOS tube and the substrate of the tenth MOS tube are connected, the connecting end of the tenth MOS tube is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second NOR gate circuit, the channel width adjusting range of the ninth MOS tube is 300-450 nm, the channel length adjusting range of the ninth MOS tube is 400-550 nm, the channel width adjusting range of the tenth MOS tube is 300-450 nm, and the channel length adjusting range of the tenth MOS tube is 400-550 nm; the second sampling module comprises a seventh MOS tube and an eighth MOS tube, the seventh MOS tube is a P-type MOS tube, the eighth MOS tube is an N-type MOS tube, the source electrode of the seventh MOS tube is connected with a power supply, the substrate of the seventh MOS tube is connected with the power supply, the grid electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube and the connection end of the seventh MOS tube is an input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube and the connection end of the eighth MOS tube is an output end of the second sampling module, the substrate of the eighth MOS tube is grounded, the channel width of the seventh MOS tube is 50-60 nm, the channel width of the eighth MOS tube is in the channel width adjustment range of 80-150 nm, and the channel width of the eighth MOS tube is in the channel adjustment range of 80-60 nm; the second input end of the first NOR gate circuit is the first input end of the SR latch circuit, the first input end of the second NOR gate circuit is the second input end of the SR latch circuit, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the first output end of the SR latch circuit, and the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit, and the connecting end of the second NOR gate circuit is the second output end of the SR latch circuit.