CN111312729B - Shared thin film transistor and display panel - Google Patents
Shared thin film transistor and display panel Download PDFInfo
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- CN111312729B CN111312729B CN202010127928.1A CN202010127928A CN111312729B CN 111312729 B CN111312729 B CN 111312729B CN 202010127928 A CN202010127928 A CN 202010127928A CN 111312729 B CN111312729 B CN 111312729B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention provides a shared thin film transistor and a display panel. The display panel comprises a shared thin film transistor, wherein the shared thin film transistor comprises a source electrode, a drain electrode, a floating electrode, a first active layer, a second active layer and a grid layer. The invention can make longer channel in the same width pixel size range by using the length of the shared thin film transistor channel as the sum of the length of the first channel region and the length of the second channel region, thereby increasing the channel length of the shared thin film transistor without increasing the pixel size, ensuring that the potential of the second display region is not too low under the condition of high mobility material, finally keeping the penetration rate and the visual angle good, and the display panel has the best display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shared thin film transistor and a display panel.
Background
Thin Film Transistors (TFTs) are widely used in driving active matrix liquid crystal displays.
As shown in fig. 1, a display panel 90 of 3TFT design has been developed for better display viewing angle. The display area of the display device is divided into a first display area 901 and a second display area 902, the first display area 901 is charged and kept at a potential by the main thin film transistor 91, the second display area 902 is charged and kept at a pull-down potential by the auxiliary thin film transistor 92 and the shared thin film transistor 93, and the potential kept by the second display area 902 is lower than that of the first display area 901. The potentials of the first display area 901 and the second display area 902 are maintained in a certain proportion, so that the best display effect, such as the transmittance and the viewing angle, can be achieved.
The amount of the potential held in the second display region 902 is directly related to the pull-down effect of the shared thin film transistor 93, and if the pull-down effect of the shared thin film transistor 93 is strong, the potential held in the second display region 902 is low, and the pull-down effect of the shared thin film transistor 93 is weak, which is the opposite. And the length and width of the channel of the shared tft 93 determine the magnitude of the pull-down effect of the shared tft 93.
With the development of the technology, the carrier transport layer material is upgraded, the amorphous silicon material is upgraded to the polysilicon material, and then the polysilicon material is upgraded to the Indium Gallium Zinc Oxide (IGZO), so that the electron mobility is gradually increased, the pixel size is smaller and smaller, and the resolution is increased. Therefore, the shared tft 93 needs to have a weaker pull-down effect to ensure that the potential maintained in the second display region 902 meets the requirement. Meanwhile, if the pull-down effect is too strong, the second display region 902 may have too low a voltage level and thus may have a low brightness. The pull-down effect of the shared tft 93 can be reduced by narrowing or lengthening the channel of the shared tft 93, but the narrowing of the channel requires a very high process requirement, and the lengthening of the channel is limited by the increasingly smaller pixel size, which is difficult to achieve.
Disclosure of Invention
An object of the present invention is to provide a common thin film transistor and a display panel, which can effectively solve the technical problems caused in the mask process.
In order to achieve the above object, the present invention provides a shared thin film transistor, which includes a source electrode, a drain electrode, a floating electrode, a first active layer, a second active layer, and a gate layer; specifically, the drain electrode is arranged away from the source electrode; one end of the floating electrode is arranged corresponding to the source electrode, the other end of the floating electrode is arranged corresponding to the drain electrode, a first channel region is formed between the floating electrode and the source electrode, and a second channel region is formed between the floating electrode and the drain electrode; the first active layer is arranged in the first channel region; the second active layer is arranged in the second channel region; the gate layer is disposed corresponding to the first active layer and the second active layer.
Further, the floating electrode is located between the source and the drain.
Further, the floating electrode is located on the same side of the source and the drain.
Further, the floating electrode is in a shape of one or a combination of a straight line, an arc and a fold line.
Further, when the floating electrode is arc-shaped, the floating electrode is disposed around the source electrode or the drain electrode.
Further, when the floating electrode is linear, the floating electrode is disposed in parallel with the source electrode or the drain electrode.
Furthermore, the first active layer and the second active layer are made of indium gallium zinc oxide.
To achieve the above object, the present invention further provides a display panel including the above-mentioned shared thin film transistor.
Further, the display panel further comprises a first display area and a second display area; the shared thin film transistor is positioned between the first display area and the second display area, the source electrode of the shared thin film transistor is connected with the first display area, and the drain electrode of the shared thin film transistor is connected with the second display area.
Further, the display panel further comprises a main thin film transistor and an auxiliary thin film transistor; the main thin film transistor is positioned between the first display area and the second display area, the drain electrode of the main thin film transistor is electrically connected with the data line, and the source electrode of the main thin film transistor is connected with the first display area; the auxiliary thin film transistor is positioned between the first display area and the second display area, the drain electrode of the auxiliary thin film transistor is electrically connected with the data line, and the source electrode of the auxiliary thin film transistor is connected with the second display area.
The invention has the technical effects that the length of the channel of the shared thin film transistor is the sum of the length of the first channel region and the length of the second channel region, and a longer channel can be formed within the range of the pixel size with the same width, so that the channel length of the shared thin film transistor can be increased on the premise of not increasing the pixel size, the potential of the second display region can be ensured not to be too low under the condition of a high-mobility material, the penetration rate and the visual angle are finally kept good, and the display panel has the best display effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic plan view of a conventional 3TFT display panel;
fig. 2 is a schematic plane structure diagram of the shared thin film transistor in embodiment 1 of the present invention;
fig. 3 is a schematic plan view of a shared thin film transistor in embodiment 2 of the present invention;
fig. 4 is a schematic plane structure diagram of the shared thin film transistor in embodiment 3 of the present invention;
fig. 5 is a schematic plane structure diagram of the shared thin film transistor in embodiment 4 of the present invention;
fig. 6 is a schematic plan view of a display panel according to an embodiment of the present invention.
Some of the symbols in the drawings are as follows:
1. a source electrode, 2, a drain electrode, 3, a floating electrode,
4. a first active layer, 5, a second active layer, 6, a gate layer,
10. a shared Thin Film Transistor (TFT), 11, a first channel region, 12, a second channel region,
20. a main thin film transistor, 30, a sub thin film transistor, 100, a display panel,
110. a first display area, 120, a second display area.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings for illustrating the invention and enabling those skilled in the art to fully describe the technical contents of the present invention so that the technical contents of the present invention can be more clearly and easily understood. The present invention may, however, be embodied in many different forms of embodiments and the scope of the present invention should not be construed as limited to the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the drawings, the thickness of layers and regions are exaggerated for clarity. For example, the thicknesses and sizes of elements in the drawings are arbitrarily shown for convenience of description, and thus, the described technical scope is not limited by the drawings.
Example 1
As shown in fig. 2, fig. 2 is a schematic plan view of a shared thin film transistor 10 according to embodiment 1 of the present invention, in which the shared thin film transistor 10 includes a source electrode 1, a drain electrode 2, a floating electrode 3, a first active layer 4, a second active layer 5, and a gate layer 6.
Specifically, the drain electrode 2 is disposed apart from the source electrode 1; one end of the floating electrode 3 is arranged corresponding to the source electrode 1, the other end of the floating electrode is arranged corresponding to the drain electrode 2, a first channel region 11 is formed between the floating electrode 3 and the source electrode 1, and a second channel region 12 is formed between the floating electrode 3 and the drain electrode 2; the first active layer 4 is arranged in the first channel region 11; the second active layer 5 is arranged in the second channel region 12; the gate layer 6 is disposed corresponding to the first active layer 4 and the second active layer 5.
In the embodiment, by using the principle that the length of the channel of the shared thin film transistor 10 is the sum of the length of the first channel region 11 and the length of the second channel region 12, the channel regions are arranged in segments, so that the shared thin film transistor 10 can be used as a longer channel within the same width of a pixel size range, the channel length of the shared thin film transistor 10 can be increased on the premise of not increasing the pixel size, the potential of a display area connected with the drain electrode 2 can be ensured not to be too low under the condition of a high-mobility material, and the penetration rate and the viewing angle of the display area can be kept good, so that the display effect is good.
The structure of the shared thin film transistor 10 is mainly aimed at making a larger width W in a smaller space, the specific form can be adjusted according to the length-width ratio W/L of the design requirement, the widths and lengths of the first channel region 11 and the second channel region 12 are not limited, that is, the widths and lengths of the first active layer 4 and the second active layer 5 are not limited, and can be changed according to the design requirement.
In this embodiment, the floating electrode 3 is located on the same side of the source 1 and the drain 2.
In this embodiment, the floating electrode 3 is linear, and the floating electrode 3 is disposed parallel to the source 1 or the drain 2.
In this embodiment, the first active layer 4 and the second active layer 5 are made of indium gallium zinc oxide, which is a carrier transport material with high electron mobility, so that the pixel size can be small, thereby increasing the resolution.
Example 2
As shown in fig. 3, most of the technical features of embodiment 1 are included in embodiment 2, which is different in that the floating electrode 3 in embodiment 2 is located between the source electrode 1 and the drain electrode 2, instead of the floating electrode 3 in embodiment 1 being located on the same side of the source electrode 1 and the drain electrode 2.
Example 3
As shown in fig. 4, most of the technical features of embodiment 1 are included in embodiment 3, which is different in that the floating electrode 3 in embodiment 3 has an arc shape, and the floating electrode 3 is disposed around the source electrode 1 or the drain electrode 2, instead of the floating electrode 3 in embodiment 1 having a straight line shape.
It should be noted that other variations of this embodiment may also adopt the distribution form in embodiment 2, that is, the floating electrode 3 in embodiment 3 is located between the source 1 and the drain 2, two ends of the floating electrode 3 are in two arcs, and the whole structure is in an S shape, instead of the floating electrode 3 in embodiment 1 being located on the same side of the source 1 and the drain 2.
Example 4
As shown in fig. 5, most of the technical features of embodiment 1 are included in embodiment 4, which is different in that the floating electrode 3 in embodiment 2 is located between the source electrode 1 and the drain electrode 2, instead of the floating electrode 3 in embodiment 1 being located on the same side of the source electrode 1 and the drain electrode 2.
Referring to fig. 5, the floating electrode 3 is a zigzag, linear and arc combined structure. One end of the floating electrode 3 is in a linear shape and is arranged corresponding to the source electrode 1, and the other end of the floating electrode is in an arc shape and is arranged corresponding to the drain electrode 2, or vice versa.
In this embodiment, when the floating electrode 3 is arc-shaped, the floating electrode 3 is disposed around the source 1 or the drain 2. When the floating electrode 3 is linear, the floating electrode 3 is disposed in parallel with the source electrode 1 or the drain electrode 2.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments, and the technical features of the respective embodiments that are emphasized in the foregoing embodiments may be combined with each other within the scope of the skilled person.
As shown in fig. 6, the present invention further provides a display panel 100 including the shared thin film transistor 10 described above.
As shown in fig. 6, in the present embodiment, the display panel 100 further includes a first display area 110 and a second display area 120; wherein the shared thin film transistor 10 is located between the first display region 110 and the second display region 120, a source 1 of the shared thin film transistor 10 is connected to the first display region 110 and connected to a common electrode, and a drain 2 of the shared thin film transistor 10 is connected to the second display region 120.
The embodiment utilizes the principle that the length of the channel of the shared thin film transistor 10 is the sum of the length of the first channel region 11 and the length of the second channel region 12, and the channel regions are arranged in sections, so that the shared thin film transistor 10 can be used as a longer channel within the range of the pixel size with the same width, the channel length of the shared thin film transistor 10 can be increased on the premise of not increasing the pixel size, and it can be ensured that the potential of the second display region 120 connected with the drain electrode 2 is pulled down not too low under the condition of a high-mobility material, so that the shared thin film transistor 10 has a weaker pull-down effect, the potential held by the second display region 120 meets the requirement, the phenomena that the potential of the second display region 120 is too low and the brightness is reduced due to the too strong pull-down effect of the shared thin film transistor 10 are avoided, and the penetration rate and the viewing angle of the shared thin film transistor are finally kept good, thereby having the best display effect.
In this embodiment, the display panel 100 further includes a main thin film transistor 20 and an auxiliary thin film transistor 30; the main thin film transistor 20 is located between the first display region 110 and the second display region 120, a drain thereof is electrically connected to a data line, and a source thereof is connected to the first display region 110; the sub thin film transistor 30 is located between the first display region 110 and the second display region 120, and has a drain electrically connected to the data line and a source connected to the second display region 120. Thus, the shared thin film transistor 10, the main thin film transistor 20 and the sub thin film transistor 30 form a display panel of a 3TFT design, which has a better display viewing angle.
The invention has the technical effects that the length of the channel of the shared thin film transistor is the sum of the length of the first channel region and the length of the second channel region, and a longer channel can be formed within the range of the pixel size with the same width, so that the channel length of the shared thin film transistor can be increased on the premise of not increasing the pixel size, the potential of the second display region can be ensured not to be too low under the condition of a high-mobility material, the penetration rate and the visual angle are finally kept good, and the display panel has the best display effect.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A shared thin film transistor, comprising:
a source electrode;
a drain electrode disposed apart from the source electrode;
the floating electrode is positioned on the same side of the source electrode and the drain electrode, one end of the floating electrode is arranged corresponding to the source electrode, the other end of the floating electrode is arranged corresponding to the drain electrode, a first channel region is formed between the floating electrode and the source electrode, and a second channel region is formed between the floating electrode and the drain electrode;
the first active layer is arranged in the first channel region;
a second active layer disposed in the second channel region; and
and the grid layer is arranged corresponding to the first active layer and the second active layer.
2. The shared thin film transistor of claim 1, wherein the floating electrode is one of a straight line shape, an arc shape, a folded line shape, or a combination thereof.
3. The shared thin film transistor of claim 2, wherein the floating electrode is disposed around the source electrode or the drain electrode when the floating electrode is in an arc shape.
4. The shared thin film transistor of claim 2, wherein the floating electrode is disposed in parallel with the source electrode or the drain electrode when the floating electrode is in a linear shape.
5. The shared thin film transistor of claim 1, wherein the first active layer and the second active layer comprise indium gallium zinc oxide.
6. A display panel comprising the shared thin film transistor of any one of claims 1-5.
7. The display panel according to claim 6, further comprising a first display region and a second display region;
the shared thin film transistor is positioned between the first display area and the second display area, the source electrode of the shared thin film transistor is connected with the first display area, and the drain electrode of the shared thin film transistor is connected with the second display area.
8. The display panel according to claim 7, characterized by further comprising:
the main thin film transistor is positioned between the first display area and the second display area, the drain electrode of the main thin film transistor is electrically connected with the data line, and the source electrode of the main thin film transistor is connected with the first display area; and
and the auxiliary thin film transistor is positioned between the first display area and the second display area, the drain electrode of the auxiliary thin film transistor is electrically connected with the data line, and the source electrode of the auxiliary thin film transistor is connected with the second display area.
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| CN202010127928.1A CN111312729B (en) | 2020-02-28 | 2020-02-28 | Shared thin film transistor and display panel |
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| CN202010127928.1A CN111312729B (en) | 2020-02-28 | 2020-02-28 | Shared thin film transistor and display panel |
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| CN111312729B true CN111312729B (en) | 2023-01-24 |
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| CN113325646A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Pixel structure and display panel with same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022157A (en) * | 2014-05-26 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and display device |
| CN107204375A (en) * | 2017-05-19 | 2017-09-26 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof |
| CN108363253A (en) * | 2018-02-09 | 2018-08-03 | 京东方科技集团股份有限公司 | Array substrate and its driving method and manufacturing method |
| CN109254460A (en) * | 2017-07-13 | 2019-01-22 | 三星显示有限公司 | Liquid crystal display |
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- 2020-02-28 CN CN202010127928.1A patent/CN111312729B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022157A (en) * | 2014-05-26 | 2014-09-03 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate and display device |
| CN107204375A (en) * | 2017-05-19 | 2017-09-26 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof |
| CN109254460A (en) * | 2017-07-13 | 2019-01-22 | 三星显示有限公司 | Liquid crystal display |
| CN108363253A (en) * | 2018-02-09 | 2018-08-03 | 京东方科技集团股份有限公司 | Array substrate and its driving method and manufacturing method |
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